#
### SIMD Copy, Insert, Move, Extract
#

code="dup v0.16b, w1" x1=q:5                  => v0=bbbbbbbbbbbbbbbb:5,5,5,5,5,5,5,5,5,5,5,5,5,5,5,5
code="dup v0.8h, w1"  x1=q:0xff00             => v0=wwwwwwww:0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00
code="dup v0.2s, w1"  x1=q:0xf00ff00f         => v0=llll:0xf00ff00f,0xf00ff00f,0,0
code="dup v0.2d, x1"  x1=q:0x1234567812345678 => v0=qq:0x1234567812345678,0x1234567812345678

code="dup b0, v1.b[15]" v1=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,42 => v0=qq:42,0
code="dup h0, v1.h[2]"  v1=wwwwwwww:0,0,0xff00,0,0,0,0,0                     => v0=qq:0xff00,0
code="dup s0, v1.s[2]"  v1=llll:0,0,0xf00ff00f,0                             => v0=qq:0xf00ff00f,0
code="dup d0, v1.d[1]"  v1=qq:0,0x1234567812345678                           => v0=qq:0x1234567812345678,0

code="dup v0.16b, v1.b[15]" v1=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,42 => v0=bbbbbbbbbbbbbbbb:42,42,42,42,42,42,42,42,42,42,42,42,42,42,42,42
code="dup v0.8b, v1.b[15]"  v1=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,42 => v0=bbbbbbbbq:42,42,42,42,42,42,42,42,0
code="dup v0.8h, v1.h[2]"   v1=wwwwwwww:0,0,0xff00,0,0,0,0,0,0                   => v0=wwwwwwww:0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00
code="dup v0.8h, v1.h[6]"   v1=wwwwwwww:0x1111,0x2222,0x3333,0x4444,0x5555,0x6666,0x7777,0x8888 => v0=wwwwwwww:0x7777,0x7777,0x7777,0x7777,0x7777,0x7777,0x7777,0x7777
code="dup v0.8h, v1.h[7]"   v1=wwwwwwww:0x1111,0x2222,0x3333,0x4444,0x5555,0x6666,0x7777,0x8888 => v0=wwwwwwww:0x8888,0x8888,0x8888,0x8888,0x8888,0x8888,0x8888,0x8888
code="dup v0.4h, v1.h[7]"   v1=wwwwwwww:0x1111,0x2222,0x3333,0x4444,0x5555,0x6666,0x7777,0x8888 => v0=wwwwq:0x8888,0x8888,0x8888,0x8888,0
code="dup v0.8h, v1.h[7]"   v1=wwwwwwww:0,0,0,0,0,0,0,0xff00                   => v0=wwwwwwww:0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00,0xff00
code="dup v0.4h, v1.h[7]"   v1=wwwwwwww:0,0,0,0,0,0,0,0xff00                   => v0=wwwwq:0xff00,0xff00,0xff00,0xff00,0
code="dup v0.4s, v1.s[2]"   v1=llll:0,0,0xf00ff00f,0                             => v0=llll:0xf00ff00f,0xf00ff00f,0xf00ff00f,0xf00ff00f
code="dup v0.2s, v1.s[3]"   v1=llll:0,0,0,0xf00ff00f                             => v0=llq:0xf00ff00f,0xf00ff00f,0
code="dup v0.2d, v1.d[1]"   v1=qq:0,0x1234567812345678                           => v0=qq:0x1234567812345678,0x1234567812345678

code="smov w0, v1.b[2]" v1=bbbbbbbbq:0,0,0xff,0,0,0,0,0,0  => x0=q:0xffffffff
code="smov w0, v1.h[2]" v1=wwwwwwww:0,0,0xffff,0,0,0,0,0   => x0=q:0xffffffff
code="smov x0, v1.s[2]" v1=llll:0,0,0xff00ff00,0,0         => x0=q:0xffffffffff00ff00
code="smov x0, v1.h[4]" v1=wwwwwwww:0,0,0,0,0xf00f,0,0,0,0 => x0=q:0xfffffffffffff00f

code="umov w0, v1.b[2]" v1=bbbbbbbbq:0,0,0xff,0,0,0,0,0,0  => x0=q:0xff
code="umov w0, v1.h[2]" v1=wwwwwwww:0,0,0xffff,0,0,0,0,0   => x0=q:0xffff
code="umov w0, v1.s[2]" v1=llll:0,0,0xff00ff00,0,0         => x0=q:0xff00ff00
code="umov x0, v1.d[1]" v1=qq:0,0xdeadbeef0000f00f         => x0=q:0xdeadbeef0000f00f

code="ins v0.b[15], w1" v0=qq:0,0 x1=q:5                  => v0=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,5
code="ins v0.h[2], w1"  v0=qq:0,0 x1=q:0xff00             => v0=wwwwwwww:0,0,0xff00,0,0,0,0,0
code="ins v0.s[2], w1"  v0=qq:0,0 x1=q:0xf00ff00f         => v0=llll:0,0,0xf00ff00f,0
code="ins v0.d[1], x1"  v0=qq:0,0 x1=q:0x1234567812345678 => v0=qq:0,0x1234567812345678

code="ins v0.b[13], v1.b[15]" v0=qq:0,0 v1=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,42 => v0=bbbbbbbbbbbbbbbb:0,0,0,0,0,0,0,0,0,0,0,0,0,42,0,0
code="ins v0.h[7], v1.h[2]"   v0=qq:0,0 v1=wwwwwwww:0,0,0xff00,0,0,0,0,0                     => v0=wwwwwwww:0,0,0,0,0,0,0,0xff00
code="ins v0.s[0], v1.s[2]"   v0=qq:0,0 v1=llll:0,0,0xf00ff00f,0                             => v0=llll:0xf00ff00f,0,0,0
code="ins v0.d[0], v1.d[1]"   v0=qq:0,0 v1=qq:0,0x1234567812345678                           => v0=qq:0x1234567812345678,0

code="ext v0.8b, v1.8b, v2.8b, #0" v0=qq:0,0 v1=bbbbbbbbq:1,2,3,4,5,6,7,8,0 v2=bbbbbbbbq:11,12,13,14,15,16,17,18,0 => v0=bbbbbbbbq:1,2,3,4,5,6,7,8,0
code="ext v0.8b, v1.8b, v2.8b, #3" v0=qq:0,0 v1=bbbbbbbbq:1,2,3,4,5,6,7,8,0 v2=bbbbbbbbq:11,12,13,14,15,16,17,18,0 => v0=bbbbbbbbq:4,5,6,7,8,11,12,13,0
code="ext v0.8b, v1.8b, v2.8b, #7" v0=qq:0,0 v1=bbbbbbbbq:1,2,3,4,5,6,7,8,0 v2=bbbbbbbbq:11,12,13,14,15,16,17,18,0 => v0=bbbbbbbbq:8,11,12,13,14,15,16,17,0
code="ext v0.16b, v1.16b, v2.16b, #13" v0=qq:0,0 v1=bbbbbbbbbbbbbbbb:1,2,3,4,5,6,7,8,9,10,11,12,13,14,15,16 v2=bbbbbbbbbbbbbbbb:11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26 => v0=bbbbbbbbbbbbbbbb:14,15,16,11,12,13,14,15,16,17,18,19,20,21,22,23,24,0,0

code="fmov v0.2s, #0.5"  v0=qq:0,0 => v0=ffll:0.5,0.5,0,0
code="fmov v0.4s, #1.0"  v0=qq:0,0 => v0=ffff:1.0,1.0,1.0,1.0
code="fmov v0.2d, #3.5"  v0=qq:0,0 => v0=dd:3.5,3.5

code="movi v0.4s, #0"                  => v0=qq:0,0
code="movi v0.4s, #4"                  => v0=llll:4,4,4,4
code="movi v0.4s, #0xf"                => v0=llll:0xf,0xf,0xf,0xf
code="movi v0.4s, #0x70, lsl #8"       => v0=llll:0x7000,0x7000,0x7000,0x7000
code="movi v0.4s, #0xf, msl #8"        => v0=llll:0xfff,0xfff,0xfff,0xfff
code="movi v0.2s, #0x80, lsl #16"      => v0=llll:0x800000,0x800000,0,0
code="movi v0.2s, #0x80, lsl #24"      => v0=llll:0x80000000,0x80000000,0,0
code="movi v0.16b, #1"                 => v0=bbbbbbbbbbbbbbbb:1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1
code="movi v0.8h, #1, lsl #8"          => v0=wwwwwwww:0x100,0x100,0x100,0x100,0x100,0x100,0x100,0x100
code="mvni v0.8h, #1, lsl #8"          => v0=wwwwwwww:0xfeff,0xfeff,0xfeff,0xfeff,0xfeff,0xfeff,0xfeff,0xfeff
code="movi v0.2s, #1, lsl #0"          => v0=llq:1,1,0
code="movi v0.2s, #1, lsl #8"          => v0=llq:0x100,0x100,0
code="movi v0.2s, #1, lsl #16"         => v0=llq:0x10000,0x10000,0
code="movi v0.2s, #1, lsl #24"         => v0=llq:0x1000000,0x1000000,0
code="mvni v0.2s, #1, lsl #24"         => v0=llq:0xfeffffff,0xfeffffff,0
code="movi v0.2s, #1, msl #8"          => v0=llq:0x1ff,0x1ff,0
code="movi v0.2s, #1, msl #16"         => v0=llq:0x1ffff,0x1ffff,0
code="movi d0, #0x00ff00ff00ff00ff"    => v0=qq:0x00ff00ff00ff00ff,0
code="movi d0, #0"                     => v0=qq:0,0
code="movi v0.2d, #0x00ff00ff00ff00ff" => v0=qq:0x00ff00ff00ff00ff,0x00ff00ff00ff00ff

code="xtn v0.2s, v1.2d"   v0=qq:0,0 v1=qq:0xffffffffffffffff,1 => v0=llq:0xffffffff,1,0
code="xtn2 v0.4s, v1.2d"  v0=qq:0,0 v1=qq:0xffffffffffffffff,1 => v0=qll:0,0xffffffff,1
code="xtn v0.4h, v1.4s"   v0=qq:0,0 v1=llll:0xffffffff,1,2,3   => v0=wwwwq:0xffff,1,2,3,0
code="xtn2 v0.8h, v1.4s"  v0=qq:0,0 v1=llll:0xffffffff,1,2,3   => v0=qwwww:0,0xffff,1,2,3
code="xtn v0.8b, v1.8h"   v0=qq:0,0 v1=wwwwwwww:0xffff,1,2,3,4,5,6,7 => v0=bbbbbbbbq:0xff,1,2,3,4,5,6,7,0
code="xtn2 v0.16b, v1.8h" v0=qq:0,0 v1=wwwwwwww:0xffff,1,2,3,4,5,6,7 => v0=qbbbbbbbb:0,0xff,1,2,3,4,5,6,7

#
### SIMD Zip/Unzip
#

# Examples from the manual. Note that we fill vectors left-to-right while the
# manual visualises the vectors with index 0 on the right.

code="zip1 v0.8b, v1.8b,v2.8b" v0=qq:0,0 v1=bbbbbbbbq:0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0 v2=bbbbbbbbq:0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0 => v0=bbbbbbbbq:0xa0,0xb0,0xa1,0xb1,0xa2,0xb2,0xa3,0xb3,0
code="zip2 v0.8b, v1.8b,v2.8b" v0=qq:0,0 v1=bbbbbbbbq:0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0 v2=bbbbbbbbq:0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0 => v0=bbbbbbbbq:0xa4,0xb4,0xa5,0xb5,0xa6,0xb6,0xa7,0xb7,0

code="uzp1 v0.8b, v1.8b,v2.8b" v0=qq:0,0 v1=bbbbbbbbq:0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0 v2=bbbbbbbbq:0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0 => v0=bbbbbbbbq:0xa0,0xa2,0xa4,0xa6,0xb0,0xb2,0xb4,0xb6,0
code="uzp2 v0.8b, v1.8b,v2.8b" v0=qq:0,0 v1=bbbbbbbbq:0xa0,0xa1,0xa2,0xa3,0xa4,0xa5,0xa6,0xa7,0 v2=bbbbbbbbq:0xb0,0xb1,0xb2,0xb3,0xb4,0xb5,0xb6,0xb7,0 => v0=bbbbbbbbq:0xa1,0xa3,0xa5,0xa7,0xb1,0xb3,0xb5,0xb7,0

#
### SIMD Table
#

# Table of values 0..n, so that tbl[i] = i; simple to test.
code="tbl v0.16b, { v1.16b }, v9.16b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v9=0f0e0d0c0b0a09080706050403020100 => v0=0f0e0d0c0b0a09080706050403020100
code="tbl v0.16b, { v1.16b, v2.16b }, v9.16b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v2=101112131415161718191a1b1c1d1e1f v9=08090a0b0c0d0e0f1011121314151617 => v0=08090a0b0c0d0e0f1011121314151617
code="tbl v0.16b, { v1.16b, v2.16b, v3.16b }, v9.16b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v2=101112131415161718191a1b1c1d1e1f v3=202122232425262728292a2b2c2d2e2f v9=08090a0b0c0d0e0f1011121314202122 => v0=08090a0b0c0d0e0f1011121314202122
code="tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v9.16b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v2=101112131415161718191a1b1c1d1e1f v3=202122232425262728292a2b2c2d2e2f v4=303132333435363738393a3b3c3d3e3f v9=08090a0b0c0d3d3e1011121314202122 => v0=08090a0b0c0d3d3e1011121314202122

# Test out of range behavior...
code="tbl v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v9.16b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v2=101112131415161718191a1b1c1d1e1f v3=202122232425262728292a2b2c2d2e2f v4=303132333435363738393a3b3c3d3e3f v9=ffffffffffffffffffffffffffffffff => v0=00000000000000000000000000000000
code="tbx v0.16b, { v1.16b, v2.16b, v3.16b, v4.16b }, v9.16b" v0=ffffffffffffffffffffffffffffffff v1=000102030405060708090a0b0c0d0e0f v2=101112131415161718191a1b1c1d1e1f v3=202122232425262728292a2b2c2d2e2f v4=303132333435363738393a3b3c3d3e3f v9=ffffffffffffffffffffffffffffffff => v0=ffffffffffffffffffffffffffffffff

# ... and finally, 8b mode.

code="tbl v0.8b, { v1.16b }, v9.8b" v0=qq:0,0 v1=000102030405060708090a0b0c0d0e0f v9=0f0e0d0c0b0a09080000000000000000 => v0=0f0e0d0c0b0a09080000000000000000

#
### SIMD Compare
#

code="fcmeq d0, d1, d2"          v0=qq:0,0 v1=dq:0.0,0 v2=dq:0.0,0           => v0=qq:-1,0
code="fcmeq d0, d1, #0.0"        v0=qq:0,0 v1=dq:1.0,0                       => v0=qq:0,0
code="fcmeq v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:1.0,0.0 v2=dd:0.0,0.0       => v0=qq:0,-1
code="fcmeq v0.2d, v1.2d, #0.0"  v0=qq:0,0 v1=dd:1.0,0.0                     => v0=qq:0,-1
code="fcmgt v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=ffq:1.0,0.0,0 v2=ffq:0.0,1.0,0 => v0=llq:-1,0,0
code="fcmge v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=ffq:1.0,0.0,0 v2=ffq:1.0,1.0,0 => v0=llq:-1,0,0
code="fcmle v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:1.0,0.0 v2=dd:0.0,0.0       => v0=qq:0,-1
code="fcmlt v0.2d, v1.2d, #0.0"  v0=qq:0,0 v1=dd:-10.0,0.0                   => v0=qq:-1,0

code="cmeq d0, d1, d2"          v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 => v0=qq:-1,0
code="cmeq d0, d1, #0"          v0=qq:0,0 v1=qq:1,0           => v0=qq:0,0
code="cmeq v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:1,0 v2=qq:0,0 => v0=qq:0,-1
code="cmeq v0.2d, v1.2d, #0"    v0=qq:0,0 v1=qq:1,0           => v0=qq:0,-1
code="cmgt v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:1,0,0 v2=llq:0,1,0 => v0=llq:-1,0,0
code="cmge v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:1,0,0 v2=llq:1,1,0 => v0=llq:-1,0,0
code="cmhi v0.4h, v1.4h, v2.4h" v0=qq:0,0 v1=wwwwq:34,0,1,2,0 v2=wwwwq:0,0,0,0,0 => v0=wwwwq:-1,0,-1,-1,0
code="cmhs v0.8b, v1.8b, v2.8b" v0=qq:0,0 v1=bbbbbbbbq:0,-1,2,3,4,5,6,7,0 v2=bbbbbbbbq:0,0,2,4,0,-1,0,0,0 => v0=bbbbbbbbq:-1,-1,-1,0,-1,0,-1,-1,0
code="cmle v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:1,0 v2=qq:0,0 => v0=qq:0,-1
code="cmlt v0.2d, v1.2d, #0"    v0=qq:0,0 v1=qq:-10,0         => v0=qq:-1,0

code="cmtst d0, d1, d2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 => v0=qq:0,0
code="cmtst d0, d1, d2" v0=qq:0,0 v1=qq:1,0 v2=qq:0,0 => v0=qq:0,0
code="cmtst d0, d1, d2" v0=qq:0,0 v1=qq:1,0 v2=qq:1,0 => v0=qq:-1,0
code="cmtst v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xff,0 v2=qq:0xff0,0xff0 => v0=qq:-1,0

#
### SIMD Reduce
#

# Scalar pairwise is really a simple reduce, not comparable to SIMD pairwise
+jit code="addp d0, v1.2d" v0=qq:0,0 v1=qq:0x1111111111111111,0xeeeeeeeeeeeeeeee => v0=qq:0xffffffffffffffff,0
code="faddp d0, v1.2d" v1=dd:1.5,99.25 => v0=dq:100.75,0
code="faddp s0, v1.2s" v1=ffq:1.5,99.25,0 => v0=flq:100.75,0,0
+jit code="fmaxp s0, v1.2s" v0=qq:0,0 v1=ffq:-1.0,1.0,0 => v0=flq:1.0,0,0
+jit code="fminp s0, v1.2s" v0=qq:0,0 v1=ffq:-1.0,1.0,0 => v0=flq:-1.0,0,0
+jit code="fmaxnmp s0, v1.2s" v0=qq:0,0 v1=ffq:-1.0,1.0,0 => v0=flq:1.0,0,0
+jit code="fminnmp s0, v1.2s" v0=qq:0,0 v1=ffq:-1.0,1.0,0 => v0=flq:-1.0,0,0
+jit code="fmaxp d0, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dq:1.0,0
+jit code="fminp d0, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dq:-1.0,0
+jit code="fmaxnmp d0, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dq:1.0,0
+jit code="fminnmp d0, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dq:-1.0,0

+jit code="addv s0, v1.4s" v0=qq:0,0 v1=llll:1,10,100,1000 => v0=qq:1111,0
+jit code="addv s0, v1.4s" v0=qq:0,0 v1=llll:0x11111111,0x11221122,0x23452345,0xf1234567 => v0=llll:0x369b8adf,0,0,0
+jit code="uminv h0, v1.8h" v1=wwwwwwww:0xffff,0xffff,0x1234,0x1234,0x1010,0x1010,0xabcd,0xabcd => v0=wwlq:0x1010,0,0,0
+jit code="uminv s0, v1.4s" v1=llll:0xffffffff,0x12341234,0x10101010,0xabcdabcd => v0=llll:0x10101010,0,0,0
+jit code="uminv s0, v1.4s" v0=qq:0,0 v1=llll:1,10,100,1000 => v0=qq:1,0
+jit code="umaxv h0, v1.4h" v0=qq:0,0 v1=wwwwq:1,10,100,1000,0 => v0=qq:1000,0
+jit code="sminv s0, v1.4s" v0=qq:0,0 v1=llll:-1,10,-100,1000 => v0=llq:-100,0,0
+jit code="smaxv s0, v1.4s" v0=qq:0,0 v1=llll:1,-10,100,-1000 => v0=llq:100,0,0

+jit code="fminv s0, v1.4s" v0=qq:0,0 v1=ffff:-100.4,-44004.3,1345.4,56677.0 => v0=flq:-44004.3,0,0
+jit code="fmaxv s0, v1.4s" v0=qq:0,0 v1=ffff:-100.4,-44004.3,1345.4,56677.0 => v0=flq:56677.0,0,0

#
### SIMD pairwise
#

code="addp v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=bbbbbbbbbbbbbbbb:1,99,2,98,3,97,4,96,5,95,6,94,7,93,8,92 v2=bbbbbbbbbbbbbbbb:1,99,2,98,3,97,4,96,5,95,6,94,7,93,8,92 => v0=bbbbbbbbbbbbbbbb:100,100,100,100,100,100,100,100,100,100,100,100,100,100,100,100
code="faddp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1,99,2,98 v2=ffff:1,99,2,98 => v0=ffff:100,100,100,100
code="addp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,2,98 v2=llll:1,99,2,98 => v0=llll:100,100,100,100

code="saddlp v0.1d, v1.2s" v0=qq:0,0 v1=llq:-1,-1,0 => v0=qq:-2,0
code="saddlp v0.2d, v1.4s" v1=llll:0x330c5eaf,0x9acbe865,0xd2485fa8,0x76be59b5 => v0=qq:0xffffffffcdd84714,0x4906b95d
code="uaddlp v0.1d, v1.2s" v0=qq:0,0 v1=llq:0xffffffff,0xffffffff,0 => v0=qq:0x1fffffffe,0
code="sadalp v0.1d, v1.2s" v0=qq:2,0 v1=llq:-1,-1,0 => v0=qq:0,0
code="uadalp v0.1d, v1.2s" v0=qq:2,0 v1=llq:0xffffffff,0xffffffff,0 => v0=qq:0x200000000,0

code="umaxp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,2,98 v2=llll:2,98,1,99 => v0=llll:99,98,98,99
code="uminp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,2,98 v2=llll:2,98,1,99 => v0=llll:1,2,2,1

code="uminp v0.16b, v0.16b, v0.16b" v0=612020636161657220696c2020666320 => v0=20206165202020202020616520202020
code="smaxp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,2,98 v2=llll:1,99,2,98 => v0=llll:99,98,99,98
code="sminp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,2,98 v2=llll:1,99,2,98 => v0=llll:1,2,1,2

# LLVM ERROR: Code generator does not support intrinsic function 'llvm.maximum.v4f32'!
# But cannot JIT either: on x86-64 hosts, there are no appropriate instructions, so FMIN and FMAX
# cannot be tested.
+jit code="fmaxp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.5,99.0,2.5,98.0 v2=ffff:1.5,99.0,2.5,98.0 => v0=ffff:99.0,98.0,99.0,98.0
+jit code="fminp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.5,99.0,2.5,98.0 v2=ffff:1.5,99.0,2.5,98.0 => v0=ffff:1.5,2.5,1.5,2.5
+jit code="fminp v0.2d, v1.2d, v2.2d" v1=dd:-100.4,-44004.3 v2=dd:1345.4,56677.0 => v0=dd:-44004.3,1345.4
+jit code="fmaxp v0.2d, v1.2d, v2.2d" v1=dd:-100.4,-44004.3 v2=dd:1345.4,56677.0 => v0=dd:-100.4,56677.0
+jit code="fmaxnmp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.5,99.0,2.5,98.0 v2=ffff:1.5,99.0,2.5,98.0 => v0=ffff:99.0,98.0,99.0,98.0
+jit code="fminnmp v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.5,99.0,2.5,98.0 v2=ffff:1.5,99.0,2.5,98.0 => v0=ffff:1.5,2.5,1.5,2.5

#
### SIMD Load/Store
#

# LD1/ST1 (mult. structures) -- 1..4 registers

code="ld1 {v0.16b}, [x1]" v0=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff => v0=00112233445566778899aabbccddeeff
code="ld1 {v0.16b}, [x1], #16" v0=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff => v0=00112233445566778899aabbccddeeff x1=q:0x200010
code="ld1 {v0.16b}, [x1], x2" v0=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=00112233445566778899aabbccddeeff => v0=00112233445566778899aabbccddeeff x1=q:0x200020
code="ld1 {v0.8b, v1.8b}, [x1]" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff => v0=bbbbbbbbq:0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0 v1=bbbbbbbbq:0x88,0x99,0xaa,0xbb,0xcc,0xdd,0xee,0xff,0
code="ld1 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1]" v29=qq:0,0 v30=qq:0,0 v31=qq:0,0 v0=qq:0,0 x1=q:0x200000 m200000=00000000000000001111111111111111222222222222222233333333333333334444444444444444555555555555555566666666666666667777777777777777 => v29=qq:0x0000000000000000,0x1111111111111111 v30=qq:0x2222222222222222,0x3333333333333333 v31=qq:0x4444444444444444,0x5555555555555555 v0=qq:0x6666666666666666,0x7777777777777777

code="st1 {v0.16b}, [x1]" v0=qq:0,0 x1=q:0x200000 v0=00112233445566778899aabbccddeeff m200000=00000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff
code="st1 {v0.16b}, [x1], #16" v0=qq:0,0 x1=q:0x200000 v0=00112233445566778899aabbccddeeff m200000=00000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff x1=q:0x200010
code="st1 {v0.16b}, [x1], x2" v0=qq:0,0 x1=q:0x200000 x2=q:0x20 v0=00112233445566778899aabbccddeeff m200000=00000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff x1=q:0x200020
code="st1 {v0.8b, v1.8b}, [x1]" v0=bbbbbbbbq:0x00,0x11,0x22,0x33,0x44,0x55,0x66,0x77,0 v1=bbbbbbbbq:0x88,0x99,0xaa,0xbb,0xcc,0xdd,0xee,0xff,0 x1=q:0x200000 m200000=00000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff
code="st1 {v29.2d, v30.2d, v31.2d, v0.2d}, [x1]" v29=qq:0x0000000000000000,0x1111111111111111 v30=qq:0x2222222222222222,0x3333333333333333 v31=qq:0x4444444444444444,0x5555555555555555 v0=qq:0x6666666666666666,0x7777777777777777 x1=q:0x200000 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00000000000000001111111111111111222222222222222233333333333333334444444444444444555555555555555566666666666666667777777777777777

# LD2/ST2 (mult. structures) -- 2 regs, with (de-)interleaving

code="ld2 {v0.16b, v1.16b}, [x1]" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff
code="ld2 {v0.16b, v1.16b}, [x1], #32" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff x1=q:0x200020
code="ld2 {v0.16b, v1.16b}, [x1], x2" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff x1=q:0x200020
code="ld2 {v0.8b, v1.8b}, [x1]" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff => v0=bbbbbbbbq:0x00,0x22,0x44,0x66,0x88,0xaa,0xcc,0xee,0 v1=bbbbbbbbq:0x11,0x33,0x55,0x77,0x99,0xbb,0xdd,0xff,0
code="ld2 {v31.2d, v0.2d}, [x1]" v31=qq:0,0 v0=qq:0,0 x1=q:0x200000 m200000=0000000000000000111111111111111122222222222222223333333333333333 => v31=qq:0x0000000000000000,0x2222222222222222 v0=qq:0x1111111111111111,0x3333333333333333

code="st2 {v0.16b, v1.16b}, [x1]" v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff x1=q:0x200000 m200000=0000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff
code="st2 {v0.16b, v1.16b}, [x1], #32" v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff x1=q:0x200000 m200000=0000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200020
code="st2 {v0.16b, v1.16b}, [x1], x2" v0=0022446688aaccee0022446688aaccee v1=1133557799bbddff1133557799bbddff x1=q:0x200000 x2=q:0x20 m200000=0000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200020
code="st2 {v0.8b, v1.8b}, [x1]" v0=bbbbbbbbq:0x00,0x22,0x44,0x66,0x88,0xaa,0xcc,0xee,0 v1=bbbbbbbbq:0x11,0x33,0x55,0x77,0x99,0xbb,0xdd,0xff,0 x1=q:0x200000 m200000=00000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff
code="st2 {v31.2d, v0.2d}, [x1]" v31=qq:0x0000000000000000,0x2222222222222222 v0=qq:0x1111111111111111,0x33333333333333333 x1=q:0x200000 m200000=0000000000000000000000000000000000000000000000000000000000000000 => m200000=0000000000000000111111111111111122222222222222223333333333333333

# LD3/ST3 (mult. structures) -- 3 regs, with (de-)interleaving

code="ld3 {v0.16b, v1.16b, v2.16b}, [x1]" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff
code="ld3 {v0.16b, v1.16b, v2.16b}, [x1], #48" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff x1=q:0x200030
code="ld3 {v0.16b, v1.16b, v2.16b}, [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 x2=q:0x30 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff x1=q:0x200030
code="ld3 {v0.8b, v1.8b, v2.8b}, [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 x2=q:0x30 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=00336699ccff22550000000000000000 v1=114477aadd0033660000000000000000 v2=225588bbee1144770000000000000000 x1=q:0x200030
code="ld3 {v31.2d, v0.2d, v1.2d}, [x1]" v31=qq:0,0 v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=000000000000000011111111111111112222222222222222333333333333333344444444444444445555555555555555 => v31=qq:0x0000000000000000,0x3333333333333333 v0=qq:0x1111111111111111,0x4444444444444444 v1=qq:0x2222222222222222,0x5555555555555555

code="st3 {v0.16b, v1.16b, v2.16b}, [x1]" v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff x1=q:0x200000 m200000=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff
code="st3 {v0.16b, v1.16b, v2.16b}, [x1], #48" v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff x1=q:0x200000 m200000=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200030
code="st3 {v0.16b, v1.16b, v2.16b}, [x1], x2"  v0=00336699ccff225588bbee114477aadd v1=114477aadd00336699ccff225588bbee v2=225588bbee114477aadd00336699ccff x1=q:0x200000 x2=q:0x30 m200000=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200030
code="st3 {v0.8b, v1.8b, v2.8b}, [x1], x2" v0=00336699ccff22550000000000000000 v1=114477aadd0033660000000000000000 v2=225588bbee1144770000000000000000 x1=q:0x200000 x2=q:0x30 m200000=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff0011223344556677 x1=q:0x200030
code="st3 {v31.2d, v0.2d, v1.2d}, [x1]" v31=qq:0x0000000000000000,0x3333333333333333 v0=qq:0x1111111111111111,0x4444444444444444 v1=qq:0x2222222222222222,0x5555555555555555 x1=q:0x200000 m200000=000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=000000000000000011111111111111112222222222222222333333333333333344444444444444445555555555555555

# LD4/ST4 (mult. structures) -- 4 regs, with (de-)interleaving

code="ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1]" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff
code="ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff x1=q:0x200040
code="ld4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 x2=q:0x40 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff x1=q:0x200040
code="ld4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 x2=q:0x40 m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff => v0=004488cc004488cc0000000000000000 v1=115599dd115599dd0000000000000000 v2=2266aaee2266aaee0000000000000000 v3=3377bbff3377bbff0000000000000000 x1=q:0x200040
code="ld4 {v31.2d, v0.2d, v1.2d, v2.2d}, [x1]" v31=qq:0,0 v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=00000000000000001111111111111111222222222222222233333333333333334444444444444444555555555555555566666666666666667777777777777777 => v31=qq:0x0000000000000000,0x4444444444444444 v0=qq:0x1111111111111111,0x5555555555555555 v1=qq:0x2222222222222222,0x6666666666666666 v2=qq:0x3333333333333333,0x7777777777777777

code="st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1]" v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff x1=q:0x200000 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff
code="st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], #64" v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff x1=q:0x200000 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200040
code="st4 {v0.16b, v1.16b, v2.16b, v3.16b}, [x1], x2" v0=004488cc004488cc004488cc004488cc v1=115599dd115599dd115599dd115599dd v2=2266aaee2266aaee2266aaee2266aaee v3=3377bbff3377bbff3377bbff3377bbff x1=q:0x200000 x2=q:0x40 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200040
code="st4 {v0.8b, v1.8b, v2.8b, v3.8b}, [x1], x2" v0=004488cc004488cc0000000000000000 v1=115599dd115599dd0000000000000000 v2=2266aaee2266aaee0000000000000000 v3=3377bbff3377bbff0000000000000000 x1=q:0x200000 x2=q:0x40 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00112233445566778899aabbccddeeff00112233445566778899aabbccddeeff x1=q:0x200040
code="st4 {v31.2d, v0.2d, v1.2d, v2.2d}, [x1]" v31=qq:0x0000000000000000,0x4444444444444444 v0=qq:0x1111111111111111,0x5555555555555555 v1=qq:0x2222222222222222,0x6666666666666666 v2=qq:0x3333333333333333,0x7777777777777777 x1=q:0x200000 m200000=00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000 => m200000=00000000000000001111111111111111222222222222222233333333333333334444444444444444555555555555555566666666666666667777777777777777

# LD1, LD2, LD3, LD4 (single-struct)

code="ld1 {v0.b}[3], [x1]"     v0=qq:0,0 x1=q:0x200000 m200000=11 => v0=00000011000000000000000000000000
code="ld1 {v0.b}[3], [x1], #1" v0=qq:0,0 x1=q:0x200000 m200000=11 => v0=00000011000000000000000000000000 x1=q:0x200001
code="ld1 {v0.d}[1], [x1], x2" v0=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=0011223344556677 => v0=00000000000000000011223344556677 x1=q:0x200020

code="ld2 {v0.b, v1.b}[3], [x1]" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=1122 => v0=00000011000000000000000000000000 v1=00000022000000000000000000000000
code="ld2 {v0.s, v1.s}[2], [x1], #8" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd => v0=00000000000000000011223300000000 v1=0000000000000000aabbccdd00000000 x1=q:0x200008
code="ld2 {v0.d, v1.d}[1], [x1], x2" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=00112233445566770011223344556677 => v0=00000000000000000011223344556677 v1=00000000000000000011223344556677 x1=q:0x200020

code="ld3 {v0.b, v1.b, v2.b}[3], [x1]"      v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=112233 => v0=00000011000000000000000000000000 v1=00000022000000000000000000000000  v2=00000033000000000000000000000000
code="ld3 {v0.s, v1.s, v2.s}[2], [x1], #12" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd00112233 => v0=00000000000000000011223300000000 v1=0000000000000000aabbccdd00000000 v2=00000000000000000011223300000000 x1=q:0x20000c
code="ld3 {v0.d, v1.d, v2.d}[0], [x1], x2"  v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=001122334455667700112233445566770011223344556677 => v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 x1=q:0x200020

code="ld4 {v0.b, v1.b, v2.b, v3.b}[15], [x1]"      v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=11223344 => v0=00000000000000000000000000000011 v1=00000000000000000000000000000022 v2=00000000000000000000000000000033  v3=00000000000000000000000000000044
code="ld4 {v0.s, v1.s, v2.s, v3.s}[0], [x1], #16" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd00112233aabbccdd => v0=00112233000000000000000000000000 v1=aabbccdd000000000000000000000000 v2=00112233000000000000000000000000 v3=aabbccdd000000000000000000000000 x1=q:0x200010
code="ld4 {v31.d, v0.d, v1.d, v2.d}[0], [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v31=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=0011223344556677001122334455667700112233445566770011223344556677 => v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 v31=00112233445566770000000000000000 x1=q:0x200020

# LD1R, LD2R, LD3R, LD4R

code="ld1r {v0.8b}, [x1]"      v0=qq:0,0 x1=q:0x200000 m200000=11 => v0=11111111111111110000000000000000
code="ld1r {v0.16b}, [x1], #1" v0=qq:0,0 x1=q:0x200000 m200000=11 => v0=11111111111111111111111111111111 x1=q:0x200001
code="ld1r {v0.1d}, [x1], x2"  v0=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=0011223344556677 => v0=00112233445566770000000000000000 x1=q:0x200020

code="ld2r {v0.8b, v1.8b}, [x1]"     v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=1122 => v0=11111111111111110000000000000000 v1=22222222222222220000000000000000
code="ld2r {v0.2s, v1.2s}, [x1], #8" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd => v0=00112233001122330000000000000000 v1=aabbccddaabbccdd0000000000000000 x1=q:0x200008
code="ld2r {v0.1d, v1.1d}, [x1], x2" v0=qq:0,0 v1=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=00112233445566770011223344556677 => v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 x1=q:0x200020

code="ld3r {v0.8b, v1.8b, v2.8b}, [x1]"      v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=112233 => v0=11111111111111110000000000000000 v1=22222222222222220000000000000000  v2=33333333333333330000000000000000
code="ld3r {v0.2s, v1.2s, v2.2s}, [x1], #12" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd00112233 => v0=00112233001122330000000000000000 v1=aabbccddaabbccdd0000000000000000 v2=00112233001122330000000000000000 x1=q:0x20000c
code="ld3r {v0.1d, v1.1d, v2.1d}, [x1], x2"  v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=001122334455667700112233445566770011223344556677 => v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 x1=q:0x200020

code="ld4r {v0.8b, v1.8b, v2.8b, v3.8b}, [x1]"      v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=11223344 => v0=11111111111111110000000000000000 v1=22222222222222220000000000000000 v2=33333333333333330000000000000000  v3=44444444444444440000000000000000
code="ld4r {v0.2s, v1.2s, v2.2s, v3.2s}, [x1], #16" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v3=qq:0,0 x1=q:0x200000 m200000=00112233aabbccdd00112233aabbccdd => v0=00112233001122330000000000000000 v1=aabbccddaabbccdd0000000000000000 v2=00112233001122330000000000000000 v3=aabbccddaabbccdd0000000000000000 x1=q:0x200010
code="ld4r {v31.1d, v0.1d, v1.1d, v2.1d}, [x1], x2" v0=qq:0,0 v1=qq:0,0 v2=qq:0,0 v31=qq:0,0 x1=q:0x200000 x2=q:0x20 m200000=0011223344556677001122334455667700112233445566770011223344556677 => v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 v31=00112233445566770000000000000000 x1=q:0x200020

# ST1, ST2, ST3, ST4 (single-struct)

code="st1 {v0.b}[3], [x1]"     v0=00000011000000000000000000000000 x1=q:0x200000 m200000=00 => m200000=11
code="st1 {v0.b}[3], [x1], #1" v0=00000011000000000000000000000000 x1=q:0x200000 m200000=00 => m200000=11 x1=q:0x200001
code="st1 {v0.d}[1], [x1], x2" v0=00000000000000000011223344556677 x1=q:0x200000 x2=q:0x20 m200000=0000000000000000 => m200000=0011223344556677 x1=q:0x200020

code="st2 {v0.b, v1.b}[3], [x1]"     v0=00000011000000000000000000000000 v1=00000022000000000000000000000000 x1=q:0x200000 m200000=0000 => m200000=1122
code="st2 {v0.s, v1.s}[2], [x1], #8" v0=00000000000000000011223300000000 v1=0000000000000000aabbccdd00000000 x1=q:0x200000 m200000=0000000000000000 => m200000=00112233aabbccdd x1=q:0x200008
code="st2 {v0.d, v1.d}[1], [x1], x2" v0=00000000000000000011223344556677 v1=00000000000000000011223344556677 x1=q:0x200000 x2=q:0x20 m200000=00000000000000000000000000000000 => m200000=00112233445566770011223344556677 x1=q:0x200020

code="st3 {v0.b, v1.b, v2.b}[3], [x1]"      v0=00000011000000000000000000000000 v1=00000022000000000000000000000000 v2=00000033000000000000000000000000 x1=q:0x200000 m200000=000000 => m200000=112233
code="st3 {v0.s, v1.s, v2.s}[2], [x1], #12" v0=00000000000000000011223300000000 v1=0000000000000000aabbccdd00000000 v2=00000000000000000011223300000000 x1=q:0x200000 m200000=000000000000000000000000 => m200000=00112233aabbccdd00112233 x1=q:0x20000c
code="st3 {v0.d, v1.d, v2.d}[0], [x1], x2"  v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 x1=q:0x200000 x2=q:0x20 m200000=000000000000000000000000000000000000000000000000 => m200000=001122334455667700112233445566770011223344556677 x1=q:0x200020

code="st4 {v0.b, v1.b, v2.b, v3.b}[15], [x1]"     v0=00000000000000000000000000000011 v1=00000000000000000000000000000022 v2=00000000000000000000000000000033  v3=00000000000000000000000000000044 x1=q:0x200000 m200000=00000000 => m200000=11223344
code="st4 {v0.s, v1.s, v2.s, v3.s}[0], [x1], #16" v0=00112233000000000000000000000000 v1=aabbccdd000000000000000000000000 v2=00112233000000000000000000000000 v3=aabbccdd000000000000000000000000 x1=q:0x200000 m200000=0000000000000000000000000000000000000000 => m200000=00112233aabbccdd00112233aabbccdd x1=q:0x200010
code="st4 {v31.d, v0.d, v1.d, v2.d}[0], [x1], x2" v0=00112233445566770000000000000000 v1=00112233445566770000000000000000 v2=00112233445566770000000000000000 v31=00112233445566770000000000000000 x1=q:0x200000 x2=q:0x20 m200000=0000000000000000000000000000000000000000000000000000000000000000 => m200000=0011223344556677001122334455667700112233445566770011223344556677 x1=q:0x200020

#
### Bit Manipulation
#

code="bsl v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=00ff00ff00ff00ff00ff00ff00ff00ff
code="bsl v0.16b, v1.16b, v2.16b" v0=ff00ff00ff00ff00ff00ff00ff00ff00 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=01ff03ff05ff07ff09ff0bff0dff0fff
code="bsl v0.16b, v1.16b, v2.16b" v0=ffffffffffffffffffffffffffffffff v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=0102030405060708090a0b0c0d0e0f10
code="bit v0.16b, v1.16b, v2.16b" v0=f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0 v1=01010101010101010101010101010101 v2=000f000f000f000f000f000f000f000f => v0=f0f1f0f1f0f1f0f1f0f1f0f1f0f1f0f1
code="bif v0.16b, v1.16b, v2.16b" v0=f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0 v1=01010101010101010101010101010101 v2=000f000f000f000f000f000f000f000f => v0=01000100010001000100010001000100

code="and v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=bbbbbbbbbbbbbbbb:0,2,0,4,0,6,0,8,0,10,0,12,0,14,0,16
code="bic v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=bbbbbbbbbbbbbbbb:1,0,3,0,5,0,7,0,9,0,11,0,13,0,15,0
code="bic v0.2s, #0xff" v0=llll:0x11223344,0x11223344,0,0 => v0=llll:0x11223300,0x11223300,0,0

code="orr v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=01ff03ff05ff07ff09ff0bff0dff0fff
code="orr v0.2s, #0xff" v0=qq:0,0 => v0=llll:0xff,0xff,0,0
code="orn v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=ff02ff04ff06ff08ff0aff0cff0eff10

code="eor v0.16b, v1.16b, v2.16b" v0=qq:0,0 v1=0102030405060708090a0b0c0d0e0f10 v2=00ff00ff00ff00ff00ff00ff00ff00ff => v0=01fd03fb05f907f709f50bf30df10fef

code="not v0.16b, v1.16b" v0=qq:0,0 v1=0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f => v0=f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0f0

# JIT because of LLVM Interpreter Bug: llvm.ctlz(i32 0x0000000f) returns 56 instead of the expected 28.
+jit code="clz v0.2s, v1.2s" v0=qq:0,0 v1=llll:0x0000000f,0x000000f0,0,0 => v0=llll:28,24,0,0

# JIT because of LLVM Interpreter Bug: llvm.ctpop.i8(i8 0xff) returns 64 instead of the expected 8.
+jit code="cnt v0.8b, v1.8b" v0=qq:0,0 v1=bbbbbbbbq:0,0,0xff,0,0xf0,0,0,0,0 => v0=bbbbbbbbq:0,0,8,0,4,0,0,0,0
+jit code="cnt v0.8b, v1.8b" v1=bbbbbbbbq:0x1b,0x23,0x00,0x3f,0x12,0xff,0x7f,0x81,0 => v0=bbbbbbbbq:4,3,0,6,2,8,7,2,0
+jit code="cnt v0.8b, v1.8b" v1=bbbbbbbbq:0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0 => v0=bbbbbbbbq:8,8,8,8,8,8,8,8,0
+jit code="cnt v0.8b, v1.8b" v1=bbbbbbbbq:0,0,0,0,0,0,0,0,0 => v0=bbbbbbbbq:0,0,0,0,0,0,0,0,0
+jit code="cnt v0.8b, v1.8b; addv b0, v0.8b" v1=bbbbbbbbq:0xff,0xff,0xff,0xff,0xff,0xff,0xff,0xff,0 => v0=qq:64,0
+jit code="cnt v0.8b, v1.8b; addv b0, v0.8b" v1=bbbbbbbbq:0x1b,0x23,0x00,0x3f,0x12,0xff,0x7f,0x81,0 => v0=qq:32,0
+jit code="cnt v0.16b, v1.16b" v1=387ab72db443b9c6a4ccb7a2802026de => v0=bbbbbbbbbbbbbbbb:3,5,6,4,4,3,5,4,3,4,6,3,1,1,3,6

+jit code="rbit v0.8b, v1.8b" v0=qq:0,0 v1=bbbbbbbbq:1,2,3,4,5,6,7,8,0 => v0=bbbbbbbbq:0x80,0x40,0xc0,0x20,0xa0,0x60,0xe0,0x10,0

code="rev16 v0.16b, v1.16b" v0=qq:0,0 v1=00112233445566778899aabbccddeeff => v0=11003322554477669988bbaaddccffee
code="rev16 v0.8b, v1.8b"   v0=qq:0,0 v1=00112233445566778899aabbccddeeff => v0=11003322554477660000000000000000
code="rev32 v0.16b, v1.16b" v0=qq:0,0 v1=00112233445566778899aabbccddeeff => v0=3322110077665544bbaa9988ffeeddcc
code="rev32 v0.8h, v1.8h"   v0=qq:0,0 v1=00001111222233334444555566667777 => v0=11110000333322225555444477776666
code="rev32 v0.4h, v1.4h"   v0=qq:0,0 v1=00001111222233334444555566667777 => v0=11110000333322220000000000000000
code="rev64 v0.16b, v1.16b" v0=qq:0,0 v1=00112233445566778899aabbccddeeff => v0=7766554433221100ffeeddccbbaa9988
code="rev64 v0.8h, v1.8h"   v0=qq:0,0 v1=00001111222233334444555566667777 => v0=33332222111100007777666655554444
code="rev64 v0.4s, v1.4s"   v0=qq:0,0 v1=00000000111111112222222233333333 => v0=11111111000000003333333322222222
code="rev64 v0.2s, v1.2s"   v0=qq:0,0 v1=00000000111111112222222233333333 => v0=11111111000000000000000000000000
#
### SIMD Integer Arithmetic
#

code="abs d0, d1" v0=qq:0,0 v1=qq:-100,-10 => v0=qq:100,0
code="abs v0.4s, v1.4s" v0=qq:0,0 v1=llll:0,-100,3455,-2220 => v0=llll:0,100,3455,2220

code="sabd v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:-1,-1,0 v2=llq:-10,0x80000000,0 => v0=llq:9,0x7fffffff,0
code="uabd v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:100,0,0 v2=llq:1,0x80000000,0   => v0=llq:99,0x80000000,0

code="saba v0.2s, v1.2s, v2.2s" v0=llq:-10,1,0 v1=llq:-1,-1,0 v2=llq:-10,0x80000000,0 => v0=llq:-1,0x80000000,0
code="uaba v0.2s, v1.2s, v2.2s" v0=llq:1,1,0 v1=llq:100,0,0 v2=llq:1,0x80000000,0     => v0=llq:100,0x80000001,0

code="sabdl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0x80000000,1,0 v2=llq:0x7fffffff,-1,0 => v0=qq:0xffffffff,2
code="sabal v0.2d, v1.2s, v2.2s"  v0=qq:1,-2 v1=llq:0x80000000,1,0 v2=llq:0x7fffffff,-1,0 => v0=qq:0x100000000,0
code="sabdl2 v0.2d, v1.4s, v2.4s"  v0=qq:0,0 v1=qll:0,0x80000000,1 v2=qll:0,0x7fffffff,-1 => v0=qq:0xffffffff,2
code="sabal2 v0.2d, v1.4s, v2.4s"  v0=qq:1,-2 v1=qll:0,0x80000000,1 v2=qll:0,0x7fffffff,-1 => v0=qq:0x100000000,0

code="uabdl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0x80000000,1,0 v2=llq:0x7fffffff,-1,0 => v0=qq:1,0xfffffffe
code="uabal v0.2d, v1.2s, v2.2s"  v0=qq:1,-2 v1=llq:0x80000000,1,0 v2=llq:0x7fffffff,-1,0 => v0=qq:2,0xfffffffc
code="uabdl2 v0.2d, v1.4s, v2.4s"  v0=qq:0,0 v1=qll:0,0x80000000,1 v2=qll:0,0x7fffffff,-1 => v0=qq:1,0xfffffffe
code="uabal2 v0.2d, v1.4s, v2.4s"  v0=qq:1,-2 v1=qll:0,0x80000000,1 v2=qll:0,0x7fffffff,-1 => v0=qq:2,0xfffffffc

code="neg d0, d1" v0=qq:0,0 v1=qq:-100,100 => v0=qq:100,0
code="neg v0.4s, v1.4s" v0=qq:0,0 v1=llll:0,-100,3455,-2220 => v0=llll:0,100,-3455,2220

code="add d0, d1, d2" v0=qq:0,0 v1=qq:100,0 v2=qq:1,0 => v0=qq:101,0
code="add v0.8b, v1.8b, v2.8b" v0=qq:0,0 v1=bbbbbbbbq:100,0,-128,255,0,0,0,1,0 v2=bbbbbbbbq:100,-123,-1,1,0,0,0,0,0 => v0=bbbbbbbbq:200,-123,127,0,0,0,0,1,0

code="saddl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:-1,1,0 v2=llq:-1,-1,0 => v0=qq:-2,0
code="saddl2 v0.2d, v1.4s, v2.4s" v0=qq:0,0 v1=qll:0,-1,1 v2=qll:0,-1,-1 => v0=qq:-2,0
code="uaddl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0xffffffff,1,0 v2=llq:1,0xffffffff,0 => v0=qq:0x100000000,0x100000000
code="uaddl2 v0.2d, v1.4s, v2.4s" v0=qq:0,0 v1=qll:0,0xffffffff,1 v2=qll:0,1,0xffffffff => v0=qq:0x100000000,0x100000000

code="saddw v0.2d, v1.2d, v2.2s"  v0=qq:0,0 v1=qq:-1,1 v2=llq:-1,-1,0 => v0=qq:-2,0
code="saddw2 v0.2d, v1.2d, v2.4s" v0=qq:0,0 v1=qq:-1,1 v2=qll:0,-1,-1 => v0=qq:-2,0
code="uaddw v0.2d, v1.2d, v2.2s"  v0=qq:0,0 v1=qq:0xf000000000000000,1 v2=llq:0xffffffff,0xffffffff,0 => v0=qq:0xf0000000ffffffff,0x100000000
code="uaddw2 v0.2d, v1.2d, v2.4s" v0=qq:0,0 v1=qq:0xf000000000000000,1 v2=qll:0,0xffffffff,0xffffffff => v0=qq:0xf0000000ffffffff,0x100000000

# Corner case: -1 + (-2^31) would overflow, but shadd(-1, -2^31) ought to arrive at trunc((-2^31 - 1) / 2) = -2^30 + 1,
# while srhadd should yield the rounded-down -2^30.
code="shadd v0.2s, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0,-1,0 v2=llq:1,0x80000000,0 => v0=llq:0,0xbfffffff,0
code="srhadd v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:0,-1,0 v2=llq:1,0x80000000,0 => v0=llq:1,0xc0000000,0

# 0xffffffff + 1 = 0x100000000; halving yields 0x80000000. 0xffffffff + 2 = 0x10000001 (odd), so truncate/round.
code="uhadd v0.2s, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0xffffffff,0xffffffff,0 v2=llq:1,2,0 => v0=llq:0x80000000,0x80000000,0
code="urhadd v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:0xffffffff,0xffffffff,0 v2=llq:1,2,0 => v0=llq:0x80000000,0x80000001,0

code="sub d0, d1, d2" v0=qq:0,0 v1=qq:101,0 v2=qq:100,0 => v0=qq:1,0
code="sub v0.8b, v1.8b, v2.8b" v0=qq:0,0 v1=bbbbbbbbq:100,0,-128,255,-128,0,0,1,0 v2=bbbbbbbbq:100,-123,-1,1,1,0,0,0,0 => v0=bbbbbbbbq:0,123,-127,254,127,0,0,1,0

code="ssubl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:-1,1,0 v2=llq:1,-1,0 => v0=qq:-2,2
code="ssubl2 v0.2d, v1.4s, v2.4s" v0=qq:0,0 v1=qll:0,-1,1 v2=qll:0,1,-1 => v0=qq:-2,2
code="usubl v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:0xffffffff,1,0 v2=llq:1,1,0 => v0=qq:0xfffffffe,0
code="usubl2 v0.2d, v1.4s, v2.4s" v0=qq:0,0 v1=qll:0,0xffffffff,1 v2=qll:0,1,1 => v0=qq:0xfffffffe,0

code="ssubw v0.2d, v1.2d, v2.2s"  v0=qq:0,0 v1=qq:-1,1 v2=llq:-1,-1,0 => v0=qq:0,2
code="ssubw2 v0.2d, v1.2d, v2.4s" v0=qq:0,0 v1=qq:-1,1 v2=qll:0,-1,-1 => v0=qq:0,2
code="usubw v0.2d, v1.2d, v2.2s"  v0=qq:0,0 v1=qq:0x100000000,1 v2=llq:0xffffffff,1,0 => v0=qq:1,0
code="usubw2 v0.2d, v1.2d, v2.4s" v0=qq:0,0 v1=qq:0x100000000,1 v2=qll:0,0xffffffff,1 => v0=qq:1,0

# Corner case: 0 - 0x80000000 = 0 - (-2^31) = 2^31 outside the range of signed 32-bit,
# but shsub(0, 0x8000000) ought to correctly halve to 0x40000000 = 2^31/2 = 2^30.
code="shsub v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:2,0,0 v2=llq:1,0x80000000,0 => v0=llq:0,0x40000000,0

code="uhsub v0.2s, v1.2s, v2.2s" v0=qq:0,0 v1=llq:2,0x80000002,0 v2=llq:1,0x80000000,0 => v0=llq:0,1,0

code="umax v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,3,98 v2=llll:99,1,98,2 => v0=llll:99,99,98,98
code="umin v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,99,3,98 v2=llll:99,1,98,2 => v0=llll:1,1,3,2
code="smax v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,-99,3,98 v2=llll:99,1,-98,2 => v0=llll:99,1,3,98
code="smin v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=llll:1,-99,3,98 v2=llll:99,1,-98,2 => v0=llll:1,-99,-98,2

code="mul v0.2s, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:-1,20,0 v2=llq:1,5,0 => v0=llq:-1,100,0
code="mul v0.4s, v1.4s, v2.s[2]" v0=qq:0,0 v1=llll:100,0,-1,3 v2=llll:0,0,-1,0 => v0=llll:-100,0,1,-3

code="mla v0.4s, v1.4s, v2.4s" v0=llll:1000,1000,1000,1000 v1=llll:100,0,-1,3 v2=llll:1,0,-1,0 => v0=llll:1100,1000,1001,1000
code="mls v0.4s, v1.4s, v2.4s" v0=llll:1000,1000,1000,1000 v1=llll:100,0,-1,3 v2=llll:1,0,-1,0 => v0=llll:900,1000,999,1000

code="mla v0.4s, v1.4s, v2.s[2]" v0=llll:1000,1000,1000,1000 v1=llll:100,0,-1,3 v2=llll:1,0,-1,0 => v0=llll:900,1000,1001,997
code="mls v0.4s, v1.4s, v2.s[2]" v0=llll:1000,1000,1000,1000 v1=llll:100,0,-1,3 v2=llll:1,0,-1,0 => v0=llll:1100,1000,999,1003

code="smull v0.2d, v1.2s, v2.2s"  v0=qq:0,0 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-2,1
code="umull v0.4s, v1.4h, v2.4h"  v0=qq:0,0 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:4,6,6,4
code="umull2 v0.4s, v1.8h, v2.8h" v0=qq:0,0 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:20,18,14,8

code="smlal v0.2d, v1.2s, v2.2s"  v0=qq:-100,100 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-102,101
code="umlal v0.4s, v1.4h, v2.4h"  v0=llll:100,100,100,100 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:104,106,106,104
code="umlal2 v0.4s, v1.8h, v2.8h" v0=llll:100,100,100,100 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:120,118,114,108

code="smlsl v0.2d, v1.2s, v2.2s"  v0=qq:-100,100 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-98,99
code="umlsl v0.4s, v1.4h, v2.4h"  v0=llll:100,100,100,100 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:96,94,94,96
code="umlsl2 v0.4s, v1.8h, v2.8h" v0=llll:100,100,100,100 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:80,82,86,92

code="smull v0.2d, v1.2s, v2.s[1]"  v0=qq:0,0 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-1,1
code="umull v0.4s, v1.4h, v2.h[3]"  v0=qq:0,0 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:1,2,3,4
code="umull2 v0.4s, v1.8h, v2.h[7]" v0=qq:0,0 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:5,6,7,8

code="smlal v0.2d, v1.2s, v2.s[1]"  v0=qq:-100,100 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-101,101
code="umlal v0.4s, v1.4h, v2.h[3]"  v0=llll:100,100,100,100 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:101,102,103,104
code="umlal2 v0.4s, v1.8h, v2.h[7]" v0=llll:100,100,100,100 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:105,106,107,108

code="smlsl v0.2d, v1.2s, v2.s[1]"  v0=qq:-100,100 v1=llq:-1,1,0 v2=llq:2,1,0 => v0=qq:-99,99
code="umlsl v0.4s, v1.4h, v2.h[3]"  v0=llll:100,100,100,100 v1=wwwwq:1,2,3,4,0 v2=wwwwq:4,3,2,1,0 => v0=llll:99,98,97,96
code="umlsl2 v0.4s, v1.8h, v2.h[7]" v0=llll:100,100,100,100 v1=wwwwwwww:1,2,3,4,5,6,7,8 v2=wwwwwwww:8,7,6,5,4,3,2,1 => v0=llll:95,94,93,92

#
### Shifts
#

code="shl d0, d1, #8" v0=qq:0,0 v1=qq:1,0 => v0=qq:0x100,0
code="shl v0.4h, v1.4h, #4" v0=qq:0,0 v1=wwwwq:1,0x10,0x100,0x1000,0 => v0=wwwwq:0x10,0x100,0x1000,0x0,0

code="ushr v0.2d, v1.2d, #12" v0=qq:0,0 v1=qq:0xfff000,0xf0f0f0 => v0=qq:0xfff,0xf0f
code="ushr v0.4s, v1.4s, #1" v1=llll:0xffffffff,0x80808080,0x11111111,0x24242424 => v0=llll:0x7fffffff,0x40404040,0x08888888,0x12121212

# Arithmetic Right Shift (with sign extension), hence 0xffffffff -> 0xffffffff
code="sshr v0.4s, v1.4s, #12" v0=qq:0,0 v1=llll:0xfff000,0xf0f0f0,0x1,0xffffffff => v0=llll:0xfff,0xf0f,0,0xffffffff
code="sshr v0.4s, v1.4s, #1" v1=llll:0xffffffff,0x80808080,0x11111111,0x24242424 => v0=llll:0xffffffff,0xc0404040,0x08888888,0x12121212

code="usra d0, d1, #12"  v0=qq:1,2 v1=qq:0xfff000,0xf0f0f0 => v0=qq:0x1000,0
code="usra d0, d1, #64"  v0=qq:0x4b1e4c35739581ce,0x2387050d33681aeb v1=qq:0x6aebede07e0908ef,0x07c6d8d825d8ac36 => v0=qq:0x4b1e4c35739581ce,0
code="usra d0, d1, #64"  v0=qq:0x4b1e4c35739581ce,0x2387050d33681aeb v1=qq:0xfaebede07e0908ef,0x07c6d8d825d8ac36 => v0=qq:0x4b1e4c35739581ce,0
code="ssra d0, d1, #12"  v0=qq:1,2 v1=qq:0xfff000,0xf0f0f0 => v0=qq:0x1000,0
code="ssra d0, d1, #64"  v0=qq:0x4b1e4c35739581ce,0x2387050d33681aeb v1=qq:0x6aebede07e0908ef,0x07c6d8d825d8ac36 => v0=qq:0x4b1e4c35739581ce,0
code="ssra d0, d1, #64"  v0=qq:0x4b1e4c35739581ce,0x2387050d33681aeb v1=qq:0xfaebede07e0908ef,0x07c6d8d825d8ac36 => v0=qq:0x4b1e4c35739581cd,0
code="ursra d0, d1, #12" v0=qq:1,2 v1=qq:0xfff800,0xf0f8f0 => v0=qq:0x1001,0
code="srsra d0, d1, #12" v0=qq:1,2 v1=qq:0xfff800,0xf0f8f0 => v0=qq:0x1001,0

code="usra v0.2d, v1.2d, #12" v0=qq:1,2 v1=qq:0xfff000,0xf0f0f0 => v0=qq:0x1000,0xf11
code="ssra v0.4s, v1.4s, #12" v0=llll:1,2,3,4 v1=llll:0xfff000,0xf0f0f0,0x1,0xffffffff => v0=llll:0x1000,0xf11,3,3
code="ursra v0.2d, v1.2d, #12" v0=qq:1,2 v1=qq:0xfff800,0xf0f8f0 => v0=qq:0x1001,0xf12
code="srsra v0.4s, v1.4s, #12" v0=llll:1,2,3,4 v1=llll:0xfff000,0xf0f0f0,0x800,0xffffffff => v0=llll:0x1000,0xf11,4,4
code="srsra v6.2d, v27.2d, #32" v6=qq:0x56ce892d9eb8413d,0x71e361c0134d8303 v27=qq:0x245f3c4d877f23f1,0xaed4a740ee942fed => v6=qq:0x56ce892dc3177d8b,0x71e361bfc2222a44

code="shrn  v0.2s, v1.2d, #12" v0=qq:0,0 v1=qq:0xfff000,0xf0f0f0 => v0=llq:0xfff,0xf0f,0
code="shrn2 v0.4s, v1.2d, #12" v0=qq:0,0 v1=qq:0xfff000,0xf0f0f0 => v0=qll:0,0xfff,0xf0f

code="sshll v0.2d, v1.2s, #4"   v0=qq:0,0 v1=llq:0xffffffff,0x01,0 => v0=qq:0xfffffffffffffff0,0x10
code="sshll2 v0.2d, v1.4s, #31" v0=qq:0,0 v1=qll:0,0xffffffff,0x01 => v0=qq:0xffffffff80000000,0x80000000
code="ushll v0.2d, v1.2s, #4"   v0=qq:0,0 v1=llq:0xffffffff,0x01,0 => v0=qq:0xffffffff0,0x10
code="ushll2 v0.2d, v1.4s, #31" v0=qq:0,0 v1=qll:0,0xffffffff,0x01 => v0=qq:0x7fffffff80000000,0x80000000

code="sshl d0, d1, d2" v0=qq:0,0 v1=qq:0xff,0 v2=qq:4,0 => v0=qq:0xff0,0
code="sshl d0, d1, d2" v0=qq:0,0 v1=qq:0xff,0 v2=qq:-4,0 => v0=qq:0xf,0
code="sshl d0, d1, d2" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 v2=qq:4,0 => v0=qq:0xfffffffffffffff0,0

# Arithmetic Right Shift: -1 >> -4 == -1
code="sshl d0, d1, d2" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 v2=qq:-4,0 => v0=qq:0xffffffffffffffff,0

# Logical Right Shift
code="ushl d0, d1, d2" v1=qq:0xffffffffffffffff,0 v2=qq:-4,0 => v0=qq:0x0fffffffffffffff,0
code="ushl d0, d1, d2" v1=qq:0xffffffffffffffff,0 v2=qq:0x101,0 => v0=qq:0xffffffffffffffffe,0
# shift amount in the byte > #bits continues shifting, but is UB in LLVM-IR.
#code="ushl d0, d1, d2" v1=qq:0xffffffffffffffff,0 v2=qq:0xbc71330e9b,0 => v0=qq:0,0
code="ushl d0, d1, d2" v1=qq:0xffffffffffffffff,0 v2=qq:0xbc71330e00,0 => v0=qq:0xffffffffffffffff,0
code="ushl d0, d1, d2" v1=qq:0xffffffffffffffff,0 v2=qq:0xbc71330efc,0 => v0=qq:0x0fffffffffffffff,0

code="sshl v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xff,0xff v2=qq:4,-4 => v0=qq:0xff0,0xf
code="sshl v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xff,0xff v2=qq:-4,4 => v0=qq:0xf,0xff0
code="sshl v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 v2=qq:4,0 => v0=qq:0xfffffffffffffff0,0
code="sshl v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 v2=qq:-4,0 => v0=qq:0xffffffffffffffff,0
code="ushl v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 v2=qq:-4,0 => v0=qq:0x0fffffffffffffff,0
# XXX see above
# code="ushl v0.8h, v1.8h, v2.8h" v1=wwwwwwww:0xe76a,0x0d42,0xb970,0xb933,0xbe22,0x4cec,0x18b0,0xb944 v2=wwwwwwww:0x6ab3,0x64d2,0x986d,0xce9a,0xa064,0xe2a0,0xf03e,0x9b5e => v0=wwwwwwww:0,0,0,0,0,0,0,0

#
### FP Conversion
#

code="scvtf d0, d1" v0=qq:0,0 v1=qq:-10,0        => v0=dq:-10.0,0
code="ucvtf d0, d1" v0=qq:0,0 v1=qq:0xffffffff,0 => v0=dq:4294967295.0,0

code="scvtf v0.2d, v1.2d" v0=qq:0,0 v1=qq:-10,31415     => v0=dd:-10.0,31415.0
code="ucvtf v0.2d, v1.2d" v0=qq:0,0 v1=qq:0xffffffff,5 => v0=dd:4294967295.0,5.0

+jit code="fcvtns d1, d0" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:0,0
+jit code="fcvtnu d1, d0" v1=qq:0,0 v0=dq:0.5,0  => v1=qq:0,0

+jit code="fcvtas d1, d0" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:-1,0
+jit code="fcvtau d1, d0" v1=qq:0,0 v0=dq:0.5,0  => v1=qq:1,0
+jit code="fcvtms d1, d0" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:-1,0
+jit code="fcvtmu d1, d0" v1=qq:0,0 v0=dq:0.5,0  => v1=qq:0,0
+jit code="fcvtzs d1, d0" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:0,0
+jit code="fcvtzu d1, d0" v1=qq:0,0 v0=dq:0.5,0  => v1=qq:0,0
+jit code="fcvtps d1, d0" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:0,0
+jit code="fcvtpu d1, d0" v1=qq:0,0 v0=dq:0.5,0  => v1=qq:1,0


# Fixed-point conversion
code="fcvtzs d1, d0, #1" v1=qq:0,0 v0=dq:0.5,0 => v1=qq:0x01,0
code="fcvtzu d1, d0, #8" v1=qq:0,0 v0=dq:0.5,0 => v1=qq:0x80,0
code="fcvtzs d1, d0, #1" v1=qq:0,0 v0=dq:-0.5,0 => v1=qq:0xffffffffffffffff,0
code="fcvtzu d1, d0, #1" v1=qq:0,0 v0=dq:0.25,0 => v1=qq:0x0,0
code="scvtf d0, d1, #8" v0=qq:0,0 v1=qq:0x80,0 => v0=dq:0.5,0
code="scvtf d0, d1, #1" v0=qq:0,0 v1=qq:0xffffffffffffffff,0 => v0=dq:-0.5,0
code="ucvtf s0, s1, #8" v0=qq:0,0 v1=llq:0xffffffff10,0,0 => v0=flq:16777215.0625,0,0

+jit code="fcvtzs v1.2d, v0.2d, #1" v1=qq:0,0 v0=dd:0.5,-0.25 => v1=qq:0x01,0
+jit code="fcvtzu v1.2d, v0.2d, #8" v1=qq:0,0 v0=dd:0.0625,16777215.0625 => v1=qq:0x10,0xffffff10
code="scvtf v0.2d, v1.2d, #1" v0=qq:0,0 v1=qq:0xffffffffffffffff,0xfffffffffffffffe => v0=dd:-0.5,-1.0
code="ucvtf v0.2s, v1.2s, #8" v0=qq:0,0 v1=llq:0xffffff10,0x10,0 => v0=ffq:16777215.0625,0.0625,0

+jit code="fcvtas v1.2d, v0.2d" v1=qq:0,0 v0=dd:-0.5,0.5 => v1=qq:-1,1
+jit code="fcvtau v1.2d, v0.2d" v1=qq:0,0 v0=dd:0.5,0.5 => v1=qq:1,1
+jit code="fcvtms v1.2d, v0.2d" v1=qq:0,0 v0=dd:-0.5,0.5 => v1=qq:-1,0
+jit code="fcvtmu v1.2d, v0.2d" v1=qq:0,0 v0=dd:0.5,0.5 => v1=qq:0,0
+jit code="fcvtzs v1.2d, v0.2d" v1=qq:0,0 v0=dd:-0.5,0.5 => v1=qq:0,0
+jit code="fcvtzu v1.2d, v0.2d" v1=qq:0,0 v0=dd:0.5,0.5 => v1=qq:0,0
+jit code="fcvtps v1.2d, v0.2d" v1=qq:0,0 v0=dd:-0.5,0.5 => v1=qq:0,1
+jit code="fcvtpu v1.2d, v0.2d" v1=qq:0,0 v0=dd:0.5,0.5 => v1=qq:1,1

+jit code="frintn v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.5,0.0  => v0=dd:4.0,0.0
+jit code="frinti v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.5,-3.5 => v0=dd:4.0,-4.0
+jit code="frinta v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.5,-3.5 => v0=dd:4.0,-4.0

+jit code="frintm v0.2d, v1.2d" v0=qq:0,0 v1=dd:-3.5,3.5 => v0=dd:-4.0,3.0
+jit code="frintz v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.5,-3.5 => v0=dd:3.0,-3.0
+jit code="frintp v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.5,-3.5 => v0=dd:4.0,-3.0

+jit code="frintx v0.2d, v1.2d" v0=qq:0,0 v1=dd:3.0,-34.0 => v0=dd:3.0,-34.0

# FP Narrow to lower precision. We do not support half-precision.
code="fcvtn v0.2s, v1.2d"  v0=qq:0,0 v1=dd:0.5,-1.0 => v0=ffq:0.5,-1.0,0
code="fcvtn2 v0.4s, v1.2d" v0=qq:0,0 v1=dd:0.5,-1.0 => v0=qff:0,0.5,-1.0

# FP Convert to higher precision. We do not support half-precision.
code="fcvtl v0.2d, v1.2s"  v1=ffff:0.5,-1.0,3.0,12.25 => v0=dd:0.5,-1.0
code="fcvtl2 v0.2d, v1.4s" v1=ffff:0.5,-1.0,3.0,12.25 => v0=dd:3.0,12.25

#
### FP Arithmetic
#

+jit code="fabs v0.2d, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dd:1.0,1.0
+jit code="fabs v0.4s, v1.4s" v0=qq:0,0 v1=ffff:-1.0,1.0,0.0,-0.5 => v0=ffff:1.0,1.0,0.0,0.5

+jit code="fneg v0.2d, v1.2d" v0=qq:0,0 v1=dd:-1.0,1.0 => v0=dd:1.0,-1.0
+jit code="fneg v0.4s, v1.4s" v0=qq:0,0 v1=ffff:-1.0,1.0,0.0,-0.5 => v0=ffff:1.0,-1.0,-0.0,0.5

+jit code="fsqrt v0.2d, v1.2d" v0=qq:0,0 v1=dd:9.0,25.0 => v0=dd:3.0,5.0
+jit code="fsqrt v0.4s, v1.4s" v0=qq:0,0 v1=ffff:9.0,25.0,49.0,64.0 => v0=ffff:3.0,5.0,7.0,8.0

code="fadd v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:-1.0,1.0 v2=dd:1.0,1.0 => v0=dd:0.0,2.0
code="fsub v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:-1.0,1.0 v2=dd:1.0,1.0 => v0=dd:-2.0,0.0
+jit code="fabd d2, d11, d29" v11=qq:0x0a52741849e54740,0x17a0dc273ba9f803  v29=qq:0x141625713239066f,0xf6f2b14fbb3184b2 => v2=qq:0x141625713239066f,0
+jit code="fabd v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:-1.0,1.0 v2=dd:1.0,1.0 => v0=dd:2.0,0.0

# LLVM ERROR: Code generator does not support intrinsic function 'llvm.maximum.v4f32'!
# But cannot JIT either: on x86-64 hosts, there are no appropriate instructions, so FMIN and FMAX
# cannot be tested.
# Workaround: lift to maxnum/minnum insteadof maximum/minimum.
+jit code="fmax v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.0,99.0,3.0,98.0 v2=ffff:99.0,1.0,98.0,2.0 => v0=ffff:99.0,99.0,98.0,98.0
+jit code="fmin v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:0.0,-1.0e10 v2=dd:1.0,0.0 => v0=dd:0.0,-1.0e10
+jit code="fmaxnm v0.4s, v1.4s, v2.4s" v0=qq:0,0 v1=ffff:1.0,99.0,3.0,98.0 v2=ffff:99.0,1.0,98.0,2.0 => v0=ffff:99.0,99.0,98.0,98.0
+jit code="fminnm v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:0.0,-1.0e10 v2=dd:1.0,0.0 => v0=dd:0.0,-1.0e10

code="fmul v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:-1.0,20.0 v2=dd:1.0,5.0 => v0=dd:-1.0,100.0
code="fdiv v0.2d, v1.2d, v2.2d" v0=qq:0,0 v1=dd:-1.0,20.0 v2=dd:1.0,5.0 => v0=dd:-1.0,4.0

code="fmul d0, d1, v2.d[1]" v0=qq:0,0 v1=dq:100.0,0 v2=dd:0.0,-1.0 => v0=dq:-100.0,0
code="fmul v0.4s, v1.4s, v2.s[2]" v0=qq:0,0 v1=ffff:100.0,0.0,-1.0,3.0 v2=ffff:0.0,0.0,-1.0,0.0 => v0=ffff:-100.0,0.0,1.0,-3.0

code="fmla d0, d1, v2.d[1]" v0=dq:111.0,0 v1=dq:100.0,0 v2=dd:0.0,-1.0 => v0=dq:11.0,0
code="fmls d0, d1, v2.d[1]" v0=dq:111.0,0 v1=dq:100.0,0 v2=dd:0.0,-1.0 => v0=dq:211.0,0

code="fmla v0.4s, v1.4s, v2.4s" v0=ffff:1000.0,1000.0,1000.0,1000.0 v1=ffff:100.0,0.0,-1.0,3.0 v2=ffff:1.0,0.0,-1.0,0.0 => v0=ffff:1100.0,1000.0,1001.0,1000.0
code="fmls v0.4s, v1.4s, v2.4s" v0=ffff:1000.0,1000.0,1000.0,1000.0 v1=ffff:100.0,0.0,-1.0,3.0 v2=ffff:1.0,0.0,-1.0,0.0 => v0=ffff:900.0,1000.0,999.0,1000.0

code="fmla v0.4s, v1.4s, v2.s[2]" v0=ffff:1000.0,1000.0,1000.0,1000.0 v1=ffff:100.0,0.0,-1.0,3.0 v2=ffff:1.0,0.0,-1.0,0.0 => v0=ffff:900.0,1000.0,1001.0,997.0
code="fmls v0.4s, v1.4s, v2.s[2]" v0=ffff:1000.0,1000.0,1000.0,1000.0 v1=ffff:100.0,0.0,-1.0,3.0 v2=ffff:1.0,0.0,-1.0,0.0 => v0=ffff:1100.0,1000.0,999.0,1003.0

# Type handling
code="mvni v0.2s, #0x0; str d0, [x0]" x0=q:0x2000000 m2000000=0123456789abcdef => v0=qq:-1,0 m2000000=ffffffffffffffff
