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e4e61c4f15135eadccb6ba050805a01e35ef7642
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5 Commits

Author SHA1 Message Date
kobalicek e4e61c4f15 [ABI] Completely reworked instruction DB and generators 
* Instruction database is now part of asmjit to keep it in sync
  * X86/X64 ISA data has been reworked, now in a proper JSON format
  * ARM32 ISA data has been added (currently only DB, support later)
  * ARM64 ISA data has been added
  * ARM features detection has been updated
 2023-09-10 09:55:17 +02:00
aegistudio 5af57595a9 [Bug] Fixed LDURSW instruction on AArch64 (#389) 
The instruction was wrongly described as supporting both W/X registers, however, it only supports X register.
 2022-11-10 10:11:05 +01:00
kobalicek d0cdd70168 [Bug] Fixed incorrect encoding of LDRSH instruction with [base+imm] addressing (AArch64) (fixes #372) 2022-06-20 09:16:39 +02:00
kobalicek d925605671 [Bug] Fixed incorrect encoding of LDRSB and LDRSH with [base+index] (AArch64) (fixes #370) 2022-06-17 12:26:34 +02:00
kobalicek 23ddf56b00 [ABI] Initial AArch64 support 2022-02-09 17:08:40 +01:00