Commit Graph

31 Commits

Author SHA1 Message Date
gg c37fd6a238 Fixed regression tests for PUSHFW and POPFW 2015-02-20 20:51:17 +01:00
Camille Mougey 441c3eb7ef Core/ASMBloc: resolve_symbol now returns only the resolved blocs 2015-01-26 11:08:50 +01:00
Wladimir J. van der Laan 03be04f520 arm: Add umull,umlal,smull,smlal to sem 2015-01-26 08:29:57 +01:00
Wladimir J. van der Laan 8001e8f6f7 arm: Add instruction umlal
umull, smull, smull and smlal are there, but not umlal
(unsigned multiply and accumulate long)
2015-01-24 16:14:19 +01:00
Fabrice Desclaux 5c45840909 Arm: add instruction bfc 2015-01-12 16:19:48 +01:00
Fabrice Desclaux 97c7d15789 Arm: Fix cf in logical mnemonics
/!\ TODO: CF is invalid in case of rotation in second argument.
2014-12-11 16:15:22 +01:00
Fabrice Desclaux 91da5bf811 Arm: add mnemonic smull 2014-12-08 18:45:06 +01:00
Fabrice Desclaux 7101a6d9d5 Arch/jit: add endianess support jitters 2014-10-09 17:04:36 +02:00
Fabrice Desclaux 809d3738bb Remove vm_ prefix /!\ API MODIF
The jitter cpu/vm modules used an unecessary vm_ prefix for various api.

jitter.cpu.vm_get_gpreg() => jitter.cpu.get_gpreg()
jitter.vm.vm_get_mem... => jitter.vm.get_mem...
2014-10-07 17:44:50 +02:00
Fabrice Desclaux 35bde6dab6 Arm: fix carry flag in sub operation; update reg tests 2014-10-06 13:34:26 +02:00
Fabrice Desclaux 6317588a7d Arm: swi is svc 2014-09-29 16:37:00 +02:00
Fabrice Desclaux d2d915478e Arm: add bkpt 2014-09-29 16:32:48 +02:00
Fabrice Desclaux 6c1c35c06b Arm: fix ldmia write back 2014-09-29 16:29:16 +02:00
Fabrice Desclaux 032263e8f5 test: add mnemonic tests 2014-09-19 15:26:05 +02:00
Fabrice Desclaux 3674bace8d merge 2014-09-19 10:43:32 +02:00
Fabrice Desclaux d3bffc301e mips: add ei/ehb (dummy semantic) 2014-09-15 09:37:01 +02:00
Fabrice Desclaux 6e09df71a3 Modify irbloc destination mecanism. Rework API in consequence.
Fat patch here: some API have changed.

Each irbloc now affects a special "IRDst" register which is used to
describe the destination irbloc. It allows simple description of
architectures using delay slots. Architectures semantic and tcc/python
jitter are modified in consequence. LLVM jitter is disabled for now,
but should be patch soon.
2014-09-05 11:30:05 +02:00
serpilliere 79be2a143a mips32: add ldc1 2014-08-28 10:18:46 +02:00
serpilliere 22c0cc1ae2 Jitter: add mips32l jit 2014-08-22 16:13:53 +02:00
serpilliere 3931f27b69 mips32: add mnemo JAL/MOVZ 2014-08-21 10:21:47 +02:00
serpilliere 5763236891 mips32: little/big endian is now an attrib 2014-08-21 09:49:01 +02:00
serpilliere 78ff130268 x86: add les/lds. Fix call/ret far 2014-08-12 14:02:07 +02:00
serpilliere 376576de29 Add mips32 arch 2014-08-06 17:28:13 +02:00
serpilliere 8cbb7db586 x86 arch: fix some mnemonic 2014-08-05 16:23:19 +02:00
serpilliere dbd0183692 Arm arch: add uxtb uxth sxtb sxth 2014-08-01 15:40:02 +02:00
ajax e97492dbd0 Test: Improve x86 SSE tests (thanks to Adrien Guinet) 2014-07-30 14:59:29 +02:00
serpilliere e11704c033 X86 arch: addps/addpd 2014-07-21 11:48:16 +02:00
serpilliere 95de9efd4f Arm: update reg tests 2014-07-03 10:19:23 +02:00
serpilliere fd3518fde9 Fix arm reg tests 2014-06-30 10:50:29 +02:00
serpilliere 240490662b Test: add x86 mnemo tests 2014-06-25 14:21:48 +02:00
serpilliere ed5c3668cc Miasm v2
* API has changed, so old scripts need updates
* See example for API usage
* Use tcc or llvm for jit emulation
* Go to test and run test_all.py to check install

Enjoy !
2014-06-03 10:27:56 +02:00