From 1aff1f565eb899fe5c356d43db360c23b1939138 Mon Sep 17 00:00:00 2001 From: Nicolas Iooss Date: Sat, 27 Aug 2022 21:54:21 +0000 Subject: [PATCH] Add configuration of Intel 440FX PCI and Memory Controller registers When testing chipsec in a QEMU virtual machine (x86-64 CPU with default machine), it fails: $ ./chipsec_main.py ... [-] ERROR: Chipset requires a supported PCH to be loaded. Unknown PCH: VID = 0xFFFF, DID = 0xFFFF, RID = 0xFF [!] WARNING: ******************************************************************* [!] WARNING: * Unknown platform! [!] WARNING: * Platform dependent functionality will likely be incorrect [!] WARNING: * Error Message: "Unknown PCH: VID = 0xFFFF, DID = 0xFFFF, RID = 0xFF" [!] WARNING: ******************************************************************* [-] ERROR: To run anyways please use -i command-line option Enumerating the PCI devices gives: $ ./chipsec_util.py -i pci enumerate ... [CHIPSEC] Enumerating available PCIe devices... BDF | VID:DID | Vendor | Device ------------------------------------------------------------------------- 00:00.0 | 8086:1237 | Intel Corporation | 440FX - 82441FX PMC [Natoma] 00:01.0 | 8086:7000 | Intel Corporation | 82371SB PIIX3 ISA [Natoma/Triton II] 00:01.1 | 8086:7010 | Intel Corporation | 82371SB PIIX3 IDE [Natoma/Triton II] 00:01.3 | 8086:7113 | Intel Corporation | 82371AB/EB/MB PIIX4 ACPI 00:02.0 | 1234:1111 | | 00:03.0 | 1AF4:1000 | Red Hat, Inc. | Virtio network device This virtual machine simulates a i440FX PMC (and does not provide a PCH). This is also described in QEMU machines list: $ qemu-system-x86_64 -M help ... pc Standard PC (i440FX + PIIX, 1996) Add a configuration file in chipsec to support such a system. With it, chipsec starts successfully: $ ./chipsec_main.py [CHIPSEC] API mode: using CHIPSEC kernel module API [!] Unknown PCH: VID = 0xFFFF, DID = 0xFFFF, RID = 0xFF; Using Default. [!] Results from this system may be incorrect. [CHIPSEC] OS : Linux 5.7.0-kali1-amd64 #1 SMP Debian 5.7.6-1kali2 (2020-07-01) x86_64 [CHIPSEC] Python : 3.8.4 (64-bit) [CHIPSEC] Helper : LinuxHelper (None) [CHIPSEC] Platform: Intel 440FX PMC [CHIPSEC] VID: 8086 [CHIPSEC] DID: 1237 [CHIPSEC] RID: 02 [CHIPSEC] PCH : Default PCH [CHIPSEC] VID: FFFF [CHIPSEC] DID: FFFF [CHIPSEC] RID: FF ... Moreover, when booting a VM with `qemu-system-x86_64 -M pc,smm=on` it is possible to successfully read the SMRAMC register: $ ./chipsec_util.py reg read PCI0.0.0_SMRAMC ... [CHIPSEC] Executing command 'reg' with args ['read', 'PCI0.0.0_SMRAMC'] [CHIPSEC] PCI0.0.0_SMRAMC=0xA [*] PCI0.0.0_SMRAMC = 0x0A << System Management RAM Control (b:d.f 00:00.0 + 0x72) [00] C_BASE_SEG = 2 << SMRAM Base Segment = 010b [03] G_SMRAME = 1 << SMRAM Enabled [04] D_LCK = 0 << SMRAM Locked [05] D_CLS = 0 << SMRAM Closed [06] D_OPEN = 0 << SMRAM Open Signed-off-by: Nicolas Iooss --- chipsec/cfg/8086/pmc_i440fx.xml | 90 +++++++++++++++++++++++++++++++++ 1 file changed, 90 insertions(+) create mode 100644 chipsec/cfg/8086/pmc_i440fx.xml diff --git a/chipsec/cfg/8086/pmc_i440fx.xml b/chipsec/cfg/8086/pmc_i440fx.xml new file mode 100644 index 00000000..c1ffc66b --- /dev/null +++ b/chipsec/cfg/8086/pmc_i440fx.xml @@ -0,0 +1,90 @@ + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + + +