From 6b8d94c854f605c9deee40ce81e11b4d250cbbfc Mon Sep 17 00:00:00 2001 From: Erik Bjorge Date: Fri, 1 Nov 2019 13:53:36 -0700 Subject: [PATCH] Fix zero padding when printing registers Signed-off-by: Erik Bjorge --- chipsec/chipset.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/chipsec/chipset.py b/chipsec/chipset.py index 72c5e72a..488b4c8b 100644 --- a/chipsec/chipset.py +++ b/chipsec/chipset.py @@ -1014,7 +1014,7 @@ class Chipset: reg = self.get_register_def( reg_name, bus_index ) rtype = reg['type'] reg_str = '' - reg_val_str = "0x{:{width}X}".format(reg_val,width=(int(reg['size'],16)*2)) + reg_val_str = "0x{:0{width}X}".format(reg_val,width=(int(reg['size'],16)*2)) if RegisterType.PCICFG == rtype or RegisterType.MMCFG == rtype: b = int(reg['bus'],16) d = int(reg['dev'],16)