From bf5157435a1350dbaa72a531e5b67df0524ef073 Mon Sep 17 00:00:00 2001
From: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
Date: Tue, 19 Nov 2024 15:58:21 -0800
Subject: [PATCH] Add adl.xml

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
---
 chipsec/cfg/8086/adl.xml | 91 ++++++++++++++++++++++++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 chipsec/cfg/8086/adl.xml

diff --git a/chipsec/cfg/8086/adl.xml b/chipsec/cfg/8086/adl.xml
new file mode 100644
index 00000000..a7a47547
--- /dev/null
+++ b/chipsec/cfg/8086/adl.xml
@@ -0,0 +1,91 @@
+<?xml version="1.0"?>
+<configuration platform="ADL" req_pch="False"> 
+<!-- TODO: req_pch = True -->
+<!--
+CHIPSEC: Platform Security Assessment Framework
+Copyright (c) 2023, Intel Corporation
+
+This program is free software; you can redistribute it and/or
+modify it under the terms of the GNU General Public License
+as published by the Free Software Foundation; Version 2.
+
+This program is distributed in the hope that it will be useful,
+but WITHOUT ANY WARRANTY; without even the implied warranty of
+MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+GNU General Public License for more details.
+
+You should have received a copy of the GNU General Public License
+along with this program; if not, write to the Free Software
+Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA  02110-1301, USA.
+
+Contact information:
+chipsec@intel.com
+-->
+
+<!--
+XML configuration file for Alder Lake based platforms
+
+http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
+
+* 12th Generation Intel(R) Core Processor Family Datasheet
+Review:    !!!
+* Intel(R) 600 Series Chipset Family on-package Platform Controller Hub (PCH)
+-->
+
+  <!-- #################################### -->
+  <!--                                      -->
+  <!-- Information                          -->
+  <!--                                      -->
+  <!-- #################################### -->
+
+  <info family="core" detection_value="0x90670-0x90672, 0x90674-0x90675, 0x906a0-0x906a4">
+    <sku did="0x4601" name="AlderLake" code="ADL" longname="ADL-P/U15 2+8"/>
+    <sku did="0x4602" name="AlderLake" code="ADL" longname="ADL-U9 2+8"/>
+    <sku did="0x4609" name="AlderLake" code="ADL" longname="ADL-U15 2+4"/>
+    <sku did="0x460A" name="AlderLake" code="ADL" longname="ADL-U9 2+4"/>
+    <sku did="0x4610" name="AlderLake" code="ADL" longname="ADL-S LGA 2+0"/>
+    <sku did="0x4619" name="AlderLake" code="ADL" longname="ADL-U15 1+4"/>
+    <sku did="0x461A" name="AlderLake" code="ADL" longname="ADL-U9 1+4"/>
+    <sku did="0x4621" name="AlderLake" code="ADL" longname="ADL-P/H 4+8"/>
+    <sku did="0x4629" name="AlderLake" code="ADL" longname="ADL-H 4+4"/>
+    <sku did="0x4630" name="AlderLake" code="ADL" longname="ADL-S LGA 4+0"/>
+    <sku did="0x4641" name="AlderLake" code="ADL" longname="ADL-P/H 6+8"/>
+    <sku did="0x4648" name="AlderLake" code="ADL" longname="ADL-S LGA 6+4"/>
+    <sku did="0x4649" name="AlderLake" code="ADL" longname="ADL-H 6+4"/>
+    <sku did="0x4650" name="AlderLake" code="ADL" longname="ADL-S LGA 6+0"/>
+    <sku did="0x4660" name="AlderLake" code="ADL" longname="ADL-S LGA 8+8"/>
+    <sku did="0x4668" name="AlderLake" code="ADL" longname="ADL-S LGA 8+4"/>
+  </info>
+
+
+
+  <!-- #################################### -->
+  <!--                                      -->
+  <!-- Integrated devices                   -->
+  <!--                                      -->
+  <!-- #################################### -->
+  <pci>
+    <!-- Review !!!!                                           !!!!                /-->
+    <device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" did="0x4621,0x4660" config="IOMMU.iommu.xml" />
+    <!-- <device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" config="HOSTCTL.hostctl1.xml"/> -->
+    <device name="IGD"     bus="0x00" dev="0x02" fun="0" config="IGD.igd0.xml" />
+    <device name="MEI1"    bus="0x00" dev="0x16" fun="0" config="ME.mei0.xml" />
+    <device name="SMBUS"   bus="0x00" dev="0x1F" fun="4" config="SMBUS.smbus0.xml" />
+    <device name="SPI"     bus="0x00" dev="0x1F" fun="5" config="SPI.spi0.xml" />
+    <device name="SPI"     bus="0x00" dev="0x1F" fun="5" config="SPI.descriptor0.xml" />
+  </pci>
+
+  <msr>
+    <definition name="MSR" config="MSR.msr2.xml" />
+  </msr>
+
+  <!-- #################################### -->
+  <!--                                      -->
+  <!-- Memory ranges                        -->
+  <!--                                      -->
+  <!-- #################################### -->
+  <memory>
+    <range name="TPM" access="mmio" address="0xFED40000" size="0x10000" config="TPM.tpm12.xml" />
+  </memory>
+
+</configuration>