From f6dbffe100ea26bf6a75d2b602ac3de9779c4fa4 Mon Sep 17 00:00:00 2001 From: Nathaniel Mitchell Date: Fri, 27 Aug 2021 07:50:29 -0700 Subject: [PATCH] Update to 1.7.1 Signed-off-by: Nathaniel Mitchell --- chipsec-manual.pdf | 33711 +++++++++++++++++++------------------- chipsec/VERSION | 2 +- drivers/linux/dkms.conf | 2 +- 3 files changed, 16817 insertions(+), 16898 deletions(-) diff --git a/chipsec-manual.pdf b/chipsec-manual.pdf index 4ab9b079..a98afc7d 100644 --- a/chipsec-manual.pdf +++ b/chipsec-manual.pdf @@ -3,7 +3,7 @@ 1 0 obj << /F1 2 0 R /F2 3 0 R /F3 101 0 R /F4 490 0 R /F5 491 0 R /F6 591 0 R - /F7 884 0 R + /F7 881 0 R >> endobj 2 0 obj @@ -26,7 +26,7 @@ s4IA0!"_al8O`[\!;#6tJ?#m^kH'FbHY$Odmc'+Yct)BU"@)B9_>,VCGe endobj 5 0 obj << -/Contents 1197 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1194 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] /XObject << /FormXob.3f77cdc828a3bce7666aad90094f4da2 4 0 R >> @@ -415,7 +415,7 @@ endobj 46 0 R 47 0 R 48 0 R 49 0 R 50 0 R 51 0 R 52 0 R 53 0 R 54 0 R 55 0 R 56 0 R 57 0 R 58 0 R 59 0 R 60 0 R 61 0 R 62 0 R 63 0 R 64 0 R 65 0 R 66 0 R 67 0 R 68 0 R 69 0 R 70 0 R 71 0 R 72 0 R 73 0 R 74 0 R 75 0 R - 76 0 R 77 0 R 78 0 R 79 0 R ] /Contents 1198 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 76 0 R 77 0 R 78 0 R 79 0 R ] /Contents 1195 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -827,7 +827,7 @@ endobj 122 0 R 123 0 R 124 0 R 125 0 R 126 0 R 127 0 R 128 0 R 129 0 R 130 0 R 131 0 R 132 0 R 133 0 R 134 0 R 135 0 R 136 0 R 137 0 R 138 0 R 139 0 R 140 0 R 141 0 R 142 0 R 143 0 R 144 0 R 145 0 R 146 0 R 147 0 R 148 0 R 149 0 R 150 0 R 151 0 R - 152 0 R 153 0 R 154 0 R 155 0 R 156 0 R 157 0 R 158 0 R 159 0 R ] /Contents 1199 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 152 0 R 153 0 R 154 0 R 155 0 R 156 0 R 157 0 R 158 0 R 159 0 R ] /Contents 1196 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -957,272 +957,272 @@ endobj endobj 185 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 140.0157 544.7008 226.1657 556.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 140.0157 544.7008 226.1657 556.7008 ] /Subtype /Link /Type /Annot >> endobj 186 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 544.1398 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 544.1398 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot >> endobj 187 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 653 0 R /XYZ 40.01575 279.7008 0 ] /Rect [ 140.0157 526.7008 199.4757 538.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 653 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 140.0157 526.7008 199.4757 538.7008 ] /Subtype /Link /Type /Annot >> endobj 188 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 653 0 R /XYZ 40.01575 279.7008 0 ] /Rect [ 544.1398 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 653 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 544.1398 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot >> endobj 189 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 555.7008 0 ] /Rect [ 140.0157 508.7008 191.7057 520.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 508.7008 191.7057 520.7008 ] /Subtype /Link /Type /Annot >> endobj 190 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 555.7008 0 ] /Rect [ 544.1398 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 544.1398 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot >> endobj 191 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 490.7008 199.4857 502.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 116.1008 0 ] /Rect [ 140.0157 490.7008 199.4857 502.7008 ] /Subtype /Link /Type /Annot >> endobj 192 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 544.1398 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 655 0 R /XYZ 40.01575 116.1008 0 ] /Rect [ 544.1398 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot >> endobj 193 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 488.7008 0 ] /Rect [ 140.0157 472.7008 186.1457 484.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 656.3008 0 ] /Rect [ 140.0157 472.7008 186.1457 484.7008 ] /Subtype /Link /Type /Annot >> endobj 194 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 488.7008 0 ] /Rect [ 544.1398 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 656.3008 0 ] /Rect [ 544.1398 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot >> endobj 195 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 454.7008 216.1657 466.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 169.5008 0 ] /Rect [ 140.0157 454.7008 216.1657 466.7008 ] /Subtype /Link /Type /Annot >> endobj 196 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 544.1398 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 169.5008 0 ] /Rect [ 544.1398 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot >> endobj 197 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 596.1008 0 ] /Rect [ 140.0157 436.7008 188.9257 448.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 661 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 436.7008 188.9257 448.7008 ] /Subtype /Link /Type /Annot >> endobj 198 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 596.1008 0 ] /Rect [ 544.1398 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 661 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot >> endobj 199 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 662 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 418.7008 217.2657 430.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 661 0 R /XYZ 40.01575 204.7008 0 ] /Rect [ 140.0157 418.7008 217.2657 430.7008 ] /Subtype /Link /Type /Annot >> endobj 200 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 662 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 544.1398 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 661 0 R /XYZ 40.01575 204.7008 0 ] /Rect [ 544.1398 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot >> endobj 201 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 662 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 140.0157 400.7008 183.3657 412.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 663 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 140.0157 400.7008 183.3657 412.7008 ] /Subtype /Link /Type /Annot >> endobj 202 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 662 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 544.1398 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 663 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 544.1398 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot >> endobj 203 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 663.7008 0 ] /Rect [ 140.0157 382.7008 197.8157 394.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 663 0 R /XYZ 40.01575 224.7008 0 ] /Rect [ 140.0157 382.7008 197.8157 394.7008 ] /Subtype /Link /Type /Annot >> endobj 204 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 663.7008 0 ] /Rect [ 544.1398 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 663 0 R /XYZ 40.01575 224.7008 0 ] /Rect [ 544.1398 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot >> endobj 205 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 231.9008 0 ] /Rect [ 140.0157 364.7008 205.5857 376.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 140.0157 364.7008 205.5857 376.7008 ] /Subtype /Link /Type /Annot >> endobj 206 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 231.9008 0 ] /Rect [ 544.1398 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 544.1398 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot >> endobj 207 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 667 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 346.7008 200.0257 358.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 308.1008 0 ] /Rect [ 140.0157 346.7008 200.0257 358.7008 ] /Subtype /Link /Type /Annot >> endobj 208 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 667 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 544.1398 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 665 0 R /XYZ 40.01575 308.1008 0 ] /Rect [ 544.1398 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot >> endobj 209 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 669 0 R /XYZ 40.01575 483.7008 0 ] /Rect [ 140.0157 328.7008 210.5957 340.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 667 0 R /XYZ 40.01575 133.1008 0 ] /Rect [ 140.0157 328.7008 210.5957 340.7008 ] /Subtype /Link /Type /Annot >> endobj 210 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 669 0 R /XYZ 40.01575 483.7008 0 ] /Rect [ 544.1398 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 667 0 R /XYZ 40.01575 133.1008 0 ] /Rect [ 544.1398 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot >> endobj 211 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 711.7008 0 ] /Rect [ 140.0157 310.7008 192.2457 322.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 671 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 140.0157 310.7008 192.2457 322.7008 ] /Subtype /Link /Type /Annot >> endobj 212 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 711.7008 0 ] /Rect [ 544.1398 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 671 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 544.1398 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot >> endobj 213 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 147.9008 0 ] /Rect [ 140.0157 292.7008 205.6057 304.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 140.0157 292.7008 205.6057 304.7008 ] /Subtype /Link /Type /Annot >> endobj 214 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 147.9008 0 ] /Rect [ 544.1398 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 544.1398 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot >> endobj 215 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 685 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 140.0157 274.7008 188.3657 286.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 684 0 R /XYZ 40.01575 399.7008 0 ] /Rect [ 140.0157 274.7008 188.3657 286.7008 ] /Subtype /Link /Type /Annot >> endobj 216 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 685 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 544.1398 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 684 0 R /XYZ 40.01575 399.7008 0 ] /Rect [ 544.1398 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot >> endobj 217 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 689 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 140.0157 256.7008 199.4857 268.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 687 0 R /XYZ 40.01575 243.7008 0 ] /Rect [ 140.0157 256.7008 199.4857 268.7008 ] /Subtype /Link /Type /Annot >> endobj 218 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 689 0 R /XYZ 40.01575 387.7008 0 ] /Rect [ 544.1398 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 687 0 R /XYZ 40.01575 243.7008 0 ] /Rect [ 544.1398 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot >> endobj 219 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 689 0 R /XYZ 40.01575 209.3008 0 ] /Rect [ 140.0157 238.7008 218.9257 250.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 690 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 238.7008 218.9257 250.7008 ] /Subtype /Link /Type /Annot >> endobj 220 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 689 0 R /XYZ 40.01575 209.3008 0 ] /Rect [ 544.1398 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 690 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot >> endobj 221 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 692 0 R /XYZ 40.01575 363.7008 0 ] /Rect [ 140.0157 220.7008 207.2557 232.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 690 0 R /XYZ 40.01575 295.9008 0 ] /Rect [ 140.0157 220.7008 207.2557 232.7008 ] /Subtype /Link /Type /Annot >> endobj 222 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 692 0 R /XYZ 40.01575 363.7008 0 ] /Rect [ 544.1398 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 690 0 R /XYZ 40.01575 295.9008 0 ] /Rect [ 544.1398 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot >> endobj 223 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 140.0157 202.7008 205.0357 214.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 140.0157 202.7008 205.0357 214.7008 ] /Subtype /Link /Type /Annot >> endobj 224 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 544.1398 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 544.1398 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot >> endobj 225 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 176.1008 0 ] /Rect [ 140.0157 184.7008 191.7057 196.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 116.1008 0 ] /Rect [ 140.0157 184.7008 191.7057 196.7008 ] /Subtype /Link /Type /Annot >> endobj 226 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 176.1008 0 ] /Rect [ 544.1398 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 116.1008 0 ] /Rect [ 544.1398 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot >> endobj 227 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 171.7008 0 ] /Rect [ 140.0157 166.7008 188.3657 178.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 123.7008 0 ] /Rect [ 140.0157 166.7008 188.3657 178.7008 ] /Subtype /Link /Type /Annot >> endobj 228 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 171.7008 0 ] /Rect [ 544.1398 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 123.7008 0 ] /Rect [ 544.1398 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot >> endobj 229 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 140.0157 148.7008 237.8257 160.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 140.0157 148.7008 237.8257 160.7008 ] /Subtype /Link /Type /Annot >> endobj 230 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 544.1398 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 544.1398 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot >> endobj 231 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 140.0157 130.7008 236.1657 142.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 140.0157 130.7008 236.1657 142.7008 ] /Subtype /Link /Type /Annot >> endobj 232 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 544.1398 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 371.1008 0 ] /Rect [ 544.1398 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot >> endobj 233 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 195.5008 0 ] /Rect [ 140.0157 112.7008 210.0457 124.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 195.5008 0 ] /Rect [ 140.0157 112.7008 210.0457 124.7008 ] /Subtype /Link /Type /Annot >> endobj 234 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 195.5008 0 ] /Rect [ 544.1398 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 711 0 R /XYZ 40.01575 195.5008 0 ] /Rect [ 544.1398 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot >> endobj 235 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 713 0 R /XYZ 40.01575 94.50079 0 ] /Rect [ 140.0157 94.70079 192.2557 106.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 94.50079 0 ] /Rect [ 140.0157 94.70079 192.2557 106.7008 ] /Subtype /Link /Type /Annot >> endobj 236 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 713 0 R /XYZ 40.01575 94.50079 0 ] /Rect [ 544.1398 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 712 0 R /XYZ 40.01575 94.50079 0 ] /Rect [ 544.1398 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot >> endobj 237 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 717 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 140.0157 76.70079 257.8357 88.70079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 716 0 R /XYZ 40.01575 351.7008 0 ] /Rect [ 140.0157 76.70079 257.8357 88.70079 ] /Subtype /Link /Type /Annot >> endobj 238 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 717 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 544.1398 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 716 0 R /XYZ 40.01575 351.7008 0 ] /Rect [ 544.1398 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot >> endobj 239 0 obj @@ -1234,7 +1234,7 @@ endobj 201 0 R 202 0 R 203 0 R 204 0 R 205 0 R 206 0 R 207 0 R 208 0 R 209 0 R 210 0 R 211 0 R 212 0 R 213 0 R 214 0 R 215 0 R 216 0 R 217 0 R 218 0 R 219 0 R 220 0 R 221 0 R 222 0 R 223 0 R 224 0 R 225 0 R 226 0 R 227 0 R 228 0 R 229 0 R 230 0 R - 231 0 R 232 0 R 233 0 R 234 0 R 235 0 R 236 0 R 237 0 R 238 0 R ] /Contents 1200 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 231 0 R 232 0 R 233 0 R 234 0 R 235 0 R 236 0 R 237 0 R 238 0 R ] /Contents 1197 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -1244,392 +1244,392 @@ endobj endobj 240 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 663.7008 0 ] /Rect [ 140.0157 760.7008 235.6157 772.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 760.7008 235.6157 772.7008 ] /Subtype /Link /Type /Annot >> endobj 241 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 663.7008 0 ] /Rect [ 544.1398 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 544.1398 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot >> endobj 242 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 120.1008 0 ] /Rect [ 140.0157 742.7008 202.8257 754.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 156.1008 0 ] /Rect [ 140.0157 742.7008 202.8257 754.7008 ] /Subtype /Link /Type /Annot >> endobj 243 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 120.1008 0 ] /Rect [ 544.1398 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 156.1008 0 ] /Rect [ 544.1398 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot >> endobj 244 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 728 0 R /XYZ 40.01575 435.5008 0 ] /Rect [ 140.0157 724.7008 191.7057 736.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 727 0 R /XYZ 40.01575 454.7008 0 ] /Rect [ 140.0157 724.7008 191.7057 736.7008 ] /Subtype /Link /Type /Annot >> endobj 245 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 728 0 R /XYZ 40.01575 435.5008 0 ] /Rect [ 544.1398 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 727 0 R /XYZ 40.01575 454.7008 0 ] /Rect [ 544.1398 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot >> endobj 246 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 730 0 R /XYZ 40.01575 303.7008 0 ] /Rect [ 140.0157 706.7008 235.6057 718.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 729 0 R /XYZ 40.01575 327.7008 0 ] /Rect [ 140.0157 706.7008 235.6057 718.7008 ] /Subtype /Link /Type /Annot >> endobj 247 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 730 0 R /XYZ 40.01575 303.7008 0 ] /Rect [ 544.1398 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 729 0 R /XYZ 40.01575 327.7008 0 ] /Rect [ 544.1398 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot >> endobj 248 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 745 0 R /XYZ 40.01575 411.7008 0 ] /Rect [ 140.0157 688.7008 205.0457 700.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 744 0 R /XYZ 40.01575 435.7008 0 ] /Rect [ 140.0157 688.7008 205.0457 700.7008 ] /Subtype /Link /Type /Annot >> endobj 249 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 745 0 R /XYZ 40.01575 411.7008 0 ] /Rect [ 544.1398 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 744 0 R /XYZ 40.01575 435.7008 0 ] /Rect [ 544.1398 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot >> endobj 250 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 483.7008 0 ] /Rect [ 140.0157 670.7008 233.3857 682.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 140.0157 670.7008 233.3857 682.7008 ] /Subtype /Link /Type /Annot >> endobj 251 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 483.7008 0 ] /Rect [ 544.1398 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 544.1398 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot >> endobj 252 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 755 0 R /XYZ 40.01575 243.7008 0 ] /Rect [ 140.0157 652.7008 227.2757 664.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 267.7008 0 ] /Rect [ 140.0157 652.7008 227.2757 664.7008 ] /Subtype /Link /Type /Annot >> endobj 253 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 755 0 R /XYZ 40.01575 243.7008 0 ] /Rect [ 544.1398 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 267.7008 0 ] /Rect [ 544.1398 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot >> endobj 254 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 634.7008 211.1357 646.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 116.7008 0 ] /Rect [ 140.0157 634.7008 211.1357 646.7008 ] /Subtype /Link /Type /Annot >> endobj 255 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 116.7008 0 ] /Rect [ 544.1398 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot >> endobj 256 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 271.9008 0 ] /Rect [ 140.0157 616.7008 197.2457 628.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 756 0 R /XYZ 40.01575 387.5008 0 ] /Rect [ 140.0157 616.7008 197.2457 628.7008 ] /Subtype /Link /Type /Annot >> endobj 257 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 271.9008 0 ] /Rect [ 544.1398 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 756 0 R /XYZ 40.01575 387.5008 0 ] /Rect [ 544.1398 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot >> endobj 258 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 120.0157 598.7008 215.5857 610.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 120.0157 598.7008 215.5857 610.7008 ] /Subtype /Link /Type /Annot >> endobj 259 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 544.1398 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 544.1398 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot >> endobj 260 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 509.7008 0 ] /Rect [ 140.0157 580.7008 245.5957 592.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 653.7008 0 ] /Rect [ 140.0157 580.7008 245.5957 592.7008 ] /Subtype /Link /Type /Annot >> endobj 261 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 509.7008 0 ] /Rect [ 544.1398 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 653.7008 0 ] /Rect [ 544.1398 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot >> endobj 262 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 442.1008 0 ] /Rect [ 140.0157 562.7008 282.2857 574.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 586.1008 0 ] /Rect [ 140.0157 562.7008 282.2857 574.7008 ] /Subtype /Link /Type /Annot >> endobj 263 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 442.1008 0 ] /Rect [ 544.1398 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 586.1008 0 ] /Rect [ 544.1398 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot >> endobj 264 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 374.5008 0 ] /Rect [ 140.0157 544.7008 282.8257 556.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 518.5008 0 ] /Rect [ 140.0157 544.7008 282.8257 556.7008 ] /Subtype /Link /Type /Annot >> endobj 265 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 374.5008 0 ] /Rect [ 544.1398 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 518.5008 0 ] /Rect [ 544.1398 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot >> endobj 266 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 288.9008 0 ] /Rect [ 140.0157 526.7008 233.3757 538.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 432.9008 0 ] /Rect [ 140.0157 526.7008 233.3757 538.7008 ] /Subtype /Link /Type /Annot >> endobj 267 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 288.9008 0 ] /Rect [ 544.1398 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 432.9008 0 ] /Rect [ 544.1398 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot >> endobj 268 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 221.3008 0 ] /Rect [ 140.0157 508.7008 178.9157 520.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 365.3008 0 ] /Rect [ 140.0157 508.7008 178.9157 520.7008 ] /Subtype /Link /Type /Annot >> endobj 269 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 221.3008 0 ] /Rect [ 544.1398 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 365.3008 0 ] /Rect [ 544.1398 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot >> endobj 270 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 625.3008 0 ] /Rect [ 140.0157 490.7008 208.3857 502.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 490.7008 208.3857 502.7008 ] /Subtype /Link /Type /Annot >> endobj 271 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 625.3008 0 ] /Rect [ 544.1398 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot >> endobj 272 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 575.7008 0 ] /Rect [ 140.0157 472.7008 193.9357 484.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 472.7008 193.9357 484.7008 ] /Subtype /Link /Type /Annot >> endobj 273 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 575.7008 0 ] /Rect [ 544.1398 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 544.1398 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot >> endobj 274 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 526.1008 0 ] /Rect [ 140.0157 454.7008 216.7157 466.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 676.5008 0 ] /Rect [ 140.0157 454.7008 216.7157 466.7008 ] /Subtype /Link /Type /Annot >> endobj 275 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 760 0 R /XYZ 40.01575 526.1008 0 ] /Rect [ 544.1398 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 759 0 R /XYZ 40.01575 676.5008 0 ] /Rect [ 544.1398 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot >> endobj 276 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 763 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 436.7008 191.1557 448.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 762 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 436.7008 191.1557 448.7008 ] /Subtype /Link /Type /Annot >> endobj 277 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 763 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 544.1398 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 762 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot >> endobj 278 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 763 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 140.0157 418.7008 213.9357 430.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 762 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 418.7008 213.9357 430.7008 ] /Subtype /Link /Type /Annot >> endobj 279 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 763 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 544.1398 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 762 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 544.1398 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot >> endobj 280 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 207.7008 0 ] /Rect [ 140.0157 400.7008 193.3757 412.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 363.7008 0 ] /Rect [ 140.0157 400.7008 193.3757 412.7008 ] /Subtype /Link /Type /Annot >> endobj 281 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 207.7008 0 ] /Rect [ 544.1398 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 363.7008 0 ] /Rect [ 544.1398 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot >> endobj 282 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 158.1008 0 ] /Rect [ 140.0157 382.7008 216.1557 394.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 314.1008 0 ] /Rect [ 140.0157 382.7008 216.1557 394.7008 ] /Subtype /Link /Type /Annot >> endobj 283 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 158.1008 0 ] /Rect [ 544.1398 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 764 0 R /XYZ 40.01575 314.1008 0 ] /Rect [ 544.1398 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot >> endobj 284 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 767 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 140.0157 364.7008 201.1557 376.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 471.7008 0 ] /Rect [ 140.0157 364.7008 201.1557 376.7008 ] /Subtype /Link /Type /Annot >> endobj 285 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 767 0 R /XYZ 40.01575 315.7008 0 ] /Rect [ 544.1398 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 471.7008 0 ] /Rect [ 544.1398 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot >> endobj 286 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 767 0 R /XYZ 40.01575 266.1008 0 ] /Rect [ 140.0157 346.7008 199.4857 358.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 422.1008 0 ] /Rect [ 140.0157 346.7008 199.4857 358.7008 ] /Subtype /Link /Type /Annot >> endobj 287 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 767 0 R /XYZ 40.01575 266.1008 0 ] /Rect [ 544.1398 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 422.1008 0 ] /Rect [ 544.1398 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot >> endobj 288 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 769 0 R /XYZ 40.01575 711.7008 0 ] /Rect [ 140.0157 328.7008 222.8257 340.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 150.5008 0 ] /Rect [ 140.0157 328.7008 222.8257 340.7008 ] /Subtype /Link /Type /Annot >> endobj 289 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 769 0 R /XYZ 40.01575 711.7008 0 ] /Rect [ 544.1398 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 766 0 R /XYZ 40.01575 150.5008 0 ] /Rect [ 544.1398 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot >> endobj 290 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 769 0 R /XYZ 40.01575 488.1008 0 ] /Rect [ 140.0157 310.7008 223.9357 322.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 768 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 310.7008 223.9357 322.7008 ] /Subtype /Link /Type /Annot >> endobj 291 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 769 0 R /XYZ 40.01575 488.1008 0 ] /Rect [ 544.1398 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 768 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 544.1398 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot >> endobj 292 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 774 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 292.7008 196.1557 304.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 773 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 292.7008 196.1557 304.7008 ] /Subtype /Link /Type /Annot >> endobj 293 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 774 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 544.1398 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 773 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 544.1398 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot >> endobj 294 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 774 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 140.0157 274.7008 218.9357 286.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 773 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 274.7008 218.9357 286.7008 ] /Subtype /Link /Type /Annot >> endobj 295 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 774 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 544.1398 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 773 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 544.1398 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot >> endobj 296 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 519.7008 0 ] /Rect [ 140.0157 256.7008 196.7057 268.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 256.7008 196.7057 268.7008 ] /Subtype /Link /Type /Annot >> endobj 297 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 519.7008 0 ] /Rect [ 544.1398 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 544.1398 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot >> endobj 298 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 470.1008 0 ] /Rect [ 140.0157 238.7008 219.4857 250.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 140.0157 238.7008 219.4857 250.7008 ] /Subtype /Link /Type /Annot >> endobj 299 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 470.1008 0 ] /Rect [ 544.1398 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 544.1398 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot >> endobj 300 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 420.5008 0 ] /Rect [ 140.0157 220.7008 195.5957 232.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 540.5008 0 ] /Rect [ 140.0157 220.7008 195.5957 232.7008 ] /Subtype /Link /Type /Annot >> endobj 301 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 420.5008 0 ] /Rect [ 544.1398 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 540.5008 0 ] /Rect [ 544.1398 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot >> endobj 302 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 370.9008 0 ] /Rect [ 140.0157 202.7008 229.4957 214.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 490.9008 0 ] /Rect [ 140.0157 202.7008 229.4957 214.7008 ] /Subtype /Link /Type /Annot >> endobj 303 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 370.9008 0 ] /Rect [ 544.1398 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 490.9008 0 ] /Rect [ 544.1398 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot >> endobj 304 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 321.3008 0 ] /Rect [ 140.0157 184.7008 225.0557 196.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 441.3008 0 ] /Rect [ 140.0157 184.7008 225.0557 196.7008 ] /Subtype /Link /Type /Annot >> endobj 305 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 321.3008 0 ] /Rect [ 544.1398 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 441.3008 0 ] /Rect [ 544.1398 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot >> endobj 306 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 779 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 140.0157 166.7008 208.3757 178.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 777 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 166.7008 208.3757 178.7008 ] /Subtype /Link /Type /Annot >> endobj 307 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 779 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 544.1398 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 777 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 544.1398 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot >> endobj 308 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 779 0 R /XYZ 40.01575 518.1008 0 ] /Rect [ 140.0157 148.7008 213.9357 160.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 777 0 R /XYZ 40.01575 638.1008 0 ] /Rect [ 140.0157 148.7008 213.9357 160.7008 ] /Subtype /Link /Type /Annot >> endobj 309 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 779 0 R /XYZ 40.01575 518.1008 0 ] /Rect [ 544.1398 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 777 0 R /XYZ 40.01575 638.1008 0 ] /Rect [ 544.1398 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot >> endobj 310 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 411.7008 0 ] /Rect [ 120.0157 130.7008 155.0257 142.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 120.0157 130.7008 155.0257 142.7008 ] /Subtype /Link /Type /Annot >> endobj 311 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 411.7008 0 ] /Rect [ 544.1398 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 544.1398 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot >> endobj 312 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 359.7008 0 ] /Rect [ 140.0157 112.7008 212.2757 124.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 647.7008 0 ] /Rect [ 140.0157 112.7008 212.2757 124.7008 ] /Subtype /Link /Type /Annot >> endobj 313 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 359.7008 0 ] /Rect [ 544.1398 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 647.7008 0 ] /Rect [ 544.1398 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot >> endobj 314 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 310.1008 0 ] /Rect [ 140.0157 94.70079 217.8057 106.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 598.1008 0 ] /Rect [ 140.0157 94.70079 217.8057 106.7008 ] /Subtype /Link /Type /Annot >> endobj 315 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 310.1008 0 ] /Rect [ 544.1398 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 598.1008 0 ] /Rect [ 544.1398 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot >> endobj 316 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 291.7008 0 ] /Rect [ 100.0157 76.70079 240.0357 88.70079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 100.0157 76.70079 240.0357 88.70079 ] /Subtype /Link /Type /Annot >> endobj 317 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 291.7008 0 ] /Rect [ 544.1398 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 567.7008 0 ] /Rect [ 544.1398 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot >> endobj 318 0 obj @@ -1641,7 +1641,7 @@ endobj 280 0 R 281 0 R 282 0 R 283 0 R 284 0 R 285 0 R 286 0 R 287 0 R 288 0 R 289 0 R 290 0 R 291 0 R 292 0 R 293 0 R 294 0 R 295 0 R 296 0 R 297 0 R 298 0 R 299 0 R 300 0 R 301 0 R 302 0 R 303 0 R 304 0 R 305 0 R 306 0 R 307 0 R 308 0 R 309 0 R - 310 0 R 311 0 R 312 0 R 313 0 R 314 0 R 315 0 R 316 0 R 317 0 R ] /Contents 1201 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 310 0 R 311 0 R 312 0 R 313 0 R 314 0 R 315 0 R 316 0 R 317 0 R ] /Contents 1198 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -1651,392 +1651,392 @@ endobj endobj 319 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 87.30079 0 ] /Rect [ 100.0157 760.7008 236.7057 772.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 363.3008 0 ] /Rect [ 100.0157 760.7008 236.7057 772.7008 ] /Subtype /Link /Type /Annot >> endobj 320 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 87.30079 0 ] /Rect [ 544.1398 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 363.3008 0 ] /Rect [ 544.1398 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot >> endobj 321 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 100.0157 742.7008 195.0457 754.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 176.9008 0 ] /Rect [ 100.0157 742.7008 195.0457 754.7008 ] /Subtype /Link /Type /Annot >> endobj 322 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 544.1398 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 176.9008 0 ] /Rect [ 544.1398 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot >> endobj 323 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 525.3008 0 ] /Rect [ 100.0157 724.7008 205.0557 736.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 86.50079 0 ] /Rect [ 100.0157 724.7008 205.0557 736.7008 ] /Subtype /Link /Type /Annot >> endobj 324 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 525.3008 0 ] /Rect [ 544.1398 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 797 0 R /XYZ 40.01575 86.50079 0 ] /Rect [ 544.1398 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot >> endobj 325 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 446.9008 0 ] /Rect [ 80.01575 706.7008 165.0357 718.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 717.7008 0 ] /Rect [ 80.01575 706.7008 165.0357 718.7008 ] /Subtype /Link /Type /Annot >> endobj 326 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 446.9008 0 ] /Rect [ 544.1398 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 717.7008 0 ] /Rect [ 544.1398 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot >> endobj 327 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 390.1008 0 ] /Rect [ 100.0157 688.7008 152.2657 700.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 660.9008 0 ] /Rect [ 100.0157 688.7008 152.2657 700.7008 ] /Subtype /Link /Type /Annot >> endobj 328 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 390.1008 0 ] /Rect [ 544.1398 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 798 0 R /XYZ 40.01575 660.9008 0 ] /Rect [ 544.1398 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot >> endobj 329 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 100.0157 670.7008 137.8057 682.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 484.9008 0 ] /Rect [ 100.0157 670.7008 137.8057 682.7008 ] /Subtype /Link /Type /Annot >> endobj 330 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 484.9008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot >> endobj 331 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 721.3008 0 ] /Rect [ 120.0157 652.7008 198.3857 664.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 430.5008 0 ] /Rect [ 120.0157 652.7008 198.3857 664.7008 ] /Subtype /Link /Type /Annot >> endobj 332 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 721.3008 0 ] /Rect [ 538.5798 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 430.5008 0 ] /Rect [ 538.5798 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot >> endobj 333 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 669.3008 0 ] /Rect [ 140.0157 634.7008 198.9357 646.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 378.5008 0 ] /Rect [ 140.0157 634.7008 198.9357 646.7008 ] /Subtype /Link /Type /Annot >> endobj 334 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 669.3008 0 ] /Rect [ 538.5798 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 378.5008 0 ] /Rect [ 538.5798 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot >> endobj 335 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 619.7008 0 ] /Rect [ 140.0157 616.7008 193.9357 628.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 328.9008 0 ] /Rect [ 140.0157 616.7008 193.9357 628.7008 ] /Subtype /Link /Type /Annot >> endobj 336 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 619.7008 0 ] /Rect [ 538.5798 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 328.9008 0 ] /Rect [ 538.5798 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot >> endobj 337 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 570.1008 0 ] /Rect [ 140.0157 598.7008 218.9357 610.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 279.3008 0 ] /Rect [ 140.0157 598.7008 218.9357 610.7008 ] /Subtype /Link /Type /Annot >> endobj 338 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 570.1008 0 ] /Rect [ 538.5798 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 279.3008 0 ] /Rect [ 538.5798 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot >> endobj 339 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 520.5008 0 ] /Rect [ 140.0157 580.7008 196.7157 592.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 229.7008 0 ] /Rect [ 140.0157 580.7008 196.7157 592.7008 ] /Subtype /Link /Type /Annot >> endobj 340 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 520.5008 0 ] /Rect [ 538.5798 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 229.7008 0 ] /Rect [ 538.5798 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot >> endobj 341 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 470.9008 0 ] /Rect [ 140.0157 562.7008 213.3857 574.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 180.1008 0 ] /Rect [ 140.0157 562.7008 213.3857 574.7008 ] /Subtype /Link /Type /Annot >> endobj 342 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 470.9008 0 ] /Rect [ 538.5798 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 802 0 R /XYZ 40.01575 180.1008 0 ] /Rect [ 538.5798 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot >> endobj 343 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 295.3008 0 ] /Rect [ 140.0157 544.7008 230.6157 556.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 803 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 140.0157 544.7008 230.6157 556.7008 ] /Subtype /Link /Type /Annot >> endobj 344 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 807 0 R /XYZ 40.01575 295.3008 0 ] /Rect [ 538.5798 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 803 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 538.5798 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot >> endobj 345 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 808 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 526.7008 224.4957 538.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 803 0 R /XYZ 40.01575 524.1008 0 ] /Rect [ 140.0157 526.7008 224.4957 538.7008 ] /Subtype /Link /Type /Annot >> endobj 346 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 808 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 803 0 R /XYZ 40.01575 524.1008 0 ] /Rect [ 538.5798 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot >> endobj 347 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 815 0 R /XYZ 40.01575 291.7008 0 ] /Rect [ 140.0157 508.7008 230.0657 520.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 508.7008 230.0657 520.7008 ] /Subtype /Link /Type /Annot >> endobj 348 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 815 0 R /XYZ 40.01575 291.7008 0 ] /Rect [ 538.5798 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot >> endobj 349 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 815 0 R /XYZ 40.01575 242.1008 0 ] /Rect [ 140.0157 490.7008 215.5957 502.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 490.7008 215.5957 502.7008 ] /Subtype /Link /Type /Annot >> endobj 350 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 815 0 R /XYZ 40.01575 242.1008 0 ] /Rect [ 538.5798 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 538.5798 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot >> endobj 351 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 140.0157 472.7008 196.7157 484.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 454.5008 0 ] /Rect [ 140.0157 472.7008 196.7157 484.7008 ] /Subtype /Link /Type /Annot >> endobj 352 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 538.5798 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 454.5008 0 ] /Rect [ 538.5798 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot >> endobj 353 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 626.1008 0 ] /Rect [ 140.0157 454.7008 249.5057 466.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 404.9008 0 ] /Rect [ 140.0157 454.7008 249.5057 466.7008 ] /Subtype /Link /Type /Annot >> endobj 354 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 626.1008 0 ] /Rect [ 538.5798 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 812 0 R /XYZ 40.01575 404.9008 0 ] /Rect [ 538.5798 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot >> endobj 355 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 360.5008 0 ] /Rect [ 140.0157 436.7008 229.4957 448.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 818 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 436.7008 229.4957 448.7008 ] /Subtype /Link /Type /Annot >> endobj 356 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 822 0 R /XYZ 40.01575 360.5008 0 ] /Rect [ 538.5798 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 818 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 538.5798 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot >> endobj 357 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 140.0157 418.7008 250.0657 430.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 418.7008 250.0657 430.7008 ] /Subtype /Link /Type /Annot >> endobj 358 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 579.7008 0 ] /Rect [ 538.5798 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot >> endobj 359 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 332.1008 0 ] /Rect [ 140.0157 400.7008 215.0357 412.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 528.1008 0 ] /Rect [ 140.0157 400.7008 215.0357 412.7008 ] /Subtype /Link /Type /Annot >> endobj 360 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 332.1008 0 ] /Rect [ 538.5798 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 528.1008 0 ] /Rect [ 538.5798 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot >> endobj 361 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 382.7008 207.2657 394.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 238.5008 0 ] /Rect [ 140.0157 382.7008 207.2657 394.7008 ] /Subtype /Link /Type /Annot >> endobj 362 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 825 0 R /XYZ 40.01575 238.5008 0 ] /Rect [ 538.5798 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot >> endobj 363 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 558.1008 0 ] /Rect [ 140.0157 364.7008 212.2657 376.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 140.0157 364.7008 212.2657 376.7008 ] /Subtype /Link /Type /Annot >> endobj 364 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 558.1008 0 ] /Rect [ 538.5798 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 538.5798 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot >> endobj 365 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 100.5008 0 ] /Rect [ 140.0157 346.7008 238.9657 358.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 266.1008 0 ] /Rect [ 140.0157 346.7008 238.9657 358.7008 ] /Subtype /Link /Type /Annot >> endobj 366 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 832 0 R /XYZ 40.01575 100.5008 0 ] /Rect [ 538.5798 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 828 0 R /XYZ 40.01575 266.1008 0 ] /Rect [ 538.5798 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot >> endobj 367 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 836 0 R /XYZ 40.01575 471.7008 0 ] /Rect [ 140.0157 328.7008 207.8257 340.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 834 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 140.0157 328.7008 207.8257 340.7008 ] /Subtype /Link /Type /Annot >> endobj 368 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 836 0 R /XYZ 40.01575 471.7008 0 ] /Rect [ 538.5798 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 834 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 538.5798 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot >> endobj 369 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 836 0 R /XYZ 40.01575 242.1008 0 ] /Rect [ 140.0157 310.7008 242.2757 322.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 834 0 R /XYZ 40.01575 398.1008 0 ] /Rect [ 140.0157 310.7008 242.2757 322.7008 ] /Subtype /Link /Type /Annot >> endobj 370 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 836 0 R /XYZ 40.01575 242.1008 0 ] /Rect [ 538.5798 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 834 0 R /XYZ 40.01575 398.1008 0 ] /Rect [ 538.5798 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot >> endobj 371 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 840 0 R /XYZ 40.01575 206.1008 0 ] /Rect [ 140.0157 292.7008 224.4857 304.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 838 0 R /XYZ 40.01575 355.7008 0 ] /Rect [ 140.0157 292.7008 224.4857 304.7008 ] /Subtype /Link /Type /Annot >> endobj 372 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 840 0 R /XYZ 40.01575 206.1008 0 ] /Rect [ 538.5798 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 838 0 R /XYZ 40.01575 355.7008 0 ] /Rect [ 538.5798 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot >> endobj 373 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 274.7008 215.5857 286.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 838 0 R /XYZ 40.01575 144.1008 0 ] /Rect [ 140.0157 274.7008 215.5857 286.7008 ] /Subtype /Link /Type /Annot >> endobj 374 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 538.5798 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 838 0 R /XYZ 40.01575 144.1008 0 ] /Rect [ 538.5798 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot >> endobj 375 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 392.1008 0 ] /Rect [ 140.0157 256.7008 203.9257 268.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 840 0 R /XYZ 40.01575 420.5008 0 ] /Rect [ 140.0157 256.7008 203.9257 268.7008 ] /Subtype /Link /Type /Annot >> endobj 376 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 392.1008 0 ] /Rect [ 538.5798 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 840 0 R /XYZ 40.01575 420.5008 0 ] /Rect [ 538.5798 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot >> endobj 377 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 174.5008 0 ] /Rect [ 140.0157 238.7008 204.4757 250.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 238.7008 204.4757 250.7008 ] /Subtype /Link /Type /Annot >> endobj 378 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 174.5008 0 ] /Rect [ 538.5798 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot >> endobj 379 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 140.0157 220.7008 222.8257 232.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 564.1008 0 ] /Rect [ 140.0157 220.7008 222.8257 232.7008 ] /Subtype /Link /Type /Annot >> endobj 380 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 538.5798 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 564.1008 0 ] /Rect [ 538.5798 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot >> endobj 381 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 476.1008 0 ] /Rect [ 140.0157 202.7008 197.2457 214.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 364.5008 0 ] /Rect [ 140.0157 202.7008 197.2457 214.7008 ] /Subtype /Link /Type /Annot >> endobj 382 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 476.1008 0 ] /Rect [ 538.5798 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 844 0 R /XYZ 40.01575 364.5008 0 ] /Rect [ 538.5798 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot >> endobj 383 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 192.5008 0 ] /Rect [ 140.0157 184.7008 245.6057 196.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 850 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 140.0157 184.7008 245.6057 196.7008 ] /Subtype /Link /Type /Annot >> endobj 384 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 848 0 R /XYZ 40.01575 192.5008 0 ] /Rect [ 538.5798 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 850 0 R /XYZ 40.01575 687.7008 0 ] /Rect [ 538.5798 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot >> endobj 385 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 857 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 140.0157 166.7008 222.2557 178.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 850 0 R /XYZ 40.01575 452.1008 0 ] /Rect [ 140.0157 166.7008 222.2557 178.7008 ] /Subtype /Link /Type /Annot >> endobj 386 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 857 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 538.5798 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 850 0 R /XYZ 40.01575 452.1008 0 ] /Rect [ 538.5798 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot >> endobj 387 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 857 0 R /XYZ 40.01575 320.1008 0 ] /Rect [ 140.0157 148.7008 195.5757 160.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 148.7008 195.5757 160.7008 ] /Subtype /Link /Type /Annot >> endobj 388 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 857 0 R /XYZ 40.01575 320.1008 0 ] /Rect [ 538.5798 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot >> endobj 389 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 130.7008 210.0457 142.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 498.1008 0 ] /Rect [ 140.0157 130.7008 210.0457 142.7008 ] /Subtype /Link /Type /Annot >> endobj 390 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 498.1008 0 ] /Rect [ 538.5798 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot >> endobj 391 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 384.1008 0 ] /Rect [ 140.0157 112.7008 225.0457 124.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 106.5008 0 ] /Rect [ 140.0157 112.7008 225.0457 124.7008 ] /Subtype /Link /Type /Annot >> endobj 392 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 384.1008 0 ] /Rect [ 538.5798 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 854 0 R /XYZ 40.01575 106.5008 0 ] /Rect [ 538.5798 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot >> endobj 393 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 184.5008 0 ] /Rect [ 140.0157 94.70079 215.0457 106.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 140.0157 94.70079 215.0457 106.7008 ] /Subtype /Link /Type /Annot >> endobj 394 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 184.5008 0 ] /Rect [ 538.5798 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 538.5798 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot >> endobj 395 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 76.70079 223.3857 88.70079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 362.1008 0 ] /Rect [ 140.0157 76.70079 223.3857 88.70079 ] /Subtype /Link /Type /Annot >> endobj 396 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 538.5798 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 362.1008 0 ] /Rect [ 538.5798 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot >> endobj 397 0 obj @@ -2048,7 +2048,7 @@ endobj 359 0 R 360 0 R 361 0 R 362 0 R 363 0 R 364 0 R 365 0 R 366 0 R 367 0 R 368 0 R 369 0 R 370 0 R 371 0 R 372 0 R 373 0 R 374 0 R 375 0 R 376 0 R 377 0 R 378 0 R 379 0 R 380 0 R 381 0 R 382 0 R 383 0 R 384 0 R 385 0 R 386 0 R 387 0 R 388 0 R - 389 0 R 390 0 R 391 0 R 392 0 R 393 0 R 394 0 R 395 0 R 396 0 R ] /Contents 1202 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 389 0 R 390 0 R 391 0 R 392 0 R 393 0 R 394 0 R 395 0 R 396 0 R ] /Contents 1199 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2058,392 +2058,392 @@ endobj endobj 398 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 440.1008 0 ] /Rect [ 140.0157 760.7008 211.7057 772.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 150.5008 0 ] /Rect [ 140.0157 760.7008 211.7057 772.7008 ] /Subtype /Link /Type /Annot >> endobj 399 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 440.1008 0 ] /Rect [ 538.5798 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 858 0 R /XYZ 40.01575 150.5008 0 ] /Rect [ 538.5798 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot >> endobj 400 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 168.5008 0 ] /Rect [ 140.0157 742.7008 198.9157 754.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 591.7008 0 ] /Rect [ 140.0157 742.7008 198.9157 754.7008 ] /Subtype /Link /Type /Annot >> endobj 401 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 863 0 R /XYZ 40.01575 168.5008 0 ] /Rect [ 538.5798 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 591.7008 0 ] /Rect [ 538.5798 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot >> endobj 402 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 724.7008 198.3757 736.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 356.1008 0 ] /Rect [ 140.0157 724.7008 198.3757 736.7008 ] /Subtype /Link /Type /Annot >> endobj 403 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 538.5798 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 356.1008 0 ] /Rect [ 538.5798 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot >> endobj 404 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 602.1008 0 ] /Rect [ 140.0157 706.7008 193.3757 718.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 306.5008 0 ] /Rect [ 140.0157 706.7008 193.3757 718.7008 ] /Subtype /Link /Type /Annot >> endobj 405 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 602.1008 0 ] /Rect [ 538.5798 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 306.5008 0 ] /Rect [ 538.5798 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot >> endobj 406 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 552.5008 0 ] /Rect [ 140.0157 688.7008 196.7157 700.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 256.9008 0 ] /Rect [ 140.0157 688.7008 196.7157 700.7008 ] /Subtype /Link /Type /Annot >> endobj 407 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 552.5008 0 ] /Rect [ 538.5798 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 256.9008 0 ] /Rect [ 538.5798 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot >> endobj 408 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 502.9008 0 ] /Rect [ 140.0157 670.7008 201.7157 682.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 207.3008 0 ] /Rect [ 140.0157 670.7008 201.7157 682.7008 ] /Subtype /Link /Type /Annot >> endobj 409 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 502.9008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 207.3008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot >> endobj 410 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 453.3008 0 ] /Rect [ 140.0157 653.4508 196.7157 665.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 157.7008 0 ] /Rect [ 140.0157 653.4508 196.7157 665.4508 ] /Subtype /Link /Type /Annot >> endobj 411 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 453.3008 0 ] /Rect [ 538.5798 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 157.7008 0 ] /Rect [ 538.5798 653.4508 555.2598 665.4508 ] /Subtype /Link /Type /Annot >> endobj 412 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 403.7008 0 ] /Rect [ 140.0157 634.7008 212.2657 646.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 108.1008 0 ] /Rect [ 140.0157 634.7008 212.2657 646.7008 ] /Subtype /Link /Type /Annot >> endobj 413 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 869 0 R /XYZ 40.01575 403.7008 0 ] /Rect [ 538.5798 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 860 0 R /XYZ 40.01575 108.1008 0 ] /Rect [ 538.5798 635.4508 555.2598 647.4508 ] /Subtype /Link /Type /Annot >> endobj 414 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 616.7008 230.0657 628.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 868 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 140.0157 616.7008 230.0657 628.7008 ] /Subtype /Link /Type /Annot >> endobj 415 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 868 0 R /XYZ 40.01575 507.7008 0 ] /Rect [ 538.5798 617.4508 555.2598 629.4508 ] /Subtype /Link /Type /Annot >> endobj 416 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 598.7008 183.9257 610.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 868 0 R /XYZ 40.01575 458.1008 0 ] /Rect [ 140.0157 598.7008 183.9257 610.7008 ] /Subtype /Link /Type /Annot >> endobj 417 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 538.5798 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 868 0 R /XYZ 40.01575 458.1008 0 ] /Rect [ 538.5798 599.4508 555.2598 611.4508 ] /Subtype /Link /Type /Annot >> endobj 418 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 580.7008 202.2557 592.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 870 0 R /XYZ 40.01575 399.7008 0 ] /Rect [ 140.0157 580.7008 202.2557 592.7008 ] /Subtype /Link /Type /Annot >> endobj 419 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 538.5798 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 870 0 R /XYZ 40.01575 399.7008 0 ] /Rect [ 538.5798 581.4508 555.2598 593.4508 ] /Subtype /Link /Type /Annot >> endobj 420 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 140.0157 562.7008 251.1657 574.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 870 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 140.0157 562.7008 251.1657 574.7008 ] /Subtype /Link /Type /Annot >> endobj 421 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 590.1008 0 ] /Rect [ 538.5798 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 870 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 538.5798 563.4508 555.2598 575.4508 ] /Subtype /Link /Type /Annot >> endobj 422 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 188.5008 0 ] /Rect [ 140.0157 544.7008 214.4757 556.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 544.7008 214.4757 556.7008 ] /Subtype /Link /Type /Annot >> endobj 423 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 188.5008 0 ] /Rect [ 538.5798 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 872 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 538.5798 545.4508 555.2598 557.4508 ] /Subtype /Link /Type /Annot >> endobj 424 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 526.7008 196.7157 538.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 874 0 R /XYZ 40.01575 495.7008 0 ] /Rect [ 140.0157 526.7008 196.7157 538.7008 ] /Subtype /Link /Type /Annot >> endobj 425 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 538.5798 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 874 0 R /XYZ 40.01575 495.7008 0 ] /Rect [ 538.5798 527.4508 555.2598 539.4508 ] /Subtype /Link /Type /Annot >> endobj 426 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 650.1008 0 ] /Rect [ 140.0157 508.7008 220.0557 520.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 874 0 R /XYZ 40.01575 446.1008 0 ] /Rect [ 140.0157 508.7008 220.0557 520.7008 ] /Subtype /Link /Type /Annot >> endobj 427 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 650.1008 0 ] /Rect [ 538.5798 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 874 0 R /XYZ 40.01575 446.1008 0 ] /Rect [ 538.5798 509.4508 555.2598 521.4508 ] /Subtype /Link /Type /Annot >> endobj 428 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 213.5008 0 ] /Rect [ 140.0157 490.7008 245.0457 502.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 140.0157 490.7008 245.0457 502.7008 ] /Subtype /Link /Type /Annot >> endobj 429 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 213.5008 0 ] /Rect [ 538.5798 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 875 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 538.5798 491.4508 555.2598 503.4508 ] /Subtype /Link /Type /Annot >> endobj 430 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 140.0157 472.7008 236.7257 484.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 876 0 R /XYZ 40.01575 435.7008 0 ] /Rect [ 140.0157 472.7008 236.7257 484.7008 ] /Subtype /Link /Type /Annot >> endobj 431 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 538.5798 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 876 0 R /XYZ 40.01575 435.7008 0 ] /Rect [ 538.5798 473.4508 555.2598 485.4508 ] /Subtype /Link /Type /Annot >> endobj 432 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 881 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 454.7008 229.4957 466.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 877 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 140.0157 454.7008 229.4957 466.7008 ] /Subtype /Link /Type /Annot >> endobj 433 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 881 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 877 0 R /XYZ 40.01575 603.7008 0 ] /Rect [ 538.5798 455.4508 555.2598 467.4508 ] /Subtype /Link /Type /Annot >> endobj 434 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 881 0 R /XYZ 40.01575 156.9008 0 ] /Rect [ 140.0157 436.7008 229.4957 448.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 436.7008 229.4957 448.7008 ] /Subtype /Link /Type /Annot >> endobj 435 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 881 0 R /XYZ 40.01575 156.9008 0 ] /Rect [ 538.5798 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 538.5798 437.4508 555.2598 449.4508 ] /Subtype /Link /Type /Annot >> endobj 436 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 346.5008 0 ] /Rect [ 140.0157 418.7008 202.2557 430.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 418.7008 202.2557 430.7008 ] /Subtype /Link /Type /Annot >> endobj 437 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 346.5008 0 ] /Rect [ 538.5798 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 419.4508 555.2598 431.4508 ] /Subtype /Link /Type /Annot >> endobj 438 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 296.9008 0 ] /Rect [ 140.0157 400.7008 191.1557 412.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 400.7008 191.1557 412.7008 ] /Subtype /Link /Type /Annot >> endobj 439 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 296.9008 0 ] /Rect [ 538.5798 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 538.5798 401.4508 555.2598 413.4508 ] /Subtype /Link /Type /Annot >> endobj 440 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 247.3008 0 ] /Rect [ 140.0157 382.7008 202.8257 394.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 676.5008 0 ] /Rect [ 140.0157 382.7008 202.8257 394.7008 ] /Subtype /Link /Type /Annot >> endobj 441 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 882 0 R /XYZ 40.01575 247.3008 0 ] /Rect [ 538.5798 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 676.5008 0 ] /Rect [ 538.5798 383.4508 555.2598 395.4508 ] /Subtype /Link /Type /Annot >> endobj 442 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 885 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 364.7008 215.5957 376.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 512.9008 0 ] /Rect [ 140.0157 364.7008 215.5957 376.7008 ] /Subtype /Link /Type /Annot >> endobj 443 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 885 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 880 0 R /XYZ 40.01575 512.9008 0 ] /Rect [ 538.5798 365.4508 555.2598 377.4508 ] /Subtype /Link /Type /Annot >> endobj 444 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 885 0 R /XYZ 40.01575 264.1008 0 ] /Rect [ 140.0157 346.7008 233.9357 358.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 883 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 346.7008 233.9357 358.7008 ] /Subtype /Link /Type /Annot >> endobj 445 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 885 0 R /XYZ 40.01575 264.1008 0 ] /Rect [ 538.5798 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 883 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 538.5798 347.4508 555.2598 359.4508 ] /Subtype /Link /Type /Annot >> endobj 446 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 888 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 140.0157 328.7008 221.1657 340.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 883 0 R /XYZ 40.01575 337.1008 0 ] /Rect [ 140.0157 328.7008 221.1657 340.7008 ] /Subtype /Link /Type /Annot >> endobj 447 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 888 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 538.5798 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 883 0 R /XYZ 40.01575 337.1008 0 ] /Rect [ 538.5798 329.4508 555.2598 341.4508 ] /Subtype /Link /Type /Annot >> endobj 448 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 888 0 R /XYZ 40.01575 200.1008 0 ] /Rect [ 140.0157 310.7008 221.1657 322.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 140.0157 310.7008 221.1657 322.7008 ] /Subtype /Link /Type /Annot >> endobj 449 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 888 0 R /XYZ 40.01575 200.1008 0 ] /Rect [ 538.5798 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 639.7008 0 ] /Rect [ 538.5798 311.4508 555.2598 323.4508 ] /Subtype /Link /Type /Annot >> endobj 450 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 140.0157 292.7008 205.0357 304.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 355.1008 0 ] /Rect [ 140.0157 292.7008 205.0357 304.7008 ] /Subtype /Link /Type /Annot >> endobj 451 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 615.7008 0 ] /Rect [ 538.5798 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 355.1008 0 ] /Rect [ 538.5798 293.4508 555.2598 305.4508 ] /Subtype /Link /Type /Annot >> endobj 452 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 140.0157 274.7008 223.3757 286.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 140.0157 274.7008 223.3757 286.7008 ] /Subtype /Link /Type /Annot >> endobj 453 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 699.7008 0 ] /Rect [ 538.5798 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 538.5798 275.4508 555.2598 287.4508 ] /Subtype /Link /Type /Annot >> endobj 454 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 337.1008 0 ] /Rect [ 140.0157 256.7008 201.7157 268.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 256.7008 201.7157 268.7008 ] /Subtype /Link /Type /Annot >> endobj 455 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 337.1008 0 ] /Rect [ 538.5798 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 257.4508 555.2598 269.4508 ] /Subtype /Link /Type /Annot >> endobj 456 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 287.5008 0 ] /Rect [ 140.0157 238.7008 272.2957 250.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 238.7008 272.2957 250.7008 ] /Subtype /Link /Type /Annot >> endobj 457 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 287.5008 0 ] /Rect [ 538.5798 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 538.5798 239.4508 555.2598 251.4508 ] /Subtype /Link /Type /Annot >> endobj 458 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 220.7008 196.7157 232.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 553.5008 0 ] /Rect [ 140.0157 220.7008 196.7157 232.7008 ] /Subtype /Link /Type /Annot >> endobj 459 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 553.5008 0 ] /Rect [ 538.5798 221.4508 555.2598 233.4508 ] /Subtype /Link /Type /Annot >> endobj 460 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 140.0157 202.7008 202.8257 214.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 503.9008 0 ] /Rect [ 140.0157 202.7008 202.8257 214.7008 ] /Subtype /Link /Type /Annot >> endobj 461 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 726.1008 0 ] /Rect [ 538.5798 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 503.9008 0 ] /Rect [ 538.5798 203.4508 555.2598 215.4508 ] /Subtype /Link /Type /Annot >> endobj 462 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 514.5008 0 ] /Rect [ 140.0157 184.7008 215.5957 196.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 292.3008 0 ] /Rect [ 140.0157 184.7008 215.5957 196.7008 ] /Subtype /Link /Type /Annot >> endobj 463 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 514.5008 0 ] /Rect [ 538.5798 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 895 0 R /XYZ 40.01575 292.3008 0 ] /Rect [ 538.5798 185.4508 555.2598 197.4508 ] /Subtype /Link /Type /Annot >> endobj 464 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 170.9008 0 ] /Rect [ 140.0157 166.7008 233.9357 178.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 166.7008 233.9357 178.7008 ] /Subtype /Link /Type /Annot >> endobj 465 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 899 0 R /XYZ 40.01575 170.9008 0 ] /Rect [ 538.5798 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 538.5798 167.4508 555.2598 179.4508 ] /Subtype /Link /Type /Annot >> endobj 466 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 414.7008 0 ] /Rect [ 140.0157 148.7008 207.8257 160.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 193.1008 0 ] /Rect [ 140.0157 148.7008 207.8257 160.7008 ] /Subtype /Link /Type /Annot >> endobj 467 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 414.7008 0 ] /Rect [ 538.5798 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 897 0 R /XYZ 40.01575 193.1008 0 ] /Rect [ 538.5798 149.4508 555.2598 161.4508 ] /Subtype /Link /Type /Annot >> endobj 468 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 226.1008 0 ] /Rect [ 140.0157 130.7008 213.9257 142.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 140.0157 130.7008 213.9257 142.7008 ] /Subtype /Link /Type /Annot >> endobj 469 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 226.1008 0 ] /Rect [ 538.5798 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 723.7008 0 ] /Rect [ 538.5798 131.4508 555.2598 143.4508 ] /Subtype /Link /Type /Annot >> endobj 470 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 159.7008 0 ] /Rect [ 140.0157 112.7008 223.3857 124.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 140.0157 112.7008 223.3857 124.7008 ] /Subtype /Link /Type /Annot >> endobj 471 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 159.7008 0 ] /Rect [ 538.5798 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 651.7008 0 ] /Rect [ 538.5798 113.4508 555.2598 125.4508 ] /Subtype /Link /Type /Annot >> endobj 472 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 140.0157 94.70079 220.0557 106.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 467.1008 0 ] /Rect [ 140.0157 94.70079 220.0557 106.7008 ] /Subtype /Link /Type /Annot >> endobj 473 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 675.7008 0 ] /Rect [ 538.5798 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 467.1008 0 ] /Rect [ 538.5798 95.45079 555.2598 107.4508 ] /Subtype /Link /Type /Annot >> endobj 474 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 305.1008 0 ] /Rect [ 140.0157 76.70079 233.9357 88.70079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 96.50079 0 ] /Rect [ 140.0157 76.70079 233.9357 88.70079 ] /Subtype /Link /Type /Annot >> endobj 475 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 305.1008 0 ] /Rect [ 538.5798 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 902 0 R /XYZ 40.01575 96.50079 0 ] /Rect [ 538.5798 77.45079 555.2598 89.45079 ] /Subtype /Link /Type /Annot >> endobj 476 0 obj @@ -2455,7 +2455,7 @@ endobj 438 0 R 439 0 R 440 0 R 441 0 R 442 0 R 443 0 R 444 0 R 445 0 R 446 0 R 447 0 R 448 0 R 449 0 R 450 0 R 451 0 R 452 0 R 453 0 R 454 0 R 455 0 R 456 0 R 457 0 R 458 0 R 459 0 R 460 0 R 461 0 R 462 0 R 463 0 R 464 0 R 465 0 R 466 0 R 467 0 R - 468 0 R 469 0 R 470 0 R 471 0 R 472 0 R 473 0 R 474 0 R 475 0 R ] /Contents 1203 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 468 0 R 469 0 R 470 0 R 471 0 R 472 0 R 473 0 R 474 0 R 475 0 R ] /Contents 1200 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2465,68 +2465,68 @@ endobj endobj 477 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 140.0157 760.7008 201.7057 772.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 903 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 140.0157 760.7008 201.7057 772.7008 ] /Subtype /Link /Type /Annot >> endobj 478 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 627.7008 0 ] /Rect [ 538.5798 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 903 0 R /XYZ 40.01575 423.7008 0 ] /Rect [ 538.5798 761.4508 555.2598 773.4508 ] /Subtype /Link /Type /Annot >> endobj 479 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 443.1008 0 ] /Rect [ 140.0157 742.7008 216.1457 754.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 903 0 R /XYZ 40.01575 239.1008 0 ] /Rect [ 140.0157 742.7008 216.1457 754.7008 ] /Subtype /Link /Type /Annot >> endobj 480 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 443.1008 0 ] /Rect [ 538.5798 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 903 0 R /XYZ 40.01575 239.1008 0 ] /Rect [ 538.5798 743.4508 555.2598 755.4508 ] /Subtype /Link /Type /Annot >> endobj 481 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 258.5008 0 ] /Rect [ 140.0157 724.7008 217.8257 736.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 724.7008 217.8257 736.7008 ] /Subtype /Link /Type /Annot >> endobj 482 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 907 0 R /XYZ 40.01575 258.5008 0 ] /Rect [ 538.5798 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 725.4508 555.2598 737.4508 ] /Subtype /Link /Type /Annot >> endobj 483 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 909 0 R /XYZ 40.01575 555.7008 0 ] /Rect [ 140.0157 706.7008 256.1757 718.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 375.1008 0 ] /Rect [ 140.0157 706.7008 256.1757 718.7008 ] /Subtype /Link /Type /Annot >> endobj 484 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 909 0 R /XYZ 40.01575 555.7008 0 ] /Rect [ 538.5798 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 375.1008 0 ] /Rect [ 538.5798 707.4508 555.2598 719.4508 ] /Subtype /Link /Type /Annot >> endobj 485 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 909 0 R /XYZ 40.01575 239.1008 0 ] /Rect [ 140.0157 688.7008 205.5957 700.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 140.0157 688.7008 205.5957 700.7008 ] /Subtype /Link /Type /Annot >> endobj 486 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 909 0 R /XYZ 40.01575 239.1008 0 ] /Rect [ 538.5798 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 689.4508 555.2598 701.4508 ] /Subtype /Link /Type /Annot >> endobj 487 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 911 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 80.01575 670.7008 198.9357 682.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 579.1008 0 ] /Rect [ 80.01575 670.7008 198.9357 682.7008 ] /Subtype /Link /Type /Annot >> endobj 488 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 911 0 R /XYZ 40.01575 775.7008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 906 0 R /XYZ 40.01575 579.1008 0 ] /Rect [ 538.5798 671.4508 555.2598 683.4508 ] /Subtype /Link /Type /Annot >> endobj 489 0 obj << /Annots [ 477 0 R 478 0 R 479 0 R 480 0 R 481 0 R 482 0 R 483 0 R 484 0 R 485 0 R 486 0 R - 487 0 R 488 0 R ] /Contents 1204 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 487 0 R 488 0 R ] /Contents 1201 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2599,7 +2599,7 @@ endobj endobj 499 0 obj << -/Annots [ 492 0 R 495 0 R 498 0 R ] /Contents 1205 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 492 0 R 495 0 R 498 0 R ] /Contents 1202 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] /XObject << /FormXob.1a10b9b0ce440b29926bd8bfcaf3cbfe 493 0 R /FormXob.4548a30dc6585b7561ff04ed4014ac68 496 0 R >> @@ -2690,7 +2690,7 @@ endobj 512 0 obj << /Annots [ 500 0 R 501 0 R 502 0 R 503 0 R 504 0 R 505 0 R 506 0 R 507 0 R 508 0 R 509 0 R - 510 0 R 511 0 R ] /Contents 1206 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << + 510 0 R 511 0 R ] /Contents 1203 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2749,7 +2749,7 @@ endobj endobj 520 0 obj << -/Annots [ 513 0 R 514 0 R 515 0 R 516 0 R 517 0 R 518 0 R 519 0 R ] /Contents 1207 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 513 0 R 514 0 R 515 0 R 516 0 R 517 0 R 518 0 R 519 0 R ] /Contents 1204 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2766,7 +2766,7 @@ endobj endobj 522 0 obj << -/Annots [ 521 0 R ] /Contents 1208 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 521 0 R ] /Contents 1205 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2846,7 +2846,7 @@ endobj endobj 533 0 obj << -/Annots [ 523 0 R 524 0 R 525 0 R 526 0 R 527 0 R 528 0 R 529 0 R 530 0 R 531 0 R 532 0 R ] /Contents 1209 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 523 0 R 524 0 R 525 0 R 526 0 R 527 0 R 528 0 R 529 0 R 530 0 R 531 0 R 532 0 R ] /Contents 1206 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2870,7 +2870,7 @@ endobj endobj 536 0 obj << -/Annots [ 534 0 R 535 0 R ] /Contents 1210 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 534 0 R 535 0 R ] /Contents 1207 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2906,7 +2906,7 @@ endobj endobj 541 0 obj << -/Annots [ 537 0 R 538 0 R 539 0 R 540 0 R ] /Contents 1211 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 537 0 R 538 0 R 539 0 R 540 0 R ] /Contents 1208 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2942,7 +2942,7 @@ endobj endobj 546 0 obj << -/Annots [ 542 0 R 543 0 R 544 0 R 545 0 R ] /Contents 1212 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 542 0 R 543 0 R 544 0 R 545 0 R ] /Contents 1209 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2957,7 +2957,7 @@ endobj endobj 548 0 obj << -/Annots [ 547 0 R ] /Contents 1213 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 547 0 R ] /Contents 1210 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2967,7 +2967,7 @@ endobj endobj 549 0 obj << -/Contents 1214 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1211 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2977,7 +2977,7 @@ endobj endobj 550 0 obj << -/Contents 1215 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1212 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2987,7 +2987,7 @@ endobj endobj 551 0 obj << -/Contents 1216 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1213 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -2997,7 +2997,7 @@ endobj endobj 552 0 obj << -/Contents 1217 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1214 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3007,7 +3007,7 @@ endobj endobj 553 0 obj << -/Contents 1218 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1215 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3025,7 +3025,7 @@ Gb",k#C$qO)ojmoMMNHY:]U_f&[@/Q<*X<2><+S+IUk-j_&No\Or*P2:O<^%^B1i-T,"Ek,F- endobj 555 0 obj << -/Contents 1219 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1216 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] /XObject << /FormXob.3119446b432c1228375b8b28cf940123 554 0 R >> @@ -3037,7 +3037,7 @@ endobj endobj 556 0 obj << -/Contents 1220 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1217 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3054,7 +3054,7 @@ endobj endobj 558 0 obj << -/Annots [ 557 0 R ] /Contents 1221 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 557 0 R ] /Contents 1218 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3085,7 +3085,7 @@ endobj endobj 562 0 obj << -/Annots [ 559 0 R 560 0 R 561 0 R ] /Contents 1222 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 559 0 R 560 0 R 561 0 R ] /Contents 1219 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3123,7 +3123,7 @@ endobj endobj 567 0 obj << -/Annots [ 563 0 R 564 0 R 565 0 R 566 0 R ] /Contents 1223 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 563 0 R 564 0 R 565 0 R 566 0 R ] /Contents 1220 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3147,7 +3147,7 @@ endobj endobj 570 0 obj << -/Annots [ 568 0 R 569 0 R ] /Contents 1224 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 568 0 R 569 0 R ] /Contents 1221 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3178,7 +3178,7 @@ endobj endobj 574 0 obj << -/Annots [ 571 0 R 572 0 R 573 0 R ] /Contents 1225 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 571 0 R 572 0 R 573 0 R ] /Contents 1222 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3230,7 +3230,7 @@ endobj endobj 581 0 obj << -/Annots [ 575 0 R 576 0 R 577 0 R 578 0 R 579 0 R 580 0 R ] /Contents 1226 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 575 0 R 576 0 R 577 0 R 578 0 R 579 0 R 580 0 R ] /Contents 1223 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3268,7 +3268,7 @@ endobj endobj 586 0 obj << -/Annots [ 582 0 R 583 0 R 584 0 R 585 0 R ] /Contents 1227 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 582 0 R 583 0 R 584 0 R 585 0 R ] /Contents 1224 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3299,7 +3299,7 @@ endobj endobj 590 0 obj << -/Annots [ 587 0 R 588 0 R 589 0 R ] /Contents 1228 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 587 0 R 588 0 R 589 0 R ] /Contents 1225 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3314,7 +3314,7 @@ endobj endobj 592 0 obj << -/Contents 1229 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1226 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3324,7 +3324,7 @@ endobj endobj 593 0 obj << -/Contents 1230 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1227 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3334,7 +3334,7 @@ endobj endobj 594 0 obj << -/Contents 1231 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1228 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3344,7 +3344,7 @@ endobj endobj 595 0 obj << -/Contents 1232 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1229 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3354,7 +3354,7 @@ endobj endobj 596 0 obj << -/Contents 1233 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1230 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3364,7 +3364,7 @@ endobj endobj 597 0 obj << -/Contents 1234 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1231 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3374,7 +3374,7 @@ endobj endobj 598 0 obj << -/Contents 1235 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1232 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3384,7 +3384,7 @@ endobj endobj 599 0 obj << -/Contents 1236 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1233 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3394,7 +3394,7 @@ endobj endobj 600 0 obj << -/Contents 1237 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1234 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3404,7 +3404,7 @@ endobj endobj 601 0 obj << -/Contents 1238 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1235 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3414,7 +3414,7 @@ endobj endobj 602 0 obj << -/Contents 1239 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1236 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3424,7 +3424,7 @@ endobj endobj 603 0 obj << -/Contents 1240 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1237 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3434,7 +3434,7 @@ endobj endobj 604 0 obj << -/Contents 1241 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1238 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3444,7 +3444,7 @@ endobj endobj 605 0 obj << -/Contents 1242 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1239 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3454,7 +3454,7 @@ endobj endobj 606 0 obj << -/Contents 1243 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1240 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3464,7 +3464,7 @@ endobj endobj 607 0 obj << -/Contents 1244 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1241 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3474,12 +3474,12 @@ endobj endobj 608 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 114.5008 251.3657 126.5008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 114.5008 251.3657 126.5008 ] /Subtype /Link /Type /Annot >> endobj 609 0 obj << -/Annots [ 608 0 R ] /Contents 1245 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 608 0 R ] /Contents 1242 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3489,32 +3489,37 @@ endobj endobj 610 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 561.7008 0 ] /Rect [ 83.36575 523.7008 287.3657 535.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 561.7008 0 ] /Rect [ 83.36575 523.7008 287.3657 535.7008 ] /Subtype /Link /Type /Annot >> endobj 611 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 290.1008 0 ] /Rect [ 83.36575 240.1008 371.3657 252.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 326.1008 0 ] /Rect [ 83.36575 276.1008 371.3657 288.1008 ] /Subtype /Link /Type /Annot >> endobj 612 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 230.1008 0 ] /Rect [ 83.36575 192.1008 413.3657 204.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 266.1008 0 ] /Rect [ 83.36575 228.1008 413.3657 240.1008 ] /Subtype /Link /Type /Annot >> endobj 613 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 182.1008 0 ] /Rect [ 83.36575 144.1008 365.3657 156.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 218.1008 0 ] /Rect [ 83.36575 180.1008 365.3657 192.1008 ] /Subtype /Link /Type /Annot >> endobj 614 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 134.1008 0 ] /Rect [ 83.36575 96.10079 425.3657 108.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 170.1008 0 ] /Rect [ 83.36575 132.1008 425.3657 144.1008 ] /Subtype /Link /Type /Annot >> endobj 615 0 obj << -/Annots [ 610 0 R 611 0 R 612 0 R 613 0 R 614 0 R ] /Contents 1246 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 122.1008 0 ] /Rect [ 83.36575 96.10079 473.3657 108.1008 ] /Subtype /Link /Type /Annot +>> +endobj +616 0 obj +<< +/Annots [ 610 0 R 611 0 R 612 0 R 613 0 R 614 0 R 615 0 R ] /Contents 1243 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3522,100 +3527,95 @@ endobj >> /Type /Page >> endobj -616 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 86.10079 0 ] /Rect [ 83.36575 763.7008 473.3657 775.7008 ] /Subtype /Link /Type /Annot ->> -endobj 617 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 753.7008 0 ] /Rect [ 83.36575 727.7008 359.3657 739.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 86.10079 0 ] /Rect [ 83.36575 763.7008 359.3657 775.7008 ] /Subtype /Link /Type /Annot >> endobj 618 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 717.7008 0 ] /Rect [ 83.36575 691.7008 365.3657 703.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 753.7008 0 ] /Rect [ 83.36575 727.7008 365.3657 739.7008 ] /Subtype /Link /Type /Annot >> endobj 619 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 681.7008 0 ] /Rect [ 83.36575 655.7008 455.3657 667.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 717.7008 0 ] /Rect [ 83.36575 691.7008 455.3657 703.7008 ] /Subtype /Link /Type /Annot >> endobj 620 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 645.7008 0 ] /Rect [ 83.36575 619.7008 377.3657 631.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 681.7008 0 ] /Rect [ 83.36575 655.7008 377.3657 667.7008 ] /Subtype /Link /Type /Annot >> endobj 621 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 609.7008 0 ] /Rect [ 83.36575 583.7008 389.3657 595.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 645.7008 0 ] /Rect [ 83.36575 619.7008 389.3657 631.7008 ] /Subtype /Link /Type /Annot >> endobj 622 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 573.7008 0 ] /Rect [ 83.36575 547.7008 383.3657 559.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 609.7008 0 ] /Rect [ 83.36575 583.7008 383.3657 595.7008 ] /Subtype /Link /Type /Annot >> endobj 623 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 537.7008 0 ] /Rect [ 83.36575 499.7008 479.3657 511.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 573.7008 0 ] /Rect [ 83.36575 535.7008 479.3657 547.7008 ] /Subtype /Link /Type /Annot >> endobj 624 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 489.7008 0 ] /Rect [ 83.36575 463.7008 413.3657 475.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 525.7008 0 ] /Rect [ 83.36575 499.7008 413.3657 511.7008 ] /Subtype /Link /Type /Annot >> endobj 625 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 453.7008 0 ] /Rect [ 83.36575 415.7008 419.3657 427.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 489.7008 0 ] /Rect [ 83.36575 451.7008 419.3657 463.7008 ] /Subtype /Link /Type /Annot >> endobj 626 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 405.7008 0 ] /Rect [ 83.36575 379.7008 425.3657 391.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 441.7008 0 ] /Rect [ 83.36575 415.7008 425.3657 427.7008 ] /Subtype /Link /Type /Annot >> endobj 627 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 369.7008 0 ] /Rect [ 83.36575 343.7008 347.3657 355.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 405.7008 0 ] /Rect [ 83.36575 379.7008 347.3657 391.7008 ] /Subtype /Link /Type /Annot >> endobj 628 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 333.7008 0 ] /Rect [ 83.36575 307.7008 347.3657 319.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 369.7008 0 ] /Rect [ 83.36575 343.7008 347.3657 355.7008 ] /Subtype /Link /Type /Annot >> endobj 629 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 297.7008 0 ] /Rect [ 83.36575 259.7008 347.3657 271.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 333.7008 0 ] /Rect [ 83.36575 295.7008 347.3657 307.7008 ] /Subtype /Link /Type /Annot >> endobj 630 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 249.7008 0 ] /Rect [ 83.36575 223.7008 389.3657 235.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 285.7008 0 ] /Rect [ 83.36575 259.7008 389.3657 271.7008 ] /Subtype /Link /Type /Annot >> endobj 631 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 213.7008 0 ] /Rect [ 83.36575 187.7008 347.3657 199.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 249.7008 0 ] /Rect [ 83.36575 223.7008 347.3657 235.7008 ] /Subtype /Link /Type /Annot >> endobj 632 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 177.7008 0 ] /Rect [ 83.36575 139.7008 347.3657 151.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 634 0 R /XYZ 40.01575 213.7008 0 ] /Rect [ 83.36575 175.7008 347.3657 187.7008 ] /Subtype /Link /Type /Annot >> endobj 633 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 103.7008 287.3657 115.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 139.7008 287.3657 151.7008 ] /Subtype /Link /Type /Annot >> endobj 634 0 obj << -/Annots [ 616 0 R 617 0 R 618 0 R 619 0 R 620 0 R 621 0 R 622 0 R 623 0 R 624 0 R 625 0 R - 626 0 R 627 0 R 628 0 R 629 0 R 630 0 R 631 0 R 632 0 R 633 0 R ] /Contents 1247 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 617 0 R 618 0 R 619 0 R 620 0 R 621 0 R 622 0 R 623 0 R 624 0 R 625 0 R 626 0 R + 627 0 R 628 0 R 629 0 R 630 0 R 631 0 R 632 0 R 633 0 R ] /Contents 1244 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3625,67 +3625,42 @@ endobj endobj 635 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 727.7008 287.3657 739.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 763.7008 287.3657 775.7008 ] /Subtype /Link /Type /Annot >> endobj 636 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 571.7008 287.3657 583.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 607.7008 287.3657 619.7008 ] /Subtype /Link /Type /Annot >> endobj 637 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 511.7008 287.3657 523.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 547.7008 287.3657 559.7008 ] /Subtype /Link /Type /Annot >> endobj 638 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 451.7008 287.3657 463.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 487.7008 287.3657 499.7008 ] /Subtype /Link /Type /Annot >> endobj 639 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 319.7008 287.3657 331.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 355.7008 287.3657 367.7008 ] /Subtype /Link /Type /Annot >> endobj 640 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 187.7008 287.3657 199.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 223.7008 287.3657 235.7008 ] /Subtype /Link /Type /Annot >> endobj 641 0 obj << -/Annots [ 635 0 R 636 0 R 637 0 R 638 0 R 639 0 R 640 0 R ] /Contents 1248 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 79.70079 287.3657 91.70079 ] /Subtype /Link /Type /Annot >> endobj 642 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 751.7008 287.3657 763.7008 ] /Subtype /Link /Type /Annot ->> -endobj -643 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 475.7008 287.3657 487.7008 ] /Subtype /Link /Type /Annot ->> -endobj -644 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 367.7008 287.3657 379.7008 ] /Subtype /Link /Type /Annot ->> -endobj -645 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 91.70079 287.3657 103.7008 ] /Subtype /Link /Type /Annot ->> -endobj -646 0 obj -<< -/Annots [ 642 0 R 643 0 R 644 0 R 645 0 R ] /Contents 1249 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 635 0 R 636 0 R 637 0 R 638 0 R 639 0 R 640 0 R 641 0 R ] /Contents 1245 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3693,39 +3668,64 @@ endobj >> /Type /Page >> endobj +643 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 511.7008 287.3657 523.7008 ] /Subtype /Link /Type /Annot +>> +endobj +644 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 403.7008 287.3657 415.7008 ] /Subtype /Link /Type /Annot +>> +endobj +645 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 127.7008 287.3657 139.7008 ] /Subtype /Link /Type /Annot +>> +endobj +646 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 67.70079 287.3657 79.70079 ] /Subtype /Link /Type /Annot +>> +endobj 647 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 751.7008 287.3657 763.7008 ] /Subtype /Link /Type /Annot +/Annots [ 643 0 R 644 0 R 645 0 R 646 0 R ] /Contents 1246 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 648 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 691.7008 287.3657 703.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 727.7008 287.3657 739.7008 ] /Subtype /Link /Type /Annot >> endobj 649 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 559.7008 287.3657 571.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 595.7008 287.3657 607.7008 ] /Subtype /Link /Type /Annot >> endobj 650 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 475.7008 287.3657 487.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 511.7008 287.3657 523.7008 ] /Subtype /Link /Type /Annot >> endobj 651 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 615 0 R /XYZ 40.01575 350.1008 0 ] /Rect [ 83.36575 343.7008 287.3657 355.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 616 0 R /XYZ 40.01575 386.1008 0 ] /Rect [ 83.36575 379.7008 287.3657 391.7008 ] /Subtype /Link /Type /Annot >> endobj 652 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 123.1008 251.3657 135.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 159.1008 251.3657 171.1008 ] /Subtype /Link /Type /Annot >> endobj 653 0 obj << -/Annots [ 647 0 R 648 0 R 649 0 R 650 0 R 651 0 R 652 0 R ] /Contents 1250 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 648 0 R 649 0 R 650 0 R 651 0 R 652 0 R ] /Contents 1247 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3735,12 +3735,12 @@ endobj endobj 654 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 492.1008 251.3657 504.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 588.1008 251.3657 600.1008 ] /Subtype /Link /Type /Annot >> endobj 655 0 obj << -/Annots [ 654 0 R ] /Contents 1251 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 654 0 R ] /Contents 1248 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3750,17 +3750,17 @@ endobj endobj 656 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 588.7008 251.3657 600.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 720.3008 251.3657 732.3008 ] /Subtype /Link /Type /Annot >> endobj 657 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 305.9008 251.3657 317.9008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 473.5008 251.3657 485.5008 ] /Subtype /Link /Type /Annot >> endobj 658 0 obj << -/Annots [ 656 0 R 657 0 R ] /Contents 1252 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 656 0 R 657 0 R ] /Contents 1249 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3770,27 +3770,17 @@ endobj endobj 659 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 497.1008 251.3657 509.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 676.7008 251.3657 688.7008 ] /Subtype /Link /Type /Annot >> endobj 660 0 obj << -/Annots [ 659 0 R ] /Contents 1253 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 96.10079 251.3657 108.1008 ] /Subtype /Link /Type /Annot >> endobj 661 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 579.1008 251.3657 591.1008 ] /Subtype /Link /Type /Annot ->> -endobj -662 0 obj -<< -/Annots [ 661 0 R ] /Contents 1254 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 659 0 R 660 0 R ] /Contents 1250 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3798,19 +3788,29 @@ endobj >> /Type /Page >> endobj +662 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 96.90079 251.3657 108.9008 ] /Subtype /Link /Type /Annot +>> +endobj 663 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 535.9008 251.3657 547.9008 ] /Subtype /Link /Type /Annot +/Annots [ 662 0 R ] /Contents 1251 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 664 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 168.3008 251.3657 180.3008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 516.1008 251.3657 528.1008 ] /Subtype /Link /Type /Annot >> endobj 665 0 obj << -/Annots [ 663 0 R 664 0 R ] /Contents 1255 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 664 0 R ] /Contents 1252 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3820,12 +3820,12 @@ endobj endobj 666 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 350.3008 251.3657 362.3008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 701.1008 251.3657 713.1008 ] /Subtype /Link /Type /Annot >> endobj 667 0 obj << -/Annots [ 666 0 R ] /Contents 1256 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 666 0 R ] /Contents 1253 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3837,12 +3837,12 @@ endobj << /A << /S /URI /Type /Action /URI (http://www.intel.com/content/dam/doc/datasheet/atom-d2000-n2000-vol-2-datasheet.pdf) ->> /Border [ 0 0 0 ] /Rect [ 63.01575 405.1008 452.0957 417.1008 ] /Subtype /Link /Type /Annot +>> /Border [ 0 0 0 ] /Rect [ 63.01575 748.7008 452.0957 760.7008 ] /Subtype /Link /Type /Annot >> endobj 669 0 obj << -/Annots [ 668 0 R ] /Contents 1257 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 668 0 R ] /Contents 1254 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3852,12 +3852,12 @@ endobj endobj 670 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 247.7008 251.3657 259.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 595.7008 251.3657 607.7008 ] /Subtype /Link /Type /Annot >> endobj 671 0 obj << -/Annots [ 670 0 R ] /Contents 1258 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 670 0 R ] /Contents 1255 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3867,7 +3867,261 @@ endobj endobj 672 0 obj << -/Contents 1259 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Border [ 0 0 0 ] /Contents () /Dest [ 680 0 R /XYZ 40.01575 597.7008 0 ] /Rect [ 83.36575 528.1008 245.3657 540.1008 ] /Subtype /Link /Type /Annot +>> +endobj +673 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 554.1008 0 ] /Rect [ 83.36575 228.1008 317.3657 240.1008 ] /Subtype /Link /Type /Annot +>> +endobj +674 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 554.1008 0 ] /Rect [ 83.36575 72.10079 317.3657 84.10079 ] /Subtype /Link /Type /Annot +>> +endobj +675 0 obj +<< +/Annots [ 672 0 R 673 0 R 674 0 R ] /Contents 1256 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +676 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 98.10079 0 ] /Rect [ 83.36575 679.7008 311.3657 691.7008 ] /Subtype /Link /Type /Annot +>> +endobj +677 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 680 0 R /XYZ 40.01575 249.7008 0 ] /Rect [ 83.36575 571.7008 407.3657 583.7008 ] /Subtype /Link /Type /Annot +>> +endobj +678 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 680 0 R /XYZ 40.01575 129.7008 0 ] /Rect [ 50.01575 559.7008 242.0157 571.7008 ] /Subtype /Link /Type /Annot +>> +endobj +679 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 680 0 R /XYZ 40.01575 309.7008 0 ] /Rect [ 83.36575 223.7008 329.3657 235.7008 ] /Subtype /Link /Type /Annot +>> +endobj +680 0 obj +<< +/Annots [ 676 0 R 677 0 R 678 0 R 679 0 R ] /Contents 1257 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +681 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 254.1008 0 ] /Rect [ 83.36575 583.7008 329.3657 595.7008 ] /Subtype /Link /Type /Annot +>> +endobj +682 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 684 0 R /XYZ 40.01575 235.5008 0 ] /Rect [ 83.36575 197.5008 269.3657 209.5008 ] /Subtype /Link /Type /Annot +>> +endobj +683 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 684 0 R /XYZ 40.01575 187.5008 0 ] /Rect [ 83.36575 161.5008 269.3657 173.5008 ] /Subtype /Link /Type /Annot +>> +endobj +684 0 obj +<< +/Annots [ 681 0 R 682 0 R 683 0 R ] /Contents 1258 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +685 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 687 0 R /XYZ 40.01575 405.7008 0 ] /Rect [ 83.36575 379.7008 245.3657 391.7008 ] /Subtype /Link /Type /Annot +>> +endobj +686 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://github.com/pciutils/pciids) +>> /Border [ 0 0 0 ] /Rect [ 48.01575 120.0508 188.6257 132.0508 ] /Subtype /Link /Type /Annot +>> +endobj +687 0 obj +<< +/Annots [ 685 0 R 686 0 R ] /Contents 1259 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +688 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 647.9008 251.3657 659.9008 ] /Subtype /Link /Type /Annot +>> +endobj +689 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 244.3008 251.3657 256.3008 ] /Subtype /Link /Type /Annot +>> +endobj +690 0 obj +<< +/Annots [ 688 0 R 689 0 R ] /Contents 1260 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +691 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 83.36575 727.7008 329.3657 739.7008 ] /Subtype /Link /Type /Annot +>> +endobj +692 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 717.7008 0 ] /Rect [ 83.36575 679.7008 329.3657 691.7008 ] /Subtype /Link /Type /Annot +>> +endobj +693 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 695 0 R /XYZ 40.01575 621.7008 0 ] /Rect [ 83.36575 595.7008 317.3657 607.7008 ] /Subtype /Link /Type /Annot +>> +endobj +694 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 444.1008 251.3657 456.1008 ] /Subtype /Link /Type /Annot +>> +endobj +695 0 obj +<< +/Annots [ 691 0 R 692 0 R 693 0 R 694 0 R ] /Contents 1261 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +696 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 763.7008 307.9257 775.7008 ] /Subtype /Link /Type /Annot +>> +endobj +697 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 751.7008 324.6057 763.7008 ] /Subtype /Link /Type /Annot +>> +endobj +698 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 739.7008 324.6057 751.7008 ] /Subtype /Link /Type /Annot +>> +endobj +699 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 727.7008 331.2757 739.7008 ] /Subtype /Link /Type /Annot +>> +endobj +700 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/184) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 715.7008 291.7457 727.7008 ] /Subtype /Link /Type /Annot +>> +endobj +701 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/153) +>> /Border [ 0 0 0 ] /Rect [ 294.5257 715.7008 546.2557 727.7008 ] /Subtype /Link /Type /Annot +>> +endobj +702 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/101) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 703.7008 291.7457 715.7008 ] /Subtype /Link /Type /Annot +>> +endobj +703 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://en.wikipedia.org/wiki/Serial_presence_detect) +>> /Border [ 0 0 0 ] /Rect [ 294.5257 703.7008 519.0657 715.7008 ] /Subtype /Link /Type /Annot +>> +endobj +704 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 393.7008 0 ] /Rect [ 83.36575 367.7008 221.3657 379.7008 ] /Subtype /Link /Type /Annot +>> +endobj +705 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 357.7008 0 ] /Rect [ 83.36575 331.7008 227.3657 343.7008 ] /Subtype /Link /Type /Annot +>> +endobj +706 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 321.7008 0 ] /Rect [ 83.36575 283.7008 227.3657 295.7008 ] /Subtype /Link /Type /Annot +>> +endobj +707 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 708 0 R /XYZ 40.01575 273.7008 0 ] /Rect [ 83.36575 235.7008 227.3657 247.7008 ] /Subtype /Link /Type /Annot +>> +endobj +708 0 obj +<< +/Annots [ 696 0 R 697 0 R 698 0 R 699 0 R 700 0 R 701 0 R 702 0 R 703 0 R 704 0 R 705 0 R + 706 0 R 707 0 R ] /Contents 1262 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +709 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 529.1008 251.3657 541.1008 ] /Subtype /Link /Type /Annot +>> +endobj +710 0 obj +<< +/Annots [ 709 0 R ] /Contents 1263 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj +711 0 obj +<< +/Contents 1264 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -3875,262 +4129,9 @@ endobj /Type /Page >> endobj -673 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 679 0 R /XYZ 40.01575 117.7008 0 ] /Rect [ 83.36575 763.7008 245.3657 775.7008 ] /Subtype /Link /Type /Annot ->> -endobj -674 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 86.30079 0 ] /Rect [ 83.36575 463.7008 317.3657 475.7008 ] /Subtype /Link /Type /Annot ->> -endobj -675 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 672 0 R /XYZ 40.01575 86.30079 0 ] /Rect [ 83.36575 307.7008 317.3657 319.7008 ] /Subtype /Link /Type /Annot ->> -endobj -676 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 679 0 R /XYZ 40.01575 333.7008 0 ] /Rect [ 83.36575 199.7008 311.3657 211.7008 ] /Subtype /Link /Type /Annot ->> -endobj -677 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 682 0 R /XYZ 40.01575 477.7008 0 ] /Rect [ 83.36575 91.70079 407.3657 103.7008 ] /Subtype /Link /Type /Annot ->> -endobj -678 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 682 0 R /XYZ 40.01575 357.7008 0 ] /Rect [ 50.01575 79.70079 242.0157 91.70079 ] /Subtype /Link /Type /Annot ->> -endobj -679 0 obj -<< -/Annots [ 673 0 R 674 0 R 675 0 R 676 0 R 677 0 R 678 0 R ] /Contents 1260 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -680 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 682 0 R /XYZ 40.01575 537.7008 0 ] /Rect [ 83.36575 451.7008 329.3657 463.7008 ] /Subtype /Link /Type /Annot ->> -endobj -681 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 679 0 R /XYZ 40.01575 489.7008 0 ] /Rect [ 83.36575 103.7008 329.3657 115.7008 ] /Subtype /Link /Type /Annot ->> -endobj -682 0 obj -<< -/Annots [ 680 0 R 681 0 R ] /Contents 1261 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -683 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 685 0 R /XYZ 40.01575 463.5008 0 ] /Rect [ 83.36575 425.5008 269.3657 437.5008 ] /Subtype /Link /Type /Annot ->> -endobj -684 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 685 0 R /XYZ 40.01575 415.5008 0 ] /Rect [ 83.36575 389.5008 269.3657 401.5008 ] /Subtype /Link /Type /Annot ->> -endobj -685 0 obj -<< -/Annots [ 683 0 R 684 0 R ] /Contents 1262 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -686 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 689 0 R /XYZ 40.01575 549.7008 0 ] /Rect [ 83.36575 523.7008 245.3657 535.7008 ] /Subtype /Link /Type /Annot ->> -endobj -687 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://github.com/pciutils/pciids) ->> /Border [ 0 0 0 ] /Rect [ 48.01575 264.0508 188.6257 276.0508 ] /Subtype /Link /Type /Annot ->> -endobj -688 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 81.50079 251.3657 93.50079 ] /Subtype /Link /Type /Annot ->> -endobj -689 0 obj -<< -/Annots [ 686 0 R 687 0 R 688 0 R ] /Contents 1263 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -690 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 312.1008 251.3657 324.1008 ] /Subtype /Link /Type /Annot ->> -endobj -691 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 692 0 R /XYZ 40.01575 146.1008 0 ] /Rect [ 83.36575 96.10079 329.3657 108.1008 ] /Subtype /Link /Type /Annot ->> -endobj -692 0 obj -<< -/Annots [ 690 0 R 691 0 R ] /Contents 1264 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -693 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 83.36575 739.7008 329.3657 751.7008 ] /Subtype /Link /Type /Annot ->> -endobj -694 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 700 0 R /XYZ 40.01575 681.7008 0 ] /Rect [ 83.36575 655.7008 317.3657 667.7008 ] /Subtype /Link /Type /Annot ->> -endobj -695 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 504.1008 251.3657 516.1008 ] /Subtype /Link /Type /Annot ->> -endobj -696 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 112.5008 307.9257 124.5008 ] /Subtype /Link /Type /Annot ->> -endobj -697 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 100.5008 324.6057 112.5008 ] /Subtype /Link /Type /Annot ->> -endobj -698 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 88.50079 324.6057 100.5008 ] /Subtype /Link /Type /Annot ->> -endobj -699 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 76.50079 331.2757 88.50079 ] /Subtype /Link /Type /Annot ->> -endobj -700 0 obj -<< -/Annots [ 693 0 R 694 0 R 695 0 R 696 0 R 697 0 R 698 0 R 699 0 R ] /Contents 1265 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -701 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/184) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 763.7008 291.7457 775.7008 ] /Subtype /Link /Type /Annot ->> -endobj -702 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/153) ->> /Border [ 0 0 0 ] /Rect [ 294.5257 763.7008 546.2557 775.7008 ] /Subtype /Link /Type /Annot ->> -endobj -703 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://www.simmtester.com/News/PublicationArticle/101) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 751.7008 291.7457 763.7008 ] /Subtype /Link /Type /Annot ->> -endobj -704 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://en.wikipedia.org/wiki/Serial_presence_detect) ->> /Border [ 0 0 0 ] /Rect [ 294.5257 751.7008 519.0657 763.7008 ] /Subtype /Link /Type /Annot ->> -endobj -705 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 441.7008 0 ] /Rect [ 83.36575 415.7008 221.3657 427.7008 ] /Subtype /Link /Type /Annot ->> -endobj -706 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 405.7008 0 ] /Rect [ 83.36575 379.7008 227.3657 391.7008 ] /Subtype /Link /Type /Annot ->> -endobj -707 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 369.7008 0 ] /Rect [ 83.36575 331.7008 227.3657 343.7008 ] /Subtype /Link /Type /Annot ->> -endobj -708 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 709 0 R /XYZ 40.01575 321.7008 0 ] /Rect [ 83.36575 283.7008 227.3657 295.7008 ] /Subtype /Link /Type /Annot ->> -endobj -709 0 obj -<< -/Annots [ 701 0 R 702 0 R 703 0 R 704 0 R 705 0 R 706 0 R 707 0 R 708 0 R ] /Contents 1266 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -710 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 598.9008 251.3657 610.9008 ] /Subtype /Link /Type /Annot ->> -endobj -711 0 obj -<< -/Annots [ 710 0 R ] /Contents 1267 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj 712 0 obj << -/Contents 1268 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1265 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4140,34 +4141,24 @@ endobj endobj 713 0 obj << -/Contents 1269 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page ->> -endobj -714 0 obj -<< /A << /S /URI /Type /Action /URI (https://trustedcomputinggroup.org) >> /Border [ 0 0 0 ] /Rect [ 40.01575 764.4508 189.5357 776.4508 ] /Subtype /Link /Type /Annot >> endobj +714 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 727.7008 251.3657 739.7008 ] /Subtype /Link /Type /Annot +>> +endobj 715 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 727.7008 251.3657 739.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 716 0 R /XYZ 40.01575 417.7008 0 ] /Rect [ 83.36575 391.7008 293.3657 403.7008 ] /Subtype /Link /Type /Annot >> endobj 716 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 717 0 R /XYZ 40.01575 417.7008 0 ] /Rect [ 83.36575 391.7008 293.3657 403.7008 ] /Subtype /Link /Type /Annot ->> -endobj -717 0 obj -<< -/Annots [ 714 0 R 715 0 R 716 0 R ] /Contents 1270 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 713 0 R 714 0 R 715 0 R ] /Contents 1266 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4175,89 +4166,89 @@ endobj >> /Type /Page >> endobj -718 0 obj +717 0 obj << /A << /S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 588.1008 281.8057 600.1008 ] /Subtype /Link /Type /Annot +>> /Border [ 0 0 0 ] /Rect [ 40.01575 624.1008 281.8057 636.1008 ] /Subtype /Link /Type /Annot +>> +endobj +718 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 594.1008 486.3357 606.1008 ] /Subtype /Link /Type /Annot >> endobj 719 0 obj << /A << -/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 558.1008 486.3357 570.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/EFI-Protocol-Specification-rev13-160330final.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 564.1008 497.4457 576.1008 ] /Subtype /Link /Type /Annot >> endobj 720 0 obj << /A << -/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/EFI-Protocol-Specification-rev13-160330final.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 528.1008 497.4457 540.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/PC-ClientSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf) +>> /Border [ 0 0 0 ] /Rect [ 283.9557 546.1008 554.6257 558.1008 ] /Subtype /Link /Type /Annot >> endobj 721 0 obj << /A << /S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/PC-ClientSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf) ->> /Border [ 0 0 0 ] /Rect [ 283.9557 510.1008 554.6257 522.1008 ] /Subtype /Link /Type /Annot +>> /Border [ 0 0 0 ] /Rect [ 40.01575 534.1008 314.0157 546.1008 ] /Subtype /Link /Type /Annot >> endobj 722 0 obj << -/A << -/S /URI /Type /Action /URI (https://trustedcomputinggroup.org/wp-content/uploads/PC-ClientSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 498.1008 314.0157 510.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 380.1008 0 ] /Rect [ 83.36575 498.1008 299.3657 510.1008 ] /Subtype /Link /Type /Annot >> endobj 723 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 344.1008 0 ] /Rect [ 83.36575 462.1008 299.3657 474.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 724 0 R /XYZ 40.01575 380.1008 0 ] /Rect [ 83.36575 390.1008 299.3657 402.1008 ] /Subtype /Link /Type /Annot >> endobj 724 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 725 0 R /XYZ 40.01575 344.1008 0 ] /Rect [ 83.36575 354.1008 299.3657 366.1008 ] /Subtype /Link /Type /Annot +/Annots [ 717 0 R 718 0 R 719 0 R 720 0 R 721 0 R 722 0 R 723 0 R ] /Contents 1267 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 725 0 obj << -/Annots [ 718 0 R 719 0 R 720 0 R 721 0 R 722 0 R 723 0 R 724 0 R ] /Contents 1271 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 727 0 R /XYZ 40.01575 580.7008 0 ] /Rect [ 83.36575 542.7008 293.3657 554.7008 ] /Subtype /Link /Type /Annot >> endobj 726 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 728 0 R /XYZ 40.01575 561.5008 0 ] /Rect [ 83.36575 523.5008 293.3657 535.5008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 391.1008 251.3657 403.1008 ] /Subtype /Link /Type /Annot >> endobj 727 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 371.9008 251.3657 383.9008 ] /Subtype /Link /Type /Annot +/Annots [ 725 0 R 726 0 R ] /Contents 1268 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 728 0 obj << -/Annots [ 726 0 R 727 0 R ] /Contents 1272 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 729 0 R /XYZ 40.01575 278.1008 0 ] /Rect [ 83.36575 168.1008 365.3657 180.1008 ] /Subtype /Link /Type /Annot >> endobj 729 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 730 0 R /XYZ 40.01575 254.1008 0 ] /Rect [ 83.36575 144.1008 365.3657 156.1008 ] /Subtype /Link /Type /Annot ->> -endobj -730 0 obj -<< -/Annots [ 729 0 R ] /Contents 1273 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 728 0 R ] /Contents 1269 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4265,34 +4256,39 @@ endobj >> /Type /Page >> endobj +730 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 729 0 R /XYZ 40.01575 122.1008 0 ] /Rect [ 83.36575 763.7008 359.3657 775.7008 ] /Subtype /Link /Type /Annot +>> +endobj 731 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 730 0 R /XYZ 40.01575 98.10079 0 ] /Rect [ 83.36575 739.7008 359.3657 751.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 693.7008 0 ] /Rect [ 83.36575 643.7008 383.3657 655.7008 ] /Subtype /Link /Type /Annot >> endobj 732 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 669.7008 0 ] /Rect [ 83.36575 619.7008 383.3657 631.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 633.7008 0 ] /Rect [ 83.36575 595.7008 323.3657 607.7008 ] /Subtype /Link /Type /Annot >> endobj 733 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 609.7008 0 ] /Rect [ 83.36575 571.7008 323.3657 583.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 561.7008 0 ] /Rect [ 83.36575 535.7008 323.3657 547.7008 ] /Subtype /Link /Type /Annot >> endobj 734 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 537.7008 0 ] /Rect [ 83.36575 511.7008 323.3657 523.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 525.7008 0 ] /Rect [ 83.36575 499.7008 323.3657 511.7008 ] /Subtype /Link /Type /Annot >> endobj 735 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 501.7008 0 ] /Rect [ 83.36575 475.7008 323.3657 487.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 381.7008 0 ] /Rect [ 83.36575 79.70079 335.3657 91.70079 ] /Subtype /Link /Type /Annot >> endobj 736 0 obj << -/Annots [ 731 0 R 732 0 R 733 0 R 734 0 R 735 0 R ] /Contents 1274 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 730 0 R 731 0 R 732 0 R 733 0 R 734 0 R 735 0 R ] /Contents 1270 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4302,17 +4298,12 @@ endobj endobj 737 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 357.7008 0 ] /Rect [ 83.36575 763.7008 335.3657 775.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 381.7008 0 ] /Rect [ 83.36575 631.7008 335.3657 643.7008 ] /Subtype /Link /Type /Annot >> endobj 738 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 736 0 R /XYZ 40.01575 357.7008 0 ] /Rect [ 83.36575 607.7008 335.3657 619.7008 ] /Subtype /Link /Type /Annot ->> -endobj -739 0 obj -<< -/Annots [ 737 0 R 738 0 R ] /Contents 1275 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 737 0 R ] /Contents 1271 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4320,9 +4311,19 @@ endobj >> /Type /Page >> endobj +739 0 obj +<< +/Contents 1272 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj 740 0 obj << -/Contents 1276 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1273 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4332,197 +4333,177 @@ endobj endobj 741 0 obj << -/Contents 1277 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 744 0 R /XYZ 40.01575 314.1008 0 ] /Rect [ 83.36575 360.1008 263.3657 372.1008 ] /Subtype /Link /Type /Annot >> endobj 742 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 745 0 R /XYZ 40.01575 290.1008 0 ] /Rect [ 83.36575 336.1008 263.3657 348.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 744 0 R /XYZ 40.01575 314.1008 0 ] /Rect [ 83.36575 324.1008 263.3657 336.1008 ] /Subtype /Link /Type /Annot >> endobj 743 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 745 0 R /XYZ 40.01575 290.1008 0 ] /Rect [ 83.36575 300.1008 263.3657 312.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 744 0 R /XYZ 40.01575 314.1008 0 ] /Rect [ 83.36575 204.1008 263.3657 216.1008 ] /Subtype /Link /Type /Annot >> endobj 744 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 745 0 R /XYZ 40.01575 290.1008 0 ] /Rect [ 83.36575 180.1008 263.3657 192.1008 ] /Subtype /Link /Type /Annot +/Annots [ 741 0 R 742 0 R 743 0 R ] /Contents 1274 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 745 0 obj << -/Annots [ 742 0 R 743 0 R 744 0 R ] /Contents 1278 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 470.1008 0 ] /Rect [ 83.36575 444.1008 317.3657 456.1008 ] /Subtype /Link /Type /Annot >> endobj 746 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 446.1008 0 ] /Rect [ 83.36575 420.1008 317.3657 432.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 434.1008 0 ] /Rect [ 83.36575 408.1008 305.3657 420.1008 ] /Subtype /Link /Type /Annot >> endobj 747 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 410.1008 0 ] /Rect [ 83.36575 384.1008 305.3657 396.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 398.1008 0 ] /Rect [ 83.36575 372.1008 341.3657 384.1008 ] /Subtype /Link /Type /Annot >> endobj 748 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 374.1008 0 ] /Rect [ 83.36575 348.1008 341.3657 360.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 749 0 R /XYZ 40.01575 362.1008 0 ] /Rect [ 83.36575 324.1008 335.3657 336.1008 ] /Subtype /Link /Type /Annot >> endobj 749 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 750 0 R /XYZ 40.01575 338.1008 0 ] /Rect [ 83.36575 300.1008 335.3657 312.1008 ] /Subtype /Link /Type /Annot +/Annots [ 745 0 R 746 0 R 747 0 R 748 0 R ] /Contents 1275 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 750 0 obj << -/Annots [ 746 0 R 747 0 R 748 0 R 749 0 R ] /Contents 1279 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 753 0 R /XYZ 40.01575 501.7008 0 ] /Rect [ 83.36575 463.7008 359.3657 475.7008 ] /Subtype /Link /Type /Annot >> endobj 751 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 477.7008 0 ] /Rect [ 83.36575 439.7008 359.3657 451.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 753 0 R /XYZ 40.01575 381.7008 0 ] /Rect [ 83.36575 355.7008 389.3657 367.7008 ] /Subtype /Link /Type /Annot >> endobj 752 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 357.7008 0 ] /Rect [ 83.36575 331.7008 389.3657 343.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 753 0 R /XYZ 40.01575 345.7008 0 ] /Rect [ 83.36575 319.7008 395.3657 331.7008 ] /Subtype /Link /Type /Annot >> endobj 753 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 754 0 R /XYZ 40.01575 321.7008 0 ] /Rect [ 83.36575 295.7008 395.3657 307.7008 ] /Subtype /Link /Type /Annot +/Annots [ 750 0 R 751 0 R 752 0 R ] /Contents 1276 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 754 0 obj << -/Annots [ 751 0 R 752 0 R 753 0 R ] /Contents 1280 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1277 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 755 0 obj << -/Contents 1281 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 658 0 R /XYZ 40.01575 131.9008 0 ] /Rect [ 83.36575 691.5008 251.3657 703.5008 ] /Subtype /Link /Type /Annot >> endobj 756 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 660 0 R /XYZ 40.01575 662.1008 0 ] /Rect [ 83.36575 575.9008 251.3657 587.9008 ] /Subtype /Link /Type /Annot +/Annots [ 755 0 R ] /Contents 1278 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 757 0 obj << -/Annots [ 756 0 R ] /Contents 1282 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1279 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 758 0 obj << -/Contents 1283 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 415.7008 0 ] /Rect [ 83.36575 594.9008 275.3657 606.9008 ] /Subtype /Link /Type /Annot >> endobj 759 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 295.7008 0 ] /Rect [ 83.36575 444.5008 275.3657 456.5008 ] /Subtype /Link /Type /Annot +/Annots [ 758 0 R ] /Contents 1280 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 760 0 obj << -/Annots [ 759 0 R ] /Contents 1284 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1281 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 761 0 obj << -/Contents 1285 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 415.7008 0 ] /Rect [ 83.36575 662.5008 275.3657 674.5008 ] /Subtype /Link /Type /Annot >> endobj 762 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 295.7008 0 ] /Rect [ 83.36575 526.5008 275.3657 538.5008 ] /Subtype /Link /Type /Annot +/Annots [ 761 0 R ] /Contents 1282 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 763 0 obj << -/Annots [ 762 0 R ] /Contents 1286 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 415.7008 0 ] /Rect [ 83.36575 118.5008 275.3657 130.5008 ] /Subtype /Link /Type /Annot >> endobj 764 0 obj << -/Contents 1287 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 763 0 R ] /Contents 1283 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << +>> /Rotate 0 + /Trans << ->> - /Type /Page +>> /Type /Page >> endobj 765 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 295.7008 0 ] /Rect [ 83.36575 679.7008 275.3657 691.7008 ] /Subtype /Link /Type /Annot ->> -endobj -766 0 obj -<< -/Annots [ 765 0 R ] /Contents 1288 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -767 0 obj -<< -/Contents 1289 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1284 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4530,14 +4511,24 @@ endobj /Type /Page >> endobj -768 0 obj +766 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 295.7008 0 ] /Rect [ 83.36575 424.5008 275.3657 436.5008 ] /Subtype /Link /Type /Annot +/Contents 1285 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page >> endobj -769 0 obj +767 0 obj << -/Annots [ 768 0 R ] /Contents 1290 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 415.7008 0 ] /Rect [ 83.36575 576.1008 275.3657 588.1008 ] /Subtype /Link /Type /Annot +>> +endobj +768 0 obj +<< +/Annots [ 767 0 R ] /Contents 1286 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4545,9 +4536,19 @@ endobj >> /Type /Page >> endobj +769 0 obj +<< +/Contents 1287 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj 770 0 obj << -/Contents 1291 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1288 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4557,7 +4558,7 @@ endobj endobj 771 0 obj << -/Contents 1292 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1289 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4567,22 +4568,12 @@ endobj endobj 772 0 obj << -/Contents 1293 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 775 0 R /XYZ 40.01575 415.7008 0 ] /Rect [ 83.36575 662.5008 275.3657 674.5008 ] /Subtype /Link /Type /Annot >> endobj 773 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 776 0 R /XYZ 40.01575 295.7008 0 ] /Rect [ 83.36575 526.5008 275.3657 538.5008 ] /Subtype /Link /Type /Annot ->> -endobj -774 0 obj -<< -/Annots [ 773 0 R ] /Contents 1294 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 772 0 R ] /Contents 1290 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4590,9 +4581,19 @@ endobj >> /Type /Page >> endobj +774 0 obj +<< +/Contents 1291 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj 775 0 obj << -/Contents 1295 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1292 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4602,7 +4603,7 @@ endobj endobj 776 0 obj << -/Contents 1296 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1293 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4612,7 +4613,7 @@ endobj endobj 777 0 obj << -/Contents 1297 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1294 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4622,22 +4623,7 @@ endobj endobj 778 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 645.7008 0 ] /Rect [ 83.36575 454.5008 305.3657 466.5008 ] /Subtype /Link /Type /Annot ->> -endobj -779 0 obj -<< -/Annots [ 778 0 R ] /Contents 1298 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page ->> -endobj -780 0 obj -<< -/Contents 1299 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1295 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4645,139 +4631,169 @@ endobj /Type /Page >> endobj +779 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 270.5008 329.3657 282.5008 ] /Subtype /Link /Type /Annot +>> +endobj +780 0 obj +<< +/Annots [ 779 0 R ] /Contents 1296 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page +>> +endobj 781 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 645.7008 0 ] /Rect [ 83.36575 583.7008 305.3657 595.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 308.5008 0 ] /Rect [ 83.36575 727.7008 299.3657 739.7008 ] /Subtype /Link /Type /Annot >> endobj 782 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 609.7008 0 ] /Rect [ 83.36575 547.7008 353.3657 559.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 691.7008 329.3657 703.7008 ] /Subtype /Link /Type /Annot >> endobj 783 0 obj << -/Annots [ 781 0 R 782 0 R ] /Contents 1300 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 308.5008 0 ] /Rect [ 83.36575 655.7008 299.3657 667.7008 ] /Subtype /Link /Type /Annot >> endobj 784 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 703.7008 329.3657 715.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 619.7008 329.3657 631.7008 ] /Subtype /Link /Type /Annot >> endobj 785 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 791 0 R /XYZ 40.01575 741.7008 0 ] /Rect [ 83.36575 451.7008 299.3657 463.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 308.5008 0 ] /Rect [ 83.36575 463.7008 299.3657 475.7008 ] /Subtype /Link /Type /Annot >> endobj 786 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 415.7008 329.3657 427.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 427.7008 329.3657 439.7008 ] /Subtype /Link /Type /Annot >> endobj 787 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 791 0 R /XYZ 40.01575 741.7008 0 ] /Rect [ 83.36575 379.7008 299.3657 391.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 295.7008 329.3657 307.7008 ] /Subtype /Link /Type /Annot >> endobj 788 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 343.7008 329.3657 355.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 572.5008 0 ] /Rect [ 83.36575 163.7008 329.3657 175.7008 ] /Subtype /Link /Type /Annot >> endobj 789 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 791 0 R /XYZ 40.01575 741.7008 0 ] /Rect [ 83.36575 187.7008 299.3657 199.7008 ] /Subtype /Link /Type /Annot +/Annots [ 781 0 R 782 0 R 783 0 R 784 0 R 785 0 R 786 0 R 787 0 R 788 0 R ] /Contents 1297 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 790 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 151.7008 329.3657 163.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 780 0 R /XYZ 40.01575 308.5008 0 ] /Rect [ 83.36575 607.7008 299.3657 619.7008 ] /Subtype /Link /Type /Annot >> endobj 791 0 obj << -/Annots [ 784 0 R 785 0 R 786 0 R 787 0 R 788 0 R 789 0 R 790 0 R ] /Contents 1301 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 655.3008 0 ] /Rect [ 93.58575 526.3008 199.1657 538.3008 ] /Subtype /Link /Type /Annot >> endobj 792 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 727.7008 329.3657 739.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 556 0 R /XYZ 40.01575 473.3008 0 ] /Rect [ 63.01575 491.0508 131.9257 503.0508 ] /Subtype /Link /Type /Annot >> endobj 793 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 783 0 R /XYZ 40.01575 284.5008 0 ] /Rect [ 83.36575 595.7008 329.3657 607.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 558 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 88.03575 472.3008 171.3957 484.3008 ] /Subtype /Link /Type /Annot >> endobj 794 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 791 0 R /XYZ 40.01575 741.7008 0 ] /Rect [ 83.36575 331.7008 299.3657 343.7008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 757 0 R /XYZ 40.01575 655.3008 0 ] /Rect [ 93.58575 321.9008 199.1657 333.9008 ] /Subtype /Link /Type /Annot >> endobj 795 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 511.3008 0 ] /Rect [ 93.58575 250.3008 199.1657 262.3008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 556 0 R /XYZ 40.01575 473.3008 0 ] /Rect [ 63.01575 286.6508 131.9257 298.6508 ] /Subtype /Link /Type /Annot >> endobj 796 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 556 0 R /XYZ 40.01575 473.3008 0 ] /Rect [ 63.01575 215.0508 131.9257 227.0508 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 558 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 88.03575 267.9008 171.3957 279.9008 ] /Subtype /Link /Type /Annot >> endobj 797 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 558 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 88.03575 196.3008 171.3957 208.3008 ] /Subtype /Link /Type /Annot +/Annots [ 790 0 R 791 0 R 792 0 R 793 0 R 794 0 R 795 0 R 796 0 R ] /Contents 1298 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 798 0 obj << -/Annots [ 792 0 R 793 0 R 794 0 R 795 0 R 796 0 R 797 0 R ] /Contents 1302 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1299 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 799 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 758 0 R /XYZ 40.01575 511.3008 0 ] /Rect [ 93.58575 760.7008 199.1657 772.7008 ] /Subtype /Link /Type /Annot +/Contents 1300 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page >> endobj 800 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 556 0 R /XYZ 40.01575 473.3008 0 ] /Rect [ 63.01575 725.4508 131.9257 737.4508 ] /Subtype /Link /Type /Annot +/Contents 1301 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page >> endobj 801 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 558 0 R /XYZ 40.01575 777.7008 0 ] /Rect [ 88.03575 706.7008 171.3957 718.7008 ] /Subtype /Link /Type /Annot +/Contents 1302 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page >> endobj 802 0 obj << -/Annots [ 799 0 R 800 0 R 801 0 R ] /Contents 1303 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1303 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 803 0 obj << -/Contents 1304 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1304 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4787,151 +4803,111 @@ endobj endobj 804 0 obj << -/Contents 1305 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html) +>> /Border [ 0 0 0 ] /Rect [ 63.01575 307.7008 459.8257 319.7008 ] /Subtype /Link /Type /Annot >> endobj 805 0 obj << -/Contents 1306 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://spectreattack.com/spectre.pdf) +>> /Border [ 0 0 0 ] /Rect [ 103.0357 289.7008 266.4457 301.7008 ] /Subtype /Link /Type /Annot >> endobj 806 0 obj << -/Contents 1307 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://meltdownattack.com/meltdown.pdf) +>> /Border [ 0 0 0 ] /Rect [ 111.3657 271.7008 294.7757 283.7008 ] /Subtype /Link /Type /Annot >> endobj 807 0 obj << -/Contents 1308 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf) +>> /Border [ 0 0 0 ] /Rect [ 44.5778 241.7008 573.6978 253.7008 ] /Subtype /Link /Type /Annot >> endobj 808 0 obj << -/Contents 1309 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://support.google.com/faqs/answer/7625886) +>> /Border [ 0 0 0 ] /Rect [ 63.01575 211.7008 279.2457 223.7008 ] /Subtype /Link /Type /Annot >> endobj 809 0 obj << -/A << -/S /URI /Type /Action /URI (https://googleprojectzero.blogspot.com/2018/01/reading-privileged-memory-with-side.html) ->> /Border [ 0 0 0 ] /Rect [ 63.01575 556.7008 459.8257 568.7008 ] /Subtype /Link /Type /Annot +/Annots [ 804 0 R 805 0 R 806 0 R 807 0 R 808 0 R ] /Contents 1305 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 810 0 obj << /A << -/S /URI /Type /Action /URI (https://spectreattack.com/spectre.pdf) ->> /Border [ 0 0 0 ] /Rect [ 103.0357 538.7008 266.4457 550.7008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://uefi.org/) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 698.5008 153.4057 710.5008 ] /Subtype /Link /Type /Annot >> endobj 811 0 obj << /A << -/S /URI /Type /Action /URI (https://meltdownattack.com/meltdown.pdf) ->> /Border [ 0 0 0 ] /Rect [ 111.3657 520.7008 294.7757 532.7008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://uefi.org/) +>> /Border [ 0 0 0 ] /Rect [ 290.6857 359.3008 409.0657 371.3008 ] /Subtype /Link /Type /Annot >> endobj 812 0 obj << -/A << -/S /URI /Type /Action /URI (https://software.intel.com/sites/default/files/managed/c5/63/336996-Speculative-Execution-Side-Channel-Mitigations.pdf) ->> /Border [ 0 0 0 ] /Rect [ 44.5778 490.7008 573.6978 502.7008 ] /Subtype /Link /Type /Annot +/Annots [ 810 0 R 811 0 R ] /Contents 1306 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 813 0 obj << /A << -/S /URI /Type /Action /URI (https://support.google.com/faqs/answer/7625886) ->> /Border [ 0 0 0 ] /Rect [ 63.01575 460.7008 279.2457 472.7008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.kb.cert.org/vuls/id/976132) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 624.1008 481.8857 636.1008 ] /Subtype /Link /Type /Annot >> endobj 814 0 obj << /A << -/S /URI /Type /Action /URI (http://uefi.org/) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 214.5008 153.4057 226.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.intelsecurity.com/advanced-threat-research/content/WP_Intel_ATR_S3_ResBS_Vuln.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 606.1008 307.8957 618.1008 ] /Subtype /Link /Type /Annot >> endobj 815 0 obj << -/Annots [ 809 0 R 810 0 R 811 0 R 812 0 R 813 0 R 814 0 R ] /Contents 1310 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/A << +/S /URI /Type /Action /URI (https://events.ccc.de/congress/2014/Fahrplan/system/attachments/2557/original/AttacksOnUEFI_Slides.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 588.1008 151.1657 600.1008 ] /Subtype /Link /Type /Annot >> endobj 816 0 obj << /A << -/S /URI /Type /Action /URI (http://uefi.org/) ->> /Border [ 0 0 0 ] /Rect [ 290.6857 580.5008 409.0657 592.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://bromiumlabs.files.wordpress.com/2015/01/venamis_whitepaper.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 570.1008 158.3957 582.1008 ] /Subtype /Link /Type /Annot >> endobj 817 0 obj << /A << -/S /URI /Type /Action /URI (https://www.kb.cert.org/vuls/id/976132) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 296.9008 481.8857 308.9008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://blog.cr4.sh/2015/02/exploiting-uefi-boot-script-table.html) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 552.1008 237.8657 564.1008 ] /Subtype /Link /Type /Annot >> endobj 818 0 obj << -/A << -/S /URI /Type /Action /URI (http://www.intelsecurity.com/advanced-threat-research/content/WP_Intel_ATR_S3_ResBS_Vuln.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 278.9008 307.8957 290.9008 ] /Subtype /Link /Type /Annot ->> -endobj -819 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://events.ccc.de/congress/2014/Fahrplan/system/attachments/2557/original/AttacksOnUEFI_Slides.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 260.9008 151.1657 272.9008 ] /Subtype /Link /Type /Annot ->> -endobj -820 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://bromiumlabs.files.wordpress.com/2015/01/venamis_whitepaper.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 242.9008 158.3957 254.9008 ] /Subtype /Link /Type /Annot ->> -endobj -821 0 obj -<< -/A << -/S /URI /Type /Action /URI (http://blog.cr4.sh/2015/02/exploiting-uefi-boot-script-table.html) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 224.9008 237.8657 236.9008 ] /Subtype /Link /Type /Annot ->> -endobj -822 0 obj -<< -/Annots [ 816 0 R 817 0 R 818 0 R 819 0 R 820 0 R 821 0 R ] /Contents 1311 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 813 0 R 814 0 R 815 0 R 816 0 R 817 0 R ] /Contents 1307 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4939,44 +4915,75 @@ endobj >> /Type /Page >> endobj -823 0 obj +819 0 obj << /A << /S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-16/dc16-presentations/brossard/defcon-16-brossard-wp.pdf) ->> /Border [ 0 0 0 ] /Rect [ 101.6957 552.1008 501.8857 564.1008 ] /Subtype /Link /Type /Annot +>> /Border [ 0 0 0 ] /Rect [ 101.6957 748.1008 501.8857 760.1008 ] /Subtype /Link /Type /Annot +>> +endobj +820 0 obj +<< +/A << +/S /URI /Type /Action /URI (http://syscan.org/index.php/download/get/6e597f6067493dd581eed737146f3afb/SyScan2014_CoreyKallenberg_SetupforFailureDefeatingSecureBoot.zip) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 452.5008 217.3257 464.5008 ] /Subtype /Link /Type /Annot +>> +endobj +821 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) +>> /Border [ 0 0 0 ] /Rect [ 275.6757 434.5008 553.5757 446.5008 ] /Subtype /Link /Type /Annot +>> +endobj +822 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 422.5008 552.3757 434.5008 ] /Subtype /Link /Type /Annot +>> +endobj +823 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 410.5008 135.0357 422.5008 ] /Subtype /Link /Type /Annot >> endobj 824 0 obj << /A << -/S /URI /Type /Action /URI (http://syscan.org/index.php/download/get/6e597f6067493dd581eed737146f3afb/SyScan2014_CoreyKallenberg_SetupforFailureDefeatingSecureBoot.zip) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 256.5008 217.3257 268.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://powerofcommunity.net/poc2007/sunbing.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 192.9008 291.2157 204.9008 ] /Subtype /Link /Type /Annot >> endobj 825 0 obj << -/A << -/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) ->> /Border [ 0 0 0 ] /Rect [ 275.6757 238.5008 553.5757 250.5008 ] /Subtype /Link /Type /Annot +/Annots [ 819 0 R 820 0 R 821 0 R 822 0 R 823 0 R 824 0 R ] /Contents 1308 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 826 0 obj << /A << -/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 226.5008 552.3757 238.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.c7zero.info/stuff/Windows8SecureBoot_Bulygin-Furtak-Bazhniuk_BHUSA2013.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 612.1008 300.1357 624.1008 ] /Subtype /Link /Type /Annot >> endobj 827 0 obj << /A << -/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 214.5008 135.0357 226.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://bromiumlabs.files.wordpress.com/2015/01/speed_racer_whitepaper.pdf) +>> /Border [ 0 0 0 ] /Rect [ 145.6257 516.1008 203.9857 528.1008 ] /Subtype /Link /Type /Annot >> endobj 828 0 obj << -/Annots [ 823 0 R 824 0 R 825 0 R 826 0 R 827 0 R ] /Contents 1312 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 826 0 R 827 0 R ] /Contents 1309 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -4987,58 +4994,41 @@ endobj 829 0 obj << /A << -/S /URI /Type /Action /URI (http://powerofcommunity.net/poc2007/sunbing.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 730.1008 291.2157 742.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://blog.ptsecurity.com/2018/10/intel-me-manufacturing-mode-macbook.html) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 335.2508 394.0357 347.2508 ] /Subtype /Link /Type /Annot >> endobj 830 0 obj << /A << -/S /URI /Type /Action /URI (http://www.c7zero.info/stuff/Windows8SecureBoot_Bulygin-Furtak-Bazhniuk_BHUSA2013.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 446.5008 300.1357 458.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/*/include/soc/pci_devs.h) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 316.5008 99.47575 328.5008 ] /Subtype /Link /Type /Annot >> endobj 831 0 obj << /A << -/S /URI /Type /Action /URI (https://bromiumlabs.files.wordpress.com/2015/01/speed_racer_whitepaper.pdf) ->> /Border [ 0 0 0 ] /Rect [ 145.6257 350.5008 203.9857 362.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/apollolake/cse.c) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 261.6508 386.8357 273.6508 ] /Subtype /Link /Type /Annot >> endobj 832 0 obj << -/Annots [ 829 0 R 830 0 R 831 0 R ] /Contents 1313 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/A << +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/pch.h) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 186.1008 71.12575 198.1008 ] /Subtype /Link /Type /Annot >> endobj 833 0 obj << /A << -/S /URI /Type /Action /URI (https://blog.ptsecurity.com/2018/10/intel-me-manufacturing-mode-macbook.html) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 179.2508 394.0357 191.2508 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/me.h) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 149.7008 65.01575 161.7008 ] /Subtype /Link /Type /Annot >> endobj 834 0 obj << -/A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/*/include/soc/pci_devs.h) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 160.5008 99.47575 172.5008 ] /Subtype /Link /Type /Annot ->> -endobj -835 0 obj -<< -/A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/apollolake/cse.c) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 105.6508 386.8357 117.6508 ] /Subtype /Link /Type /Annot ->> -endobj -836 0 obj -<< -/Annots [ 833 0 R 834 0 R 835 0 R ] /Contents 1314 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 829 0 R 830 0 R 831 0 R 832 0 R 833 0 R ] /Contents 1310 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5046,30 +5036,47 @@ endobj >> /Type /Page >> endobj +835 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/me_status.c) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 672.1008 110.0257 684.1008 ] /Subtype /Link /Type /Annot +>> +endobj +836 0 obj +<< +/A << +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c) +>> /Border [ 0 0 0 ] /Rect [ 91.70575 98.50079 469.6557 110.5008 ] /Subtype /Link /Type /Annot +>> +endobj 837 0 obj << /A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/pch.h) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 729.7008 71.12575 741.7008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 86.50079 439.0657 98.50079 ] /Subtype /Link /Type /Annot >> endobj 838 0 obj << -/A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/me.h) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 693.3008 65.01575 705.3008 ] /Subtype /Link /Type /Annot +/Annots [ 835 0 R 836 0 R 837 0 R ] /Contents 1311 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 839 0 obj << /A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/me_status.c) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 522.5008 110.0257 534.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/bh08/part2-full.pdf) +>> /Border [ 0 0 0 ] /Rect [ 91.70575 374.9008 322.9057 386.9008 ] /Subtype /Link /Type /Annot >> endobj 840 0 obj << -/Annots [ 837 0 R 838 0 R 839 0 R ] /Contents 1315 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 839 0 R ] /Contents 1312 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5080,27 +5087,27 @@ endobj 841 0 obj << /A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c) ->> /Border [ 0 0 0 ] /Rect [ 91.70575 642.1008 469.6557 654.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/archive/fr/sciences/fichiers/lti/cansecwest2006-duflot.pdf) +>> /Border [ 0 0 0 ] /Rect [ 130.6257 306.9008 411.2957 318.9008 ] /Subtype /Link /Type /Annot >> endobj 842 0 obj << /A << -/S /URI /Type /Action /URI (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 630.1008 439.0657 642.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://fawlty.cs.usfca.edu/~cruse/cs630f06/duflot.pdf) +>> /Border [ 0 0 0 ] /Rect [ 96.70575 240.9008 338.9857 252.9008 ] /Subtype /Link /Type /Annot >> endobj 843 0 obj << /A << -/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/bh08/part2-full.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 364.5008 271.2157 376.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://phrack.org/issues/65/7.html) +>> /Border [ 0 0 0 ] /Rect [ 361.2257 240.9008 500.1557 252.9008 ] /Subtype /Link /Type /Annot >> endobj 844 0 obj << -/Annots [ 841 0 R 842 0 R 843 0 R ] /Contents 1316 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 841 0 R 842 0 R 843 0 R ] /Contents 1313 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5111,93 +5118,103 @@ endobj 845 0 obj << /A << -/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/archive/fr/sciences/fichiers/lti/cansecwest2006-duflot.pdf) ->> /Border [ 0 0 0 ] /Rect [ 78.93575 448.5008 359.6057 460.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/archive/fr/sciences/fichiers/lti/pacsec2007-duflot-papier.pdf) +>> /Border [ 0 0 0 ] /Rect [ 181.7257 358.5008 469.0557 370.5008 ] /Subtype /Link /Type /Annot >> endobj 846 0 obj << /A << -/S /URI /Type /Action /URI (http://fawlty.cs.usfca.edu/~cruse/cs630f06/duflot.pdf) ->> /Border [ 0 0 0 ] /Rect [ 96.70575 382.5008 338.9857 394.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/uploads/IMG/pdf/IT_Defense_2010_final.pdf) +>> /Border [ 0 0 0 ] /Rect [ 491.2957 358.5008 524.6357 370.5008 ] /Subtype /Link /Type /Annot >> endobj 847 0 obj << /A << -/S /URI /Type /Action /URI (http://phrack.org/issues/65/7.html) ->> /Border [ 0 0 0 ] /Rect [ 361.2257 382.5008 500.1557 394.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/uploads/IMG/pdf/IT_Defense_2010_final.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 346.5008 250.1057 358.5008 ] /Subtype /Link /Type /Annot >> endobj 848 0 obj << -/Annots [ 845 0 R 846 0 R 847 0 R ] /Contents 1317 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/A << +/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) +>> /Border [ 0 0 0 ] /Rect [ 97.82575 334.5008 553.0057 346.5008 ] /Subtype /Link /Type /Annot >> endobj 849 0 obj << /A << -/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/archive/fr/sciences/fichiers/lti/pacsec2007-duflot-papier.pdf) ->> /Border [ 0 0 0 ] /Rect [ 181.7257 582.1008 469.0557 594.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 322.5008 470.1157 334.5008 ] /Subtype /Link /Type /Annot >> endobj 850 0 obj << -/A << -/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/uploads/IMG/pdf/IT_Defense_2010_final.pdf) ->> /Border [ 0 0 0 ] /Rect [ 491.2957 582.1008 524.6357 594.1008 ] /Subtype /Link /Type /Annot +/Annots [ 845 0 R 846 0 R 847 0 R 848 0 R 849 0 R ] /Contents 1314 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 851 0 obj << /A << -/S /URI /Type /Action /URI (http://www.ssi.gouv.fr/uploads/IMG/pdf/IT_Defense_2010_final.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 570.1008 250.1057 582.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/misc09/smm_cache_fun.pdf) +>> /Border [ 0 0 0 ] /Rect [ 462.4057 748.1008 529.6457 760.1008 ] /Subtype /Link /Type /Annot >> endobj 852 0 obj << /A << -/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) ->> /Border [ 0 0 0 ] /Rect [ 97.82575 558.1008 553.0057 570.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/misc09/smm_cache_fun.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 736.1008 215.6257 748.1008 ] /Subtype /Link /Type /Annot >> endobj 853 0 obj << /A << -/S /URI /Type /Action /URI (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 546.1008 470.1157 558.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://cansecwest.com/csw09/csw09-duflot.pdf) +>> /Border [ 0 0 0 ] /Rect [ 237.8657 736.1008 420.1557 748.1008 ] /Subtype /Link /Type /Annot >> endobj 854 0 obj << -/A << -/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/misc09/smm_cache_fun.pdf) ->> /Border [ 0 0 0 ] /Rect [ 462.4057 292.5008 529.6457 304.5008 ] /Subtype /Link /Type /Annot +/Annots [ 851 0 R 852 0 R 853 0 R ] /Contents 1315 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 855 0 obj << /A << -/S /URI /Type /Action /URI (http://www.invisiblethingslab.com/resources/misc09/smm_cache_fun.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 280.5008 215.6257 292.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.flashrom.org/) +>> /Border [ 0 0 0 ] /Rect [ 402.3657 92.90079 440.7057 104.9008 ] /Subtype /Link /Type /Annot >> endobj 856 0 obj << /A << -/S /URI /Type /Action /URI (http://cansecwest.com/csw09/csw09-duflot.pdf) ->> /Border [ 0 0 0 ] /Rect [ 237.8657 280.5008 420.1557 292.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.mitre.org/capabilities/cybersecurity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) +>> /Border [ 0 0 0 ] /Rect [ 370.6957 80.90079 554.6357 92.90079 ] /Subtype /Link /Type /Annot >> endobj 857 0 obj << -/Annots [ 849 0 R 850 0 R 851 0 R 852 0 R 853 0 R 854 0 R 855 0 R 856 0 R ] /Contents 1318 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/A << +/S /URI /Type /Action /URI (http://www.mitre.org/capabilities/cybersecurity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 68.90079 387.8957 80.90079 ] /Subtype /Link /Type /Annot +>> +endobj +858 0 obj +<< +/Annots [ 855 0 R 856 0 R 857 0 R ] /Contents 1316 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5205,92 +5222,75 @@ endobj >> /Type /Page >> endobj -858 0 obj -<< -/Contents 1319 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page ->> -endobj 859 0 obj << /A << -/S /URI /Type /Action /URI (http://www.flashrom.org/) ->> /Border [ 0 0 0 ] /Rect [ 402.3657 382.5008 440.7057 394.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/oem-uefi-wsmt) +>> /Border [ 0 0 0 ] /Rect [ 45.85575 528.1008 465.4257 540.1008 ] /Subtype /Link /Type /Annot >> endobj 860 0 obj << -/A << -/S /URI /Type /Action /URI (http://www.mitre.org/capabilities/cybersecurity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) ->> /Border [ 0 0 0 ] /Rect [ 370.6957 370.5008 554.6357 382.5008 ] /Subtype /Link /Type /Annot +/Annots [ 859 0 R ] /Contents 1317 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 861 0 obj << /A << -/S /URI /Type /Action /URI (http://www.mitre.org/capabilities/cybersecurity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 358.5008 387.8957 370.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf) +>> /Border [ 0 0 0 ] /Rect [ 245.0757 715.7008 554.0457 727.7008 ] /Subtype /Link /Type /Annot >> endobj 862 0 obj << /A << -/S /URI /Type /Action /URI (https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/oem-uefi-wsmt) ->> /Border [ 0 0 0 ] /Rect [ 45.85575 104.9008 465.4257 116.9008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 703.7008 444.5357 715.7008 ] /Subtype /Link /Type /Annot >> endobj 863 0 obj << -/Annots [ 859 0 R 860 0 R 861 0 R 862 0 R ] /Contents 1320 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/A << +/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) +>> /Border [ 0 0 0 ] /Rect [ 531.2457 703.7008 552.9257 715.7008 ] /Subtype /Link /Type /Annot >> endobj 864 0 obj << /A << -/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf) ->> /Border [ 0 0 0 ] /Rect [ 245.0757 310.1008 554.0457 322.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 691.7008 552.8957 703.7008 ] /Subtype /Link /Type /Annot >> endobj 865 0 obj << /A << -/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 298.1008 444.5357 310.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 679.7008 235.0557 691.7008 ] /Subtype /Link /Type /Annot >> endobj 866 0 obj << /A << -/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) ->> /Border [ 0 0 0 ] /Rect [ 531.2457 298.1008 552.9257 310.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://cansecwest.com/slides/2014/AllYourBoot_csw14-intel-final.pdf) +>> /Border [ 0 0 0 ] /Rect [ 431.8357 430.5008 555.3459 442.5008 ] /Subtype /Link /Type /Annot >> endobj 867 0 obj << /A << -/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 286.1008 552.8957 298.1008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://cansecwest.com/slides/2014/AllYourBoot_csw14-intel-final.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 418.5008 52.23575 430.5008 ] /Subtype /Link /Type /Annot >> endobj 868 0 obj << -/A << -/S /URI /Type /Action /URI (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation-wp.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 274.1008 235.0557 286.1008 ] /Subtype /Link /Type /Annot ->> -endobj -869 0 obj -<< -/Annots [ 864 0 R 865 0 R 866 0 R 867 0 R 868 0 R ] /Contents 1321 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 861 0 R 862 0 R 863 0 R 864 0 R 865 0 R 866 0 R 867 0 R ] /Contents 1318 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5298,23 +5298,33 @@ endobj >> /Type /Page >> endobj -870 0 obj +869 0 obj << /A << -/S /URI /Type /Action /URI (https://cansecwest.com/slides/2014/AllYourBoot_csw14-intel-final.pdf) ->> /Border [ 0 0 0 ] /Rect [ 431.8357 698.5008 555.3459 710.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (http://www.intelsecurity.com/advanced-threat-research/content/data/REConBrussels2017_BARing_the_system.pdf) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 292.5008 374.5757 304.5008 ] /Subtype /Link /Type /Annot +>> +endobj +870 0 obj +<< +/Annots [ 869 0 R ] /Contents 1319 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 871 0 obj << /A << -/S /URI /Type /Action /URI (https://cansecwest.com/slides/2014/AllYourBoot_csw14-intel-final.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 686.5008 52.23575 698.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://cansecwest.com/slides/2015/A%20New%20Class%20of%20Vulnin%20SMI%20-%20Andrew%20Furtak.pdf) +>> /Border [ 0 0 0 ] /Rect [ 126.1657 624.1008 433.4657 636.1008 ] /Subtype /Link /Type /Annot >> endobj 872 0 obj << -/Annots [ 870 0 R 871 0 R ] /Contents 1322 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 871 0 R ] /Contents 1320 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5325,20 +5335,13 @@ endobj 873 0 obj << /A << -/S /URI /Type /Action /URI (http://www.intelsecurity.com/advanced-threat-research/content/data/REConBrussels2017_BARing_the_system.pdf) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 532.5008 374.5757 544.5008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://www.virustotal.com/gui/join-us) +>> /Border [ 0 0 0 ] /Rect [ 359.5957 318.5008 524.0857 330.5008 ] /Subtype /Link /Type /Annot >> endobj 874 0 obj << -/A << -/S /URI /Type /Action /URI (https://cansecwest.com/slides/2015/A%20New%20Class%20of%20Vulnin%20SMI%20-%20Andrew%20Furtak.pdf) ->> /Border [ 0 0 0 ] /Rect [ 126.1657 160.9008 433.4657 172.9008 ] /Subtype /Link /Type /Annot ->> -endobj -875 0 obj -<< -/Annots [ 873 0 R 874 0 R ] /Contents 1323 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 873 0 R ] /Contents 1321 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5346,9 +5349,19 @@ endobj >> /Type /Page >> endobj +875 0 obj +<< +/Contents 1322 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj 876 0 obj << -/Contents 1324 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1323 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5358,94 +5371,77 @@ endobj endobj 877 0 obj << -/A << -/S /URI /Type /Action /URI (https://www.virustotal.com/gui/join-us) ->> /Border [ 0 0 0 ] /Rect [ 359.5957 522.5008 524.0857 534.5008 ] /Subtype /Link /Type /Annot +/Contents 1324 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page >> endobj 878 0 obj << -/Annots [ 877 0 R ] /Contents 1325 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Contents 1325 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << +>> /Rotate 0 /Trans << ->> /Type /Page +>> + /Type /Page >> endobj 879 0 obj << -/Contents 1326 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 506.1008 0 ] /Rect [ 83.36575 449.3008 389.3657 461.3008 ] /Subtype /Link /Type /Annot >> endobj 880 0 obj << -/Contents 1327 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 879 0 R ] /Contents 1326 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << +>> /Rotate 0 + /Trans << ->> - /Type /Page +>> /Type /Page >> endobj 881 0 obj << -/Contents 1328 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/BaseFont /Symbol /Name /F7 /Subtype /Type1 /Type /Font >> endobj 882 0 obj << -/Contents 1329 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 729.7008 0 ] /Rect [ 83.36575 165.5008 377.3657 177.5008 ] /Subtype /Link /Type /Annot >> endobj 883 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 729.7008 0 ] /Rect [ 83.36575 712.1008 389.3657 724.1008 ] /Subtype /Link /Type /Annot +/Annots [ 882 0 R ] /Contents 1327 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 884 0 obj << -/BaseFont /Symbol /Name /F7 /Subtype /Type1 /Type /Font +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 161.5008 0 ] /Rect [ 83.36575 527.1008 353.3657 539.1008 ] /Subtype /Link /Type /Annot >> endobj 885 0 obj << -/Annots [ 883 0 R ] /Contents 1330 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 686.1008 0 ] /Rect [ 83.36575 291.5008 371.3657 303.5008 ] /Subtype /Link /Type /Annot >> endobj 886 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 894 0 R /XYZ 40.01575 285.7008 0 ] /Rect [ 83.36575 444.1008 377.3657 456.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 686.1008 0 ] /Rect [ 83.36575 135.5008 371.3657 147.5008 ] /Subtype /Link /Type /Annot >> endobj 887 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 422.1008 0 ] /Rect [ 83.36575 87.50079 353.3657 99.50079 ] /Subtype /Link /Type /Annot ->> -endobj -888 0 obj -<< -/Annots [ 886 0 R 887 0 R ] /Contents 1331 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 884 0 R 885 0 R 886 0 R ] /Contents 1328 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5453,24 +5449,34 @@ endobj >> /Type /Page >> endobj +888 0 obj +<< +/Border [ 0 0 0 ] /Contents () /Dest [ 887 0 R /XYZ 40.01575 317.5008 0 ] /Rect [ 83.36575 607.7008 329.3657 619.7008 ] /Subtype /Link /Type /Annot +>> +endobj 889 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 188.5008 0 ] /Rect [ 83.36575 552.1008 371.3657 564.1008 ] /Subtype /Link /Type /Annot +/Annots [ 888 0 R ] /Contents 1329 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 890 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 188.5008 0 ] /Rect [ 83.36575 396.1008 371.3657 408.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 889 0 R /XYZ 40.01575 633.7008 0 ] /Rect [ 83.36575 703.7008 323.3657 715.7008 ] /Subtype /Link /Type /Annot >> endobj 891 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 578.1008 0 ] /Rect [ 83.36575 168.1008 329.3657 180.1008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 729.7008 0 ] /Rect [ 83.36575 221.1008 377.3657 233.1008 ] /Subtype /Link /Type /Annot >> endobj 892 0 obj << -/Annots [ 889 0 R 890 0 R 891 0 R ] /Contents 1332 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 890 0 R 891 0 R ] /Contents 1330 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5480,12 +5486,19 @@ endobj endobj 893 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 892 0 R /XYZ 40.01575 194.1008 0 ] /Rect [ 83.36575 259.7008 323.3657 271.7008 ] /Subtype /Link /Type /Annot +/A << +/S /URI /Type /Action /URI (http://www.oracle.com/technetwork/topics/security/cpujan2015-1972971.html) +>> /Border [ 0 0 0 ] /Rect [ 40.01575 686.5008 379.5957 698.5008 ] /Subtype /Link /Type /Annot >> endobj 894 0 obj << -/Annots [ 893 0 R ] /Contents 1333 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 506.1008 0 ] /Rect [ 83.36575 228.7008 389.3657 240.7008 ] /Subtype /Link /Type /Annot +>> +endobj +895 0 obj +<< +/Annots [ 893 0 R 894 0 R ] /Contents 1331 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5493,21 +5506,16 @@ endobj >> /Type /Page >> endobj -895 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 894 0 R /XYZ 40.01575 285.7008 0 ] /Rect [ 83.36575 497.1008 377.3657 509.1008 ] /Subtype /Link /Type /Annot ->> -endobj 896 0 obj << /A << -/S /URI /Type /Action /URI (http://www.oracle.com/technetwork/topics/security/cpujan2015-1972971.html) ->> /Border [ 0 0 0 ] /Rect [ 40.01575 247.9008 379.5957 259.9008 ] /Subtype /Link /Type /Annot +/S /URI /Type /Action /URI (https://xenbits.xen.org/xsa/advisory-188.html) +>> /Border [ 0 0 0 ] /Rect [ 233.4357 165.5008 431.2957 177.5008 ] /Subtype /Link /Type /Annot >> endobj 897 0 obj << -/Annots [ 895 0 R 896 0 R ] /Contents 1334 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 896 0 R ] /Contents 1332 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5517,49 +5525,32 @@ endobj endobj 898 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 729.7008 0 ] /Rect [ 83.36575 450.9008 389.3657 462.9008 ] /Subtype /Link /Type /Annot +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 398.1008 0 ] /Rect [ 83.36575 480.1008 383.3657 492.1008 ] /Subtype /Link /Type /Annot >> endobj 899 0 obj << -/Annots [ 898 0 R ] /Contents 1335 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 900 0 R /XYZ 40.01575 686.1008 0 ] /Rect [ 83.36575 372.1008 371.3657 384.1008 ] /Subtype /Link /Type /Annot >> endobj 900 0 obj << -/A << -/S /URI /Type /Action /URI (https://xenbits.xen.org/xsa/advisory-188.html) ->> /Border [ 0 0 0 ] /Rect [ 233.4357 387.1008 431.2957 399.1008 ] /Subtype /Link /Type /Annot +/Annots [ 898 0 R 899 0 R ] /Contents 1333 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 901 0 obj << -/Annots [ 900 0 R ] /Contents 1336 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Border [ 0 0 0 ] /Contents () /Dest [ 675 0 R /XYZ 40.01575 254.1008 0 ] /Rect [ 83.36575 388.5008 329.3657 400.5008 ] /Subtype /Link /Type /Annot >> endobj 902 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 904 0 R /XYZ 40.01575 621.7008 0 ] /Rect [ 83.36575 703.7008 383.3657 715.7008 ] /Subtype /Link /Type /Annot ->> -endobj -903 0 obj -<< -/Border [ 0 0 0 ] /Contents () /Dest [ 901 0 R /XYZ 40.01575 188.5008 0 ] /Rect [ 83.36575 595.7008 371.3657 607.7008 ] /Subtype /Link /Type /Annot ->> -endobj -904 0 obj -<< -/Annots [ 902 0 R 903 0 R ] /Contents 1337 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 901 0 R ] /Contents 1334 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5567,14 +5558,36 @@ endobj >> /Type /Page >> endobj +903 0 obj +<< +/Contents 1335 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj +904 0 obj +<< +/Contents 1336 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 /Trans << + +>> + /Type /Page +>> +endobj 905 0 obj << -/Border [ 0 0 0 ] /Contents () /Dest [ 679 0 R /XYZ 40.01575 489.7008 0 ] /Rect [ 83.36575 597.1008 329.3657 609.1008 ] /Subtype /Link /Type /Annot +/A << +/S /URI /Type /Action /URI (https://marc.info/?l=oss-security&m=143155206320935&w=2) +>> /Border [ 0 0 0 ] /Rect [ 43.34575 736.1008 313.7557 748.1008 ] /Subtype /Link /Type /Annot >> endobj 906 0 obj << -/Annots [ 905 0 R ] /Contents 1338 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << +/Annots [ 905 0 R ] /Contents 1337 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << /Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] >> /Rotate 0 /Trans << @@ -5584,1537 +5597,1510 @@ endobj endobj 907 0 obj << -/Contents 1339 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 /Trans << - ->> - /Type /Page +/A << +/S /URI /Type /Action /URI (https://github.com/chipsec/chipsec/wiki/files/training/OSFC_2018_CHIPSEC_Workshop.pdf) +>> /Border [ 0 0 0 ] /Rect [ 48.01575 726.9008 244.7457 738.9008 ] /Subtype /Link /Type /Annot >> endobj 908 0 obj << -/A << -/S /URI /Type /Action /URI (https://marc.info/?l=oss-security&m=143155206320935&w=2) ->> /Border [ 0 0 0 ] /Rect [ 43.34575 199.5008 313.7557 211.5008 ] /Subtype /Link /Type /Annot +/Annots [ 907 0 R ] /Contents 1338 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1193 0 R /Resources << +/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] +>> /Rotate 0 + /Trans << + +>> /Type /Page >> endobj 909 0 obj << -/Annots [ 908 0 R ] /Contents 1340 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Outlines 911 0 R /PageLabels 1339 0 R /PageMode /UseNone /Pages 1193 0 R /Type /Catalog >> endobj 910 0 obj << -/A << -/S /URI /Type /Action /URI (https://github.com/chipsec/chipsec/wiki/files/training/OSFC_2018_CHIPSEC_Workshop.pdf) ->> /Border [ 0 0 0 ] /Rect [ 48.01575 205.3008 244.7457 217.3008 ] /Subtype /Link /Type /Annot +/Author () /CreationDate (D:20210827081551+08'00') /Creator (\(unspecified\)) /Keywords () /ModDate (D:20210827081551+08'00') /Producer (ReportLab PDF Library - www.reportlab.com) + /Subject (\(unspecified\)) /Title () /Trapped /False >> endobj 911 0 obj << -/Annots [ 910 0 R ] /Contents 1341 0 R /MediaBox [ 0 0 595.2756 841.8898 ] /Parent 1196 0 R /Resources << -/Font 1 0 R /ProcSet [ /PDF /Text /ImageB /ImageC /ImageI ] ->> /Rotate 0 - /Trans << - ->> /Type /Page +/Count 333 /First 912 0 R /Last 912 0 R /Type /Outlines >> endobj 912 0 obj << -/Outlines 914 0 R /PageLabels 1342 0 R /PageMode /UseNone /Pages 1196 0 R /Type /Catalog +/Count 280 /Dest [ 499 0 R /XYZ 40.01575 775.7008 0 ] /First 913 0 R /Last 952 0 R /Parent 911 0 R /Title (CHIPSEC) >> endobj 913 0 obj << -/Author () /CreationDate (D:20210729161220+08'00') /Creator (\(unspecified\)) /Keywords () /ModDate (D:20210729161220+08'00') /Producer (ReportLab PDF Library - www.reportlab.com) - /Subject (\(unspecified\)) /Title () /Trapped /False +/Count 2 /Dest [ 499 0 R /XYZ 40.01575 384.9008 0 ] /First 914 0 R /Last 915 0 R /Next 916 0 R /Parent 912 0 R + /Title (Download CHIPSEC) >> endobj 914 0 obj << -/Count 333 /First 915 0 R /Last 915 0 R /Type /Outlines +/Dest [ 499 0 R /XYZ 40.01575 325.7008 0 ] /Next 915 0 R /Parent 913 0 R /Title (GitHub repository) >> endobj 915 0 obj << -/Count 280 /Dest [ 499 0 R /XYZ 40.01575 775.7008 0 ] /First 916 0 R /Last 955 0 R /Parent 914 0 R /Title (CHIPSEC) +/Dest [ 499 0 R /XYZ 40.01575 198.4008 0 ] /Parent 913 0 R /Prev 914 0 R /Title (Releases) >> endobj 916 0 obj << -/Count 2 /Dest [ 499 0 R /XYZ 40.01575 384.9008 0 ] /First 917 0 R /Last 918 0 R /Next 919 0 R /Parent 915 0 R - /Title (Download CHIPSEC) +/Dest [ 512 0 R /XYZ 40.01575 711.7008 0 ] /Next 917 0 R /Parent 912 0 R /Prev 913 0 R /Title (Contact) >> endobj 917 0 obj << -/Dest [ 499 0 R /XYZ 40.01575 325.7008 0 ] /Next 918 0 R /Parent 916 0 R /Title (GitHub repository) +/Count 24 /Dest [ 512 0 R /XYZ 40.01575 466.5008 0 ] /First 918 0 R /Last 939 0 R /Next 942 0 R /Parent 912 0 R + /Prev 916 0 R /Title (Installation) >> endobj 918 0 obj << -/Dest [ 499 0 R /XYZ 40.01575 198.4008 0 ] /Parent 916 0 R /Prev 917 0 R /Title (Releases) +/Count 4 /Dest [ 512 0 R /XYZ 40.01575 377.3008 0 ] /First 919 0 R /Last 922 0 R /Next 923 0 R /Parent 917 0 R + /Title (Windows Installation) >> endobj 919 0 obj << -/Dest [ 512 0 R /XYZ 40.01575 711.7008 0 ] /Next 920 0 R /Parent 915 0 R /Prev 916 0 R /Title (Contact) +/Dest [ 512 0 R /XYZ 40.01575 185.7008 0 ] /Next 920 0 R /Parent 918 0 R /Title (Install CHIPSEC Dependencies) >> endobj 920 0 obj << -/Count 24 /Dest [ 512 0 R /XYZ 40.01575 466.5008 0 ] /First 921 0 R /Last 942 0 R /Next 945 0 R /Parent 915 0 R - /Prev 919 0 R /Title (Installation) +/Dest [ 520 0 R /XYZ 40.01575 543.7008 0 ] /Next 921 0 R /Parent 918 0 R /Prev 919 0 R /Title (Building) >> endobj 921 0 obj << -/Count 4 /Dest [ 512 0 R /XYZ 40.01575 377.3008 0 ] /First 922 0 R /Last 925 0 R /Next 926 0 R /Parent 920 0 R - /Title (Windows Installation) +/Dest [ 520 0 R /XYZ 40.01575 318.5008 0 ] /Next 922 0 R /Parent 918 0 R /Prev 920 0 R /Title (Turn off kernel driver signature checks) >> endobj 922 0 obj << -/Dest [ 512 0 R /XYZ 40.01575 185.7008 0 ] /Next 923 0 R /Parent 921 0 R /Title (Install CHIPSEC Dependencies) +/Dest [ 522 0 R /XYZ 40.01575 519.7008 0 ] /Parent 918 0 R /Prev 921 0 R /Title (Alternate Build Methods) >> endobj 923 0 obj << -/Dest [ 520 0 R /XYZ 40.01575 543.7008 0 ] /Next 924 0 R /Parent 921 0 R /Prev 922 0 R /Title (Building) +/Count 2 /Dest [ 533 0 R /XYZ 40.01575 639.7008 0 ] /First 924 0 R /Last 925 0 R /Next 926 0 R /Parent 917 0 R + /Prev 918 0 R /Title (DAL Windows Installation) >> endobj 924 0 obj << -/Dest [ 520 0 R /XYZ 40.01575 318.5008 0 ] /Next 925 0 R /Parent 921 0 R /Prev 923 0 R /Title (Turn off kernel driver signature checks) +/Dest [ 533 0 R /XYZ 40.01575 582.9008 0 ] /Next 925 0 R /Parent 923 0 R /Title (Prerequisites) >> endobj 925 0 obj << -/Dest [ 522 0 R /XYZ 40.01575 519.7008 0 ] /Parent 921 0 R /Prev 924 0 R /Title (Alternate Build Methods) +/Dest [ 533 0 R /XYZ 40.01575 381.7008 0 ] /Parent 923 0 R /Prev 924 0 R /Title (Building) >> endobj 926 0 obj << -/Count 2 /Dest [ 533 0 R /XYZ 40.01575 639.7008 0 ] /First 927 0 R /Last 928 0 R /Next 929 0 R /Parent 920 0 R - /Prev 921 0 R /Title (DAL Windows Installation) +/Count 3 /Dest [ 533 0 R /XYZ 40.01575 291.3008 0 ] /First 927 0 R /Last 929 0 R /Next 930 0 R /Parent 917 0 R + /Prev 923 0 R /Title (Linux Installation) >> endobj 927 0 obj << -/Dest [ 533 0 R /XYZ 40.01575 582.9008 0 ] /Next 928 0 R /Parent 926 0 R /Title (Prerequisites) +/Dest [ 536 0 R /XYZ 40.01575 775.7008 0 ] /Next 928 0 R /Parent 926 0 R /Title (Prerequisites) >> endobj 928 0 obj << -/Dest [ 533 0 R /XYZ 40.01575 381.7008 0 ] /Parent 926 0 R /Prev 927 0 R /Title (Building) +/Dest [ 536 0 R /XYZ 40.01575 472.5008 0 ] /Next 929 0 R /Parent 926 0 R /Prev 927 0 R /Title (Building) >> endobj 929 0 obj << -/Count 3 /Dest [ 533 0 R /XYZ 40.01575 291.3008 0 ] /First 930 0 R /Last 932 0 R /Next 933 0 R /Parent 920 0 R - /Prev 926 0 R /Title (Linux Installation) +/Dest [ 536 0 R /XYZ 40.01575 346.1008 0 ] /Parent 926 0 R /Prev 928 0 R /Title (Creating a Live Linux image) >> endobj 930 0 obj << -/Dest [ 536 0 R /XYZ 40.01575 775.7008 0 ] /Next 931 0 R /Parent 929 0 R /Title (Prerequisites) +/Count 5 /Dest [ 536 0 R /XYZ 40.01575 183.7008 0 ] /First 931 0 R /Last 935 0 R /Next 936 0 R /Parent 917 0 R + /Prev 926 0 R /Title (MacOS Installation) >> endobj 931 0 obj << -/Dest [ 536 0 R /XYZ 40.01575 472.5008 0 ] /Next 932 0 R /Parent 929 0 R /Prev 930 0 R /Title (Building) +/Dest [ 541 0 R /XYZ 40.01575 775.7008 0 ] /Next 932 0 R /Parent 930 0 R /Title (Install CHIPSEC Dependencies) >> endobj 932 0 obj << -/Dest [ 536 0 R /XYZ 40.01575 346.1008 0 ] /Parent 929 0 R /Prev 931 0 R /Title (Creating a Live Linux image) +/Dest [ 541 0 R /XYZ 40.01575 526.5008 0 ] /Next 933 0 R /Parent 930 0 R /Prev 931 0 R /Title (Building Chipsec) >> endobj 933 0 obj << -/Count 5 /Dest [ 536 0 R /XYZ 40.01575 183.7008 0 ] /First 934 0 R /Last 938 0 R /Next 939 0 R /Parent 920 0 R - /Prev 929 0 R /Title (MacOS Installation) +/Dest [ 541 0 R /XYZ 40.01575 436.1008 0 ] /Next 934 0 R /Parent 930 0 R /Prev 932 0 R /Title (Run CHIPSEC) >> endobj 934 0 obj << -/Dest [ 541 0 R /XYZ 40.01575 775.7008 0 ] /Next 935 0 R /Parent 933 0 R /Title (Install CHIPSEC Dependencies) +/Dest [ 541 0 R /XYZ 40.01575 345.7008 0 ] /Next 935 0 R /Parent 930 0 R /Prev 933 0 R /Title (CHIPSEC Cleanup) >> endobj 935 0 obj << -/Dest [ 541 0 R /XYZ 40.01575 526.5008 0 ] /Next 936 0 R /Parent 933 0 R /Prev 934 0 R /Title (Building Chipsec) +/Dest [ 541 0 R /XYZ 40.01575 237.3008 0 ] /Parent 930 0 R /Prev 934 0 R /Title (Build Errors) >> endobj 936 0 obj << -/Dest [ 541 0 R /XYZ 40.01575 436.1008 0 ] /Next 937 0 R /Parent 933 0 R /Prev 935 0 R /Title (Run CHIPSEC) +/Count 2 /Dest [ 541 0 R /XYZ 40.01575 146.9008 0 ] /First 937 0 R /Last 938 0 R /Next 939 0 R /Parent 917 0 R + /Prev 930 0 R /Title (Building a Bootable USB drive with UEFI Shell \(x64\)) >> endobj 937 0 obj << -/Dest [ 541 0 R /XYZ 40.01575 345.7008 0 ] /Next 938 0 R /Parent 933 0 R /Prev 936 0 R /Title (CHIPSEC Cleanup) +/Dest [ 546 0 R /XYZ 40.01575 669.7008 0 ] /Next 938 0 R /Parent 936 0 R /Title (Installing CHIPSEC) >> endobj 938 0 obj << -/Dest [ 541 0 R /XYZ 40.01575 237.3008 0 ] /Parent 933 0 R /Prev 937 0 R /Title (Build Errors) +/Dest [ 546 0 R /XYZ 40.01575 302.9008 0 ] /Parent 936 0 R /Prev 937 0 R /Title (Run CHIPSEC in UEFI Shell) >> endobj 939 0 obj << -/Count 2 /Dest [ 541 0 R /XYZ 40.01575 146.9008 0 ] /First 940 0 R /Last 941 0 R /Next 942 0 R /Parent 920 0 R - /Prev 933 0 R /Title (Building a Bootable USB drive with UEFI Shell \(x64\)) +/Count 2 /Dest [ 546 0 R /XYZ 40.01575 188.5008 0 ] /First 940 0 R /Last 941 0 R /Parent 917 0 R /Prev 936 0 R + /Title (Creating the Kali Linux Live USB) >> endobj 940 0 obj << -/Dest [ 546 0 R /XYZ 40.01575 669.7008 0 ] /Next 941 0 R /Parent 939 0 R /Title (Installing CHIPSEC) +/Dest [ 546 0 R /XYZ 40.01575 113.7008 0 ] /Next 941 0 R /Parent 939 0 R /Title (Installing CHIPSEC) >> endobj 941 0 obj << -/Dest [ 546 0 R /XYZ 40.01575 302.9008 0 ] /Parent 939 0 R /Prev 940 0 R /Title (Run CHIPSEC in UEFI Shell) +/Dest [ 548 0 R /XYZ 40.01575 510.9008 0 ] /Parent 939 0 R /Prev 940 0 R /Title (Run CHIPSEC) >> endobj 942 0 obj << -/Count 2 /Dest [ 546 0 R /XYZ 40.01575 188.5008 0 ] /First 943 0 R /Last 944 0 R /Parent 920 0 R /Prev 939 0 R - /Title (Creating the Kali Linux Live USB) +/Count 9 /Dest [ 548 0 R /XYZ 40.01575 438.5008 0 ] /First 943 0 R /Last 948 0 R /Next 952 0 R /Parent 912 0 R + /Prev 917 0 R /Title (Using CHIPSEC) >> endobj 943 0 obj << -/Dest [ 546 0 R /XYZ 40.01575 113.7008 0 ] /Next 944 0 R /Parent 942 0 R /Title (Installing CHIPSEC) +/Count 4 /Dest [ 548 0 R /XYZ 40.01575 301.3008 0 ] /First 944 0 R /Last 947 0 R /Next 948 0 R /Parent 942 0 R + /Title (Running CHIPSEC) >> endobj 944 0 obj << -/Dest [ 548 0 R /XYZ 40.01575 510.9008 0 ] /Parent 942 0 R /Prev 943 0 R /Title (Run CHIPSEC) +/Dest [ 549 0 R /XYZ 40.01575 775.7008 0 ] /Next 945 0 R /Parent 943 0 R /Title (Running in Shell) >> endobj 945 0 obj << -/Count 9 /Dest [ 548 0 R /XYZ 40.01575 438.5008 0 ] /First 946 0 R /Last 951 0 R /Next 955 0 R /Parent 915 0 R - /Prev 920 0 R /Title (Using CHIPSEC) +/Dest [ 549 0 R /XYZ 40.01575 613.3008 0 ] /Next 946 0 R /Parent 943 0 R /Prev 944 0 R /Title (Using as a Python Package) >> endobj 946 0 obj << -/Count 4 /Dest [ 548 0 R /XYZ 40.01575 301.3008 0 ] /First 947 0 R /Last 950 0 R /Next 951 0 R /Parent 945 0 R - /Title (Running CHIPSEC) +/Dest [ 550 0 R /XYZ 40.01575 775.7008 0 ] /Next 947 0 R /Parent 943 0 R /Prev 945 0 R /Title (chipsec_main options) >> endobj 947 0 obj << -/Dest [ 549 0 R /XYZ 40.01575 775.7008 0 ] /Next 948 0 R /Parent 946 0 R /Title (Running in Shell) +/Dest [ 550 0 R /XYZ 40.01575 412.7539 0 ] /Parent 943 0 R /Prev 946 0 R /Title (chipsec_util options) >> endobj 948 0 obj << -/Dest [ 549 0 R /XYZ 40.01575 613.3008 0 ] /Next 949 0 R /Parent 946 0 R /Prev 947 0 R /Title (Using as a Python Package) +/Count 3 /Dest [ 550 0 R /XYZ 40.01575 211.1539 0 ] /First 949 0 R /Last 951 0 R /Parent 942 0 R /Prev 943 0 R + /Title (Interpreting results) >> endobj 949 0 obj << -/Dest [ 550 0 R /XYZ 40.01575 775.7008 0 ] /Next 950 0 R /Parent 946 0 R /Prev 948 0 R /Title (chipsec_main options) +/Dest [ 551 0 R /XYZ 40.01575 775.7008 0 ] /Next 950 0 R /Parent 948 0 R /Title (Results) >> endobj 950 0 obj << -/Dest [ 550 0 R /XYZ 40.01575 412.7539 0 ] /Parent 946 0 R /Prev 949 0 R /Title (chipsec_util options) +/Dest [ 551 0 R /XYZ 40.01575 386.9008 0 ] /Next 951 0 R /Parent 948 0 R /Prev 949 0 R /Title (Automated Tests) >> endobj 951 0 obj << -/Count 3 /Dest [ 550 0 R /XYZ 40.01575 211.1539 0 ] /First 952 0 R /Last 954 0 R /Parent 945 0 R /Prev 946 0 R - /Title (Interpreting results) +/Dest [ 555 0 R /XYZ 40.01575 645.7008 0 ] /Parent 948 0 R /Prev 950 0 R /Title (Tools) >> endobj 952 0 obj << -/Dest [ 551 0 R /XYZ 40.01575 775.7008 0 ] /Next 953 0 R /Parent 951 0 R /Title (Results) +/Count 240 /Dest [ 555 0 R /XYZ 40.01575 561.3008 0 ] /First 953 0 R /Last 1192 0 R /Parent 912 0 R /Prev 942 0 R + /Title (Module & Command Development) >> endobj 953 0 obj << -/Dest [ 551 0 R /XYZ 40.01575 386.9008 0 ] /Next 954 0 R /Parent 951 0 R /Prev 952 0 R /Title (Automated Tests) +/Count 158 /Dest [ 555 0 R /XYZ 40.01575 502.1008 0 ] /First 954 0 R /Last 1111 0 R /Next 1112 0 R /Parent 952 0 R + /Title (Architecture Overview) >> endobj 954 0 obj << -/Dest [ 555 0 R /XYZ 40.01575 645.7008 0 ] /Parent 951 0 R /Prev 953 0 R /Title (Tools) +/Dest [ 555 0 R /XYZ 40.01575 163.3008 0 ] /Next 955 0 R /Parent 953 0 R /Title (Core components) >> endobj 955 0 obj << -/Count 240 /Dest [ 555 0 R /XYZ 40.01575 561.3008 0 ] /First 956 0 R /Last 1195 0 R /Parent 915 0 R /Prev 945 0 R - /Title (Module & Command Development) +/Count 152 /Dest [ 556 0 R /XYZ 40.01575 543.7008 0 ] /First 956 0 R /Last 1105 0 R /Next 1108 0 R /Parent 953 0 R + /Prev 954 0 R /Title (Modules & Tools) >> endobj 956 0 obj << -/Count 158 /Dest [ 555 0 R /XYZ 40.01575 502.1008 0 ] /First 957 0 R /Last 1114 0 R /Next 1115 0 R /Parent 955 0 R - /Title (Architecture Overview) +/Count 4 /Dest [ 556 0 R /XYZ 40.01575 471.3008 0 ] /First 957 0 R /Last 957 0 R /Next 961 0 R /Parent 955 0 R + /Title (Platform detection) >> endobj 957 0 obj << -/Dest [ 555 0 R /XYZ 40.01575 163.3008 0 ] /Next 958 0 R /Parent 956 0 R /Title (Core components) +/Count 3 /Dest [ 556 0 R /XYZ 40.01575 419.3008 0 ] /First 958 0 R /Last 960 0 R /Parent 956 0 R /Title (Methods for Platform Detection) >> endobj 958 0 obj << -/Count 152 /Dest [ 556 0 R /XYZ 40.01575 543.7008 0 ] /First 959 0 R /Last 1108 0 R /Next 1111 0 R /Parent 956 0 R - /Prev 957 0 R /Title (Modules & Tools) +/Dest [ 556 0 R /XYZ 40.01575 369.7008 0 ] /Next 959 0 R /Parent 957 0 R /Title (Uses PCI VID and DID to detect processor and PCH) >> endobj 959 0 obj << -/Count 4 /Dest [ 556 0 R /XYZ 40.01575 471.3008 0 ] /First 960 0 R /Last 960 0 R /Next 964 0 R /Parent 958 0 R - /Title (Platform detection) +/Dest [ 556 0 R /XYZ 40.01575 284.1008 0 ] /Next 960 0 R /Parent 957 0 R /Prev 958 0 R /Title (Chip information located in chipsec/chipset.py) >> endobj 960 0 obj << -/Count 3 /Dest [ 556 0 R /XYZ 40.01575 419.3008 0 ] /First 961 0 R /Last 963 0 R /Parent 959 0 R /Title (Methods for Platform Detection) +/Dest [ 556 0 R /XYZ 40.01575 180.5008 0 ] /Parent 957 0 R /Prev 959 0 R /Title (Platform Configuration Options) >> endobj 961 0 obj << -/Dest [ 556 0 R /XYZ 40.01575 369.7008 0 ] /Next 962 0 R /Parent 960 0 R /Title (Uses PCI VID and DID to detect processor and PCH) +/Count 45 /Dest [ 558 0 R /XYZ 40.01575 775.7008 0 ] /First 962 0 R /Last 1006 0 R /Next 1007 0 R /Parent 955 0 R + /Prev 956 0 R /Title (Configuration Files) >> endobj 962 0 obj << -/Dest [ 556 0 R /XYZ 40.01575 284.1008 0 ] /Next 963 0 R /Parent 960 0 R /Prev 961 0 R /Title (Chip information located in chipsec/chipset.py) +/Count 1 /Dest [ 558 0 R /XYZ 40.01575 639.7008 0 ] /First 963 0 R /Last 963 0 R /Next 964 0 R /Parent 961 0 R + /Title (Configuration Files) >> endobj 963 0 obj << -/Dest [ 556 0 R /XYZ 40.01575 180.5008 0 ] /Parent 960 0 R /Prev 962 0 R /Title (Platform Configuration Options) +/Dest [ 558 0 R /XYZ 40.01575 518.1008 0 ] /Parent 962 0 R /Title (Configuraiton File Example) >> endobj 964 0 obj << -/Count 45 /Dest [ 558 0 R /XYZ 40.01575 775.7008 0 ] /First 965 0 R /Last 1009 0 R /Next 1010 0 R /Parent 958 0 R - /Prev 959 0 R /Title (Configuration Files) +/Dest [ 558 0 R /XYZ 40.01575 368.9493 0 ] /Next 965 0 R /Parent 961 0 R /Prev 962 0 R /Title (hsw) >> endobj 965 0 obj << -/Count 1 /Dest [ 558 0 R /XYZ 40.01575 639.7008 0 ] /First 966 0 R /Last 966 0 R /Next 967 0 R /Parent 964 0 R - /Title (Configuration Files) +/Dest [ 558 0 R /XYZ 40.01575 283.3493 0 ] /Next 966 0 R /Parent 961 0 R /Prev 964 0 R /Title (sfdp) >> endobj 966 0 obj << -/Dest [ 558 0 R /XYZ 40.01575 518.1008 0 ] /Parent 965 0 R /Title (Configuraiton File Example) +/Dest [ 558 0 R /XYZ 40.01575 185.7493 0 ] /Next 967 0 R /Parent 961 0 R /Prev 965 0 R /Title (pch_4xxlp) >> endobj 967 0 obj << -/Dest [ 558 0 R /XYZ 40.01575 368.9493 0 ] /Next 968 0 R /Parent 964 0 R /Prev 965 0 R /Title (hsw) +/Dest [ 558 0 R /XYZ 40.01575 100.1493 0 ] /Next 968 0 R /Parent 961 0 R /Prev 966 0 R /Title (glk) >> endobj 968 0 obj << -/Dest [ 558 0 R /XYZ 40.01575 283.3493 0 ] /Next 969 0 R /Parent 964 0 R /Prev 967 0 R /Title (sfdp) +/Dest [ 562 0 R /XYZ 40.01575 708.7008 0 ] /Next 969 0 R /Parent 961 0 R /Prev 967 0 R /Title (icx) >> endobj 969 0 obj << -/Dest [ 558 0 R /XYZ 40.01575 185.7493 0 ] /Next 970 0 R /Parent 964 0 R /Prev 968 0 R /Title (pch_4xxlp) +/Dest [ 562 0 R /XYZ 40.01575 623.1008 0 ] /Next 970 0 R /Parent 961 0 R /Prev 968 0 R /Title (ivt) >> endobj 970 0 obj << -/Dest [ 558 0 R /XYZ 40.01575 100.1493 0 ] /Next 971 0 R /Parent 964 0 R /Prev 969 0 R /Title (glk) +/Dest [ 562 0 R /XYZ 40.01575 537.5008 0 ] /Next 971 0 R /Parent 961 0 R /Prev 969 0 R /Title (pch_2xx) >> endobj 971 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 708.7008 0 ] /Next 972 0 R /Parent 964 0 R /Prev 970 0 R /Title (icx) +/Dest [ 562 0 R /XYZ 40.01575 421.9008 0 ] /Next 972 0 R /Parent 961 0 R /Prev 970 0 R /Title (cht) >> endobj 972 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 623.1008 0 ] /Next 973 0 R /Parent 964 0 R /Prev 971 0 R /Title (ivt) +/Dest [ 562 0 R /XYZ 40.01575 276.3008 0 ] /Next 973 0 R /Parent 961 0 R /Prev 971 0 R /Title (skx) >> endobj 973 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 537.5008 0 ] /Next 974 0 R /Parent 964 0 R /Prev 972 0 R /Title (pch_2xx) +/Dest [ 562 0 R /XYZ 40.01575 190.7008 0 ] /Next 974 0 R /Parent 961 0 R /Prev 972 0 R /Title (pch_5xxh) >> endobj 974 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 421.9008 0 ] /Next 975 0 R /Parent 964 0 R /Prev 973 0 R /Title (cht) +/Dest [ 562 0 R /XYZ 40.01575 105.1008 0 ] /Next 975 0 R /Parent 961 0 R /Prev 973 0 R /Title (jkt) >> endobj 975 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 276.3008 0 ] /Next 976 0 R /Parent 964 0 R /Prev 974 0 R /Title (skx) +/Dest [ 567 0 R /XYZ 40.01575 723.7008 0 ] /Next 976 0 R /Parent 961 0 R /Prev 974 0 R /Title (tpm12) >> endobj 976 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 190.7008 0 ] /Next 977 0 R /Parent 964 0 R /Prev 975 0 R /Title (pch_5xxh) +/Dest [ 567 0 R /XYZ 40.01575 518.1008 0 ] /Next 977 0 R /Parent 961 0 R /Prev 975 0 R /Title (apl) >> endobj 977 0 obj << -/Dest [ 562 0 R /XYZ 40.01575 105.1008 0 ] /Next 978 0 R /Parent 964 0 R /Prev 976 0 R /Title (jkt) +/Dest [ 567 0 R /XYZ 40.01575 432.5008 0 ] /Next 978 0 R /Parent 961 0 R /Prev 976 0 R /Title (pch_495) >> endobj 978 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 723.7008 0 ] /Next 979 0 R /Parent 964 0 R /Prev 977 0 R /Title (tpm12) +/Dest [ 567 0 R /XYZ 40.01575 346.9008 0 ] /Next 979 0 R /Parent 961 0 R /Prev 977 0 R /Title (snb) >> endobj 979 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 518.1008 0 ] /Next 980 0 R /Parent 964 0 R /Prev 978 0 R /Title (apl) +/Dest [ 567 0 R /XYZ 40.01575 261.3008 0 ] /Next 980 0 R /Parent 961 0 R /Prev 978 0 R /Title (pch_3xx) >> endobj 980 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 432.5008 0 ] /Next 981 0 R /Parent 964 0 R /Prev 979 0 R /Title (pch_495) +/Dest [ 567 0 R /XYZ 40.01575 151.7008 0 ] /Next 981 0 R /Parent 961 0 R /Prev 979 0 R /Title (pch_3xxop) >> endobj 981 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 346.9008 0 ] /Next 982 0 R /Parent 964 0 R /Prev 980 0 R /Title (snb) +/Dest [ 570 0 R /XYZ 40.01575 775.7008 0 ] /Next 982 0 R /Parent 961 0 R /Prev 980 0 R /Title (pch_5xxlp) >> endobj 982 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 261.3008 0 ] /Next 983 0 R /Parent 964 0 R /Prev 981 0 R /Title (pch_3xx) +/Dest [ 570 0 R /XYZ 40.01575 690.1008 0 ] /Next 983 0 R /Parent 961 0 R /Prev 981 0 R /Title (bdx) >> endobj 983 0 obj << -/Dest [ 567 0 R /XYZ 40.01575 151.7008 0 ] /Next 984 0 R /Parent 964 0 R /Prev 982 0 R /Title (pch_3xxop) +/Dest [ 570 0 R /XYZ 40.01575 556.5008 0 ] /Next 984 0 R /Parent 961 0 R /Prev 982 0 R /Title (cml) >> endobj 984 0 obj << -/Dest [ 570 0 R /XYZ 40.01575 775.7008 0 ] /Next 985 0 R /Parent 964 0 R /Prev 983 0 R /Title (pch_5xxlp) +/Dest [ 570 0 R /XYZ 40.01575 470.9008 0 ] /Next 985 0 R /Parent 961 0 R /Prev 983 0 R /Title (skl) >> endobj 985 0 obj << -/Dest [ 570 0 R /XYZ 40.01575 690.1008 0 ] /Next 986 0 R /Parent 964 0 R /Prev 984 0 R /Title (bdx) +/Dest [ 570 0 R /XYZ 40.01575 277.3008 0 ] /Next 986 0 R /Parent 961 0 R /Prev 984 0 R /Title (tglu) >> endobj 986 0 obj << -/Dest [ 570 0 R /XYZ 40.01575 556.5008 0 ] /Next 987 0 R /Parent 964 0 R /Prev 985 0 R /Title (cml) +/Dest [ 574 0 R /XYZ 40.01575 775.7008 0 ] /Next 987 0 R /Parent 961 0 R /Prev 985 0 R /Title (hsx) >> endobj 987 0 obj << -/Dest [ 570 0 R /XYZ 40.01575 470.9008 0 ] /Next 988 0 R /Parent 964 0 R /Prev 986 0 R /Title (skl) +/Dest [ 574 0 R /XYZ 40.01575 642.1008 0 ] /Next 988 0 R /Parent 961 0 R /Prev 986 0 R /Title (qrk) >> endobj 988 0 obj << -/Dest [ 570 0 R /XYZ 40.01575 277.3008 0 ] /Next 989 0 R /Parent 964 0 R /Prev 987 0 R /Title (tglu) +/Dest [ 574 0 R /XYZ 40.01575 556.5008 0 ] /Next 989 0 R /Parent 961 0 R /Prev 987 0 R /Title (pch_4xx) >> endobj 989 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 775.7008 0 ] /Next 990 0 R /Parent 964 0 R /Prev 988 0 R /Title (hsx) +/Dest [ 574 0 R /XYZ 40.01575 470.9008 0 ] /Next 990 0 R /Parent 961 0 R /Prev 988 0 R /Title (common) >> endobj 990 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 642.1008 0 ] /Next 991 0 R /Parent 964 0 R /Prev 989 0 R /Title (qrk) +/Dest [ 574 0 R /XYZ 40.01575 385.3008 0 ] /Next 991 0 R /Parent 961 0 R /Prev 989 0 R /Title (rkl) >> endobj 991 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 556.5008 0 ] /Next 992 0 R /Parent 964 0 R /Prev 990 0 R /Title (pch_4xx) +/Dest [ 574 0 R /XYZ 40.01575 179.7008 0 ] /Next 992 0 R /Parent 961 0 R /Prev 990 0 R /Title (pch_3xxlp) >> endobj 992 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 470.9008 0 ] /Next 993 0 R /Parent 964 0 R /Prev 991 0 R /Title (common) +/Dest [ 581 0 R /XYZ 40.01575 775.7008 0 ] /Next 993 0 R /Parent 961 0 R /Prev 991 0 R /Title (whl) >> endobj 993 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 385.3008 0 ] /Next 994 0 R /Parent 964 0 R /Prev 992 0 R /Title (rkl) +/Dest [ 581 0 R /XYZ 40.01575 648.1008 0 ] /Next 994 0 R /Parent 961 0 R /Prev 992 0 R /Title (bdw) >> endobj 994 0 obj << -/Dest [ 574 0 R /XYZ 40.01575 179.7008 0 ] /Next 995 0 R /Parent 964 0 R /Prev 993 0 R /Title (pch_3xxlp) +/Dest [ 581 0 R /XYZ 40.01575 562.5008 0 ] /Next 995 0 R /Parent 961 0 R /Prev 993 0 R /Title (byt) >> endobj 995 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 775.7008 0 ] /Next 996 0 R /Parent 964 0 R /Prev 994 0 R /Title (whl) +/Dest [ 581 0 R /XYZ 40.01575 446.9008 0 ] /Next 996 0 R /Parent 961 0 R /Prev 994 0 R /Title (avn) >> endobj 996 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 648.1008 0 ] /Next 997 0 R /Parent 964 0 R /Prev 995 0 R /Title (bdw) +/Dest [ 581 0 R /XYZ 40.01575 331.3008 0 ] /Next 997 0 R /Parent 961 0 R /Prev 995 0 R /Title (pch_c620) >> endobj 997 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 562.5008 0 ] /Next 998 0 R /Parent 964 0 R /Prev 996 0 R /Title (byt) +/Dest [ 581 0 R /XYZ 40.01575 215.7008 0 ] /Next 998 0 R /Parent 961 0 R /Prev 996 0 R /Title (dnv) >> endobj 998 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 446.9008 0 ] /Next 999 0 R /Parent 964 0 R /Prev 997 0 R /Title (avn) +/Dest [ 581 0 R /XYZ 40.01575 100.1008 0 ] /Next 999 0 R /Parent 961 0 R /Prev 997 0 R /Title (icl) >> endobj 999 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 331.3008 0 ] /Next 1000 0 R /Parent 964 0 R /Prev 998 0 R /Title (pch_c620) +/Dest [ 586 0 R /XYZ 40.01575 723.7008 0 ] /Next 1000 0 R /Parent 961 0 R /Prev 998 0 R /Title (pch_c60x) >> endobj 1000 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 215.7008 0 ] /Next 1001 0 R /Parent 964 0 R /Prev 999 0 R /Title (dnv) +/Dest [ 586 0 R /XYZ 40.01575 601.1008 0 ] /Next 1001 0 R /Parent 961 0 R /Prev 999 0 R /Title (kbl) >> endobj 1001 0 obj << -/Dest [ 581 0 R /XYZ 40.01575 100.1008 0 ] /Next 1002 0 R /Parent 964 0 R /Prev 1000 0 R /Title (icl) +/Dest [ 586 0 R /XYZ 40.01575 461.5008 0 ] /Next 1002 0 R /Parent 961 0 R /Prev 1000 0 R /Title (iommu) >> endobj 1002 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 723.7008 0 ] /Next 1003 0 R /Parent 964 0 R /Prev 1001 0 R /Title (pch_c60x) +/Dest [ 586 0 R /XYZ 40.01575 345.9008 0 ] /Next 1003 0 R /Parent 961 0 R /Prev 1001 0 R /Title (ivb) >> endobj 1003 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 601.1008 0 ] /Next 1004 0 R /Parent 964 0 R /Prev 1002 0 R /Title (kbl) +/Dest [ 586 0 R /XYZ 40.01575 260.3008 0 ] /Next 1004 0 R /Parent 961 0 R /Prev 1002 0 R /Title (pch_c61x) >> endobj 1004 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 461.5008 0 ] /Next 1005 0 R /Parent 964 0 R /Prev 1003 0 R /Title (iommu) +/Dest [ 586 0 R /XYZ 40.01575 149.7008 0 ] /Next 1005 0 R /Parent 961 0 R /Prev 1003 0 R /Title (pch_1xx) >> endobj 1005 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 345.9008 0 ] /Next 1006 0 R /Parent 964 0 R /Prev 1004 0 R /Title (ivb) +/Dest [ 590 0 R /XYZ 40.01575 591.7008 0 ] /Next 1006 0 R /Parent 961 0 R /Prev 1004 0 R /Title (cfl) >> endobj 1006 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 260.3008 0 ] /Next 1007 0 R /Parent 964 0 R /Prev 1005 0 R /Title (pch_c61x) +/Dest [ 590 0 R /XYZ 40.01575 476.1008 0 ] /Parent 961 0 R /Prev 1005 0 R /Title (pch_4xxh) >> endobj 1007 0 obj << -/Dest [ 586 0 R /XYZ 40.01575 149.7008 0 ] /Next 1008 0 R /Parent 964 0 R /Prev 1006 0 R /Title (pch_1xx) +/Count 32 /Dest [ 590 0 R /XYZ 40.01575 390.5008 0 ] /First 1008 0 R /Last 1008 0 R /Next 1040 0 R /Parent 955 0 R + /Prev 961 0 R /Title (Commands) >> endobj 1008 0 obj << -/Dest [ 590 0 R /XYZ 40.01575 591.7008 0 ] /Next 1009 0 R /Parent 964 0 R /Prev 1007 0 R /Title (cfl) +/Count 31 /Dest [ 592 0 R /XYZ 40.01575 775.7008 0 ] /First 1009 0 R /Last 1039 0 R /Parent 1007 0 R /Title (utilcmd package) >> endobj 1009 0 obj << -/Dest [ 590 0 R /XYZ 40.01575 476.1008 0 ] /Parent 964 0 R /Prev 1008 0 R /Title (pch_4xxh) +/Dest [ 592 0 R /XYZ 40.01575 726.1008 0 ] /Next 1010 0 R /Parent 1008 0 R /Title (acpi_cmd module) >> endobj 1010 0 obj << -/Count 32 /Dest [ 590 0 R /XYZ 40.01575 390.5008 0 ] /First 1011 0 R /Last 1011 0 R /Next 1043 0 R /Parent 958 0 R - /Prev 964 0 R /Title (Commands) +/Dest [ 592 0 R /XYZ 40.01575 436.9008 0 ] /Next 1011 0 R /Parent 1008 0 R /Prev 1009 0 R /Title (chipset_cmd module) >> endobj 1011 0 obj << -/Count 31 /Dest [ 592 0 R /XYZ 40.01575 775.7008 0 ] /First 1012 0 R /Last 1042 0 R /Parent 1010 0 R /Title (utilcmd package) +/Dest [ 592 0 R /XYZ 40.01575 253.9008 0 ] /Next 1012 0 R /Parent 1008 0 R /Prev 1010 0 R /Title (cmos_cmd module) >> endobj 1012 0 obj << -/Dest [ 592 0 R /XYZ 40.01575 726.1008 0 ] /Next 1013 0 R /Parent 1011 0 R /Title (acpi_cmd module) +/Dest [ 593 0 R /XYZ 40.01575 603.7008 0 ] /Next 1013 0 R /Parent 1008 0 R /Prev 1011 0 R /Title (config_cmd module) >> endobj 1013 0 obj << -/Dest [ 592 0 R /XYZ 40.01575 436.9008 0 ] /Next 1014 0 R /Parent 1011 0 R /Prev 1012 0 R /Title (chipset_cmd module) +/Dest [ 593 0 R /XYZ 40.01575 168.1008 0 ] /Next 1014 0 R /Parent 1008 0 R /Prev 1012 0 R /Title (cpu_cmd module) >> endobj 1014 0 obj << -/Dest [ 592 0 R /XYZ 40.01575 253.9008 0 ] /Next 1015 0 R /Parent 1011 0 R /Prev 1013 0 R /Title (cmos_cmd module) +/Dest [ 594 0 R /XYZ 40.01575 449.3008 0 ] /Next 1015 0 R /Parent 1008 0 R /Prev 1013 0 R /Title (decode_cmd module) >> endobj 1015 0 obj << -/Dest [ 593 0 R /XYZ 40.01575 603.7008 0 ] /Next 1016 0 R /Parent 1011 0 R /Prev 1014 0 R /Title (config_cmd module) +/Dest [ 595 0 R /XYZ 40.01575 775.7008 0 ] /Next 1016 0 R /Parent 1008 0 R /Prev 1014 0 R /Title (deltas_cmd module) >> endobj 1016 0 obj << -/Dest [ 593 0 R /XYZ 40.01575 168.1008 0 ] /Next 1017 0 R /Parent 1011 0 R /Prev 1015 0 R /Title (cpu_cmd module) +/Dest [ 595 0 R /XYZ 40.01575 587.7008 0 ] /Next 1017 0 R /Parent 1008 0 R /Prev 1015 0 R /Title (desc_cmd module) >> endobj 1017 0 obj << -/Dest [ 594 0 R /XYZ 40.01575 449.3008 0 ] /Next 1018 0 R /Parent 1011 0 R /Prev 1016 0 R /Title (decode_cmd module) +/Dest [ 596 0 R /XYZ 40.01575 775.7008 0 ] /Next 1018 0 R /Parent 1008 0 R /Prev 1016 0 R /Title (ec_cmd module) >> endobj 1018 0 obj << -/Dest [ 595 0 R /XYZ 40.01575 775.7008 0 ] /Next 1019 0 R /Parent 1011 0 R /Prev 1017 0 R /Title (deltas_cmd module) +/Dest [ 596 0 R /XYZ 40.01575 378.5008 0 ] /Next 1019 0 R /Parent 1008 0 R /Prev 1017 0 R /Title (igd_cmd module) >> endobj 1019 0 obj << -/Dest [ 595 0 R /XYZ 40.01575 587.7008 0 ] /Next 1020 0 R /Parent 1011 0 R /Prev 1018 0 R /Title (desc_cmd module) +/Dest [ 596 0 R /XYZ 40.01575 89.30079 0 ] /Next 1020 0 R /Parent 1008 0 R /Prev 1018 0 R /Title (interrupts_cmd module) >> endobj 1020 0 obj << -/Dest [ 596 0 R /XYZ 40.01575 775.7008 0 ] /Next 1021 0 R /Parent 1011 0 R /Prev 1019 0 R /Title (ec_cmd module) +/Dest [ 597 0 R /XYZ 40.01575 341.5657 0 ] /Next 1021 0 R /Parent 1008 0 R /Prev 1019 0 R /Title (io_cmd module) >> endobj 1021 0 obj << -/Dest [ 596 0 R /XYZ 40.01575 378.5008 0 ] /Next 1022 0 R /Parent 1011 0 R /Prev 1020 0 R /Title (igd_cmd module) +/Dest [ 598 0 R /XYZ 40.01575 723.7008 0 ] /Next 1022 0 R /Parent 1008 0 R /Prev 1020 0 R /Title (iommu_cmd module) >> endobj 1022 0 obj << -/Dest [ 596 0 R /XYZ 40.01575 89.30079 0 ] /Next 1023 0 R /Parent 1011 0 R /Prev 1021 0 R /Title (interrupts_cmd module) +/Dest [ 598 0 R /XYZ 40.01575 266.5008 0 ] /Next 1023 0 R /Parent 1008 0 R /Prev 1021 0 R /Title (mem_cmd module) >> endobj 1023 0 obj << -/Dest [ 597 0 R /XYZ 40.01575 341.5657 0 ] /Next 1024 0 R /Parent 1011 0 R /Prev 1022 0 R /Title (io_cmd module) +/Dest [ 599 0 R /XYZ 40.01575 423.3008 0 ] /Next 1024 0 R /Parent 1008 0 R /Prev 1022 0 R /Title (mmcfg_base_cmd module) >> endobj 1024 0 obj << -/Dest [ 598 0 R /XYZ 40.01575 723.7008 0 ] /Next 1025 0 R /Parent 1011 0 R /Prev 1023 0 R /Title (iommu_cmd module) +/Dest [ 599 0 R /XYZ 40.01575 210.9008 0 ] /Next 1025 0 R /Parent 1008 0 R /Prev 1023 0 R /Title (mmcfg_cmd module) >> endobj 1025 0 obj << -/Dest [ 598 0 R /XYZ 40.01575 266.5008 0 ] /Next 1026 0 R /Parent 1011 0 R /Prev 1024 0 R /Title (mem_cmd module) +/Dest [ 600 0 R /XYZ 40.01575 653.7008 0 ] /Next 1026 0 R /Parent 1008 0 R /Prev 1024 0 R /Title (mmio_cmd module) >> endobj 1026 0 obj << -/Dest [ 599 0 R /XYZ 40.01575 423.3008 0 ] /Next 1027 0 R /Parent 1011 0 R /Prev 1025 0 R /Title (mmcfg_base_cmd module) +/Dest [ 600 0 R /XYZ 40.01575 299.7008 0 ] /Next 1027 0 R /Parent 1008 0 R /Prev 1025 0 R /Title (msgbus_cmd module) >> endobj 1027 0 obj << -/Dest [ 599 0 R /XYZ 40.01575 210.9008 0 ] /Next 1028 0 R /Parent 1011 0 R /Prev 1026 0 R /Title (mmcfg_cmd module) +/Dest [ 601 0 R /XYZ 40.01575 579.7008 0 ] /Next 1028 0 R /Parent 1008 0 R /Prev 1026 0 R /Title (msr_cmd module) >> endobj 1028 0 obj << -/Dest [ 600 0 R /XYZ 40.01575 653.7008 0 ] /Next 1029 0 R /Parent 1011 0 R /Prev 1027 0 R /Title (mmio_cmd module) +/Dest [ 601 0 R /XYZ 40.01575 348.1008 0 ] /Next 1029 0 R /Parent 1008 0 R /Prev 1027 0 R /Title (pci_cmd module) >> endobj 1029 0 obj << -/Dest [ 600 0 R /XYZ 40.01575 299.7008 0 ] /Next 1030 0 R /Parent 1011 0 R /Prev 1028 0 R /Title (msgbus_cmd module) +/Dest [ 602 0 R /XYZ 40.01575 555.7008 0 ] /Next 1030 0 R /Parent 1008 0 R /Prev 1028 0 R /Title (reg_cmd module) >> endobj 1030 0 obj << -/Dest [ 601 0 R /XYZ 40.01575 579.7008 0 ] /Next 1031 0 R /Parent 1011 0 R /Prev 1029 0 R /Title (msr_cmd module) +/Dest [ 602 0 R /XYZ 40.01575 105.7008 0 ] /Next 1031 0 R /Parent 1008 0 R /Prev 1029 0 R /Title (smbios_cmd module) >> endobj 1031 0 obj << -/Dest [ 601 0 R /XYZ 40.01575 348.1008 0 ] /Next 1032 0 R /Parent 1011 0 R /Prev 1030 0 R /Title (pci_cmd module) +/Dest [ 603 0 R /XYZ 40.01575 535.7008 0 ] /Next 1032 0 R /Parent 1008 0 R /Prev 1030 0 R /Title (smbus_cmd module) >> endobj 1032 0 obj << -/Dest [ 602 0 R /XYZ 40.01575 555.7008 0 ] /Next 1033 0 R /Parent 1011 0 R /Prev 1031 0 R /Title (reg_cmd module) +/Dest [ 603 0 R /XYZ 40.01575 277.7008 0 ] /Next 1033 0 R /Parent 1008 0 R /Prev 1031 0 R /Title (spd_cmd module) >> endobj 1033 0 obj << -/Dest [ 602 0 R /XYZ 40.01575 105.7008 0 ] /Next 1034 0 R /Parent 1011 0 R /Prev 1032 0 R /Title (smbios_cmd module) +/Dest [ 604 0 R /XYZ 40.01575 603.7008 0 ] /Next 1034 0 R /Parent 1008 0 R /Prev 1032 0 R /Title (spi_cmd module) >> endobj 1034 0 obj << -/Dest [ 603 0 R /XYZ 40.01575 535.7008 0 ] /Next 1035 0 R /Parent 1011 0 R /Prev 1033 0 R /Title (smbus_cmd module) +/Dest [ 605 0 R /XYZ 40.01575 699.7008 0 ] /Next 1035 0 R /Parent 1008 0 R /Prev 1033 0 R /Title (spidesc_cmd module) >> endobj 1035 0 obj << -/Dest [ 603 0 R /XYZ 40.01575 277.7008 0 ] /Next 1036 0 R /Parent 1011 0 R /Prev 1034 0 R /Title (spd_cmd module) +/Dest [ 605 0 R /XYZ 40.01575 499.3008 0 ] /Next 1036 0 R /Parent 1008 0 R /Prev 1034 0 R /Title (tpm_cmd module) >> endobj 1036 0 obj << -/Dest [ 604 0 R /XYZ 40.01575 603.7008 0 ] /Next 1037 0 R /Parent 1011 0 R /Prev 1035 0 R /Title (spi_cmd module) +/Dest [ 605 0 R /XYZ 40.01575 118.9008 0 ] /Next 1037 0 R /Parent 1008 0 R /Prev 1035 0 R /Title (ucode_cmd module) >> endobj 1037 0 obj << -/Dest [ 605 0 R /XYZ 40.01575 699.7008 0 ] /Next 1038 0 R /Parent 1011 0 R /Prev 1036 0 R /Title (spidesc_cmd module) +/Dest [ 606 0 R /XYZ 40.01575 535.7008 0 ] /Next 1038 0 R /Parent 1008 0 R /Prev 1036 0 R /Title (uefi_cmd module) >> endobj 1038 0 obj << -/Dest [ 605 0 R /XYZ 40.01575 499.3008 0 ] /Next 1039 0 R /Parent 1011 0 R /Prev 1037 0 R /Title (tpm_cmd module) +/Dest [ 607 0 R /XYZ 40.01575 435.7008 0 ] /Next 1039 0 R /Parent 1008 0 R /Prev 1037 0 R /Title (vmem_cmd module) >> endobj 1039 0 obj << -/Dest [ 605 0 R /XYZ 40.01575 118.9008 0 ] /Next 1040 0 R /Parent 1011 0 R /Prev 1038 0 R /Title (ucode_cmd module) +/Dest [ 609 0 R /XYZ 40.01575 627.7008 0 ] /Parent 1008 0 R /Prev 1038 0 R /Title (vmm_cmd module) >> endobj 1040 0 obj << -/Dest [ 606 0 R /XYZ 40.01575 535.7008 0 ] /Next 1041 0 R /Parent 1011 0 R /Prev 1039 0 R /Title (uefi_cmd module) +/Count 38 /Dest [ 609 0 R /XYZ 40.01575 297.7008 0 ] /First 1041 0 R /Last 1041 0 R /Next 1079 0 R /Parent 955 0 R + /Prev 1007 0 R /Title (HAL \(Hardware Abstraction Layer\)) >> endobj 1041 0 obj << -/Dest [ 607 0 R /XYZ 40.01575 435.7008 0 ] /Next 1042 0 R /Parent 1011 0 R /Prev 1040 0 R /Title (vmem_cmd module) +/Count 37 /Dest [ 609 0 R /XYZ 40.01575 227.7008 0 ] /First 1042 0 R /Last 1078 0 R /Parent 1040 0 R /Title (hal package) >> endobj 1042 0 obj << -/Dest [ 609 0 R /XYZ 40.01575 627.7008 0 ] /Parent 1011 0 R /Prev 1041 0 R /Title (vmm_cmd module) +/Dest [ 609 0 R /XYZ 40.01575 178.1008 0 ] /Next 1043 0 R /Parent 1041 0 R /Title (acpi module) >> endobj 1043 0 obj << -/Count 38 /Dest [ 609 0 R /XYZ 40.01575 297.7008 0 ] /First 1044 0 R /Last 1044 0 R /Next 1082 0 R /Parent 958 0 R - /Prev 1010 0 R /Title (HAL \(Hardware Abstraction Layer\)) +/Dest [ 616 0 R /XYZ 40.01575 423.7008 0 ] /Next 1044 0 R /Parent 1041 0 R /Prev 1042 0 R /Title (acpi_tables module) >> endobj 1044 0 obj << -/Count 37 /Dest [ 609 0 R /XYZ 40.01575 227.7008 0 ] /First 1045 0 R /Last 1081 0 R /Parent 1043 0 R /Title (hal package) +/Dest [ 653 0 R /XYZ 40.01575 315.7008 0 ] /Next 1045 0 R /Parent 1041 0 R /Prev 1043 0 R /Title (cmos module) >> endobj 1045 0 obj << -/Dest [ 609 0 R /XYZ 40.01575 178.1008 0 ] /Next 1046 0 R /Parent 1044 0 R /Title (acpi module) +/Dest [ 655 0 R /XYZ 40.01575 651.7008 0 ] /Next 1046 0 R /Parent 1041 0 R /Prev 1044 0 R /Title (cpu module) >> endobj 1046 0 obj << -/Dest [ 615 0 R /XYZ 40.01575 387.7008 0 ] /Next 1047 0 R /Parent 1044 0 R /Prev 1045 0 R /Title (acpi_tables module) +/Dest [ 655 0 R /XYZ 40.01575 116.1008 0 ] /Next 1047 0 R /Parent 1041 0 R /Prev 1045 0 R /Title (cpuid module) >> endobj 1047 0 obj << -/Dest [ 653 0 R /XYZ 40.01575 279.7008 0 ] /Next 1048 0 R /Parent 1044 0 R /Prev 1046 0 R /Title (cmos module) +/Dest [ 658 0 R /XYZ 40.01575 656.3008 0 ] /Next 1048 0 R /Parent 1041 0 R /Prev 1046 0 R /Title (ec module) >> endobj 1048 0 obj << -/Dest [ 655 0 R /XYZ 40.01575 555.7008 0 ] /Next 1049 0 R /Parent 1044 0 R /Prev 1047 0 R /Title (cpu module) +/Dest [ 658 0 R /XYZ 40.01575 169.5008 0 ] /Next 1049 0 R /Parent 1041 0 R /Prev 1047 0 R /Title (hal_base module) >> endobj 1049 0 obj << -/Dest [ 658 0 R /XYZ 40.01575 687.7008 0 ] /Next 1050 0 R /Parent 1044 0 R /Prev 1048 0 R /Title (cpuid module) +/Dest [ 661 0 R /XYZ 40.01575 775.7008 0 ] /Next 1050 0 R /Parent 1041 0 R /Prev 1048 0 R /Title (igd module) >> endobj 1050 0 obj << -/Dest [ 658 0 R /XYZ 40.01575 488.7008 0 ] /Next 1051 0 R /Parent 1044 0 R /Prev 1049 0 R /Title (ec module) +/Dest [ 661 0 R /XYZ 40.01575 204.7008 0 ] /Next 1051 0 R /Parent 1041 0 R /Prev 1049 0 R /Title (interrupts module) >> endobj 1051 0 obj << -/Dest [ 660 0 R /XYZ 40.01575 699.7008 0 ] /Next 1052 0 R /Parent 1044 0 R /Prev 1050 0 R /Title (hal_base module) +/Dest [ 663 0 R /XYZ 40.01575 603.7008 0 ] /Next 1052 0 R /Parent 1041 0 R /Prev 1050 0 R /Title (io module) >> endobj 1052 0 obj << -/Dest [ 660 0 R /XYZ 40.01575 596.1008 0 ] /Next 1053 0 R /Parent 1044 0 R /Prev 1051 0 R /Title (igd module) +/Dest [ 663 0 R /XYZ 40.01575 224.7008 0 ] /Next 1053 0 R /Parent 1041 0 R /Prev 1051 0 R /Title (iobar module) >> endobj 1053 0 obj << -/Dest [ 662 0 R /XYZ 40.01575 687.7008 0 ] /Next 1054 0 R /Parent 1044 0 R /Prev 1052 0 R /Title (interrupts module) +/Dest [ 665 0 R /XYZ 40.01575 579.7008 0 ] /Next 1054 0 R /Parent 1041 0 R /Prev 1052 0 R /Title (iommu module) >> endobj 1054 0 obj << -/Dest [ 662 0 R /XYZ 40.01575 371.1008 0 ] /Next 1055 0 R /Parent 1044 0 R /Prev 1053 0 R /Title (io module) +/Dest [ 665 0 R /XYZ 40.01575 308.1008 0 ] /Next 1055 0 R /Parent 1041 0 R /Prev 1053 0 R /Title (mmio module) >> endobj 1055 0 obj << -/Dest [ 665 0 R /XYZ 40.01575 663.7008 0 ] /Next 1056 0 R /Parent 1044 0 R /Prev 1054 0 R /Title (iobar module) +/Dest [ 667 0 R /XYZ 40.01575 133.1008 0 ] /Next 1056 0 R /Parent 1041 0 R /Prev 1054 0 R /Title (msgbus module) >> endobj 1056 0 obj << -/Dest [ 665 0 R /XYZ 40.01575 231.9008 0 ] /Next 1057 0 R /Parent 1044 0 R /Prev 1055 0 R /Title (iommu module) +/Dest [ 671 0 R /XYZ 40.01575 387.7008 0 ] /Next 1057 0 R /Parent 1041 0 R /Prev 1055 0 R /Title (msr module) >> endobj 1057 0 obj << -/Dest [ 667 0 R /XYZ 40.01575 639.7008 0 ] /Next 1058 0 R /Parent 1044 0 R /Prev 1056 0 R /Title (mmio module) +/Dest [ 675 0 R /XYZ 40.01575 579.7008 0 ] /Next 1058 0 R /Parent 1041 0 R /Prev 1056 0 R /Title (paging module) >> endobj 1058 0 obj << -/Dest [ 669 0 R /XYZ 40.01575 483.7008 0 ] /Next 1059 0 R /Parent 1044 0 R /Prev 1057 0 R /Title (msgbus module) +/Dest [ 684 0 R /XYZ 40.01575 399.7008 0 ] /Next 1059 0 R /Parent 1041 0 R /Prev 1057 0 R /Title (pci module) >> endobj 1059 0 obj << -/Dest [ 672 0 R /XYZ 40.01575 711.7008 0 ] /Next 1060 0 R /Parent 1044 0 R /Prev 1058 0 R /Title (msr module) +/Dest [ 687 0 R /XYZ 40.01575 243.7008 0 ] /Next 1060 0 R /Parent 1041 0 R /Prev 1058 0 R /Title (pcidb module) >> endobj 1060 0 obj << -/Dest [ 672 0 R /XYZ 40.01575 147.9008 0 ] /Next 1061 0 R /Parent 1044 0 R /Prev 1059 0 R /Title (paging module) +/Dest [ 690 0 R /XYZ 40.01575 775.7008 0 ] /Next 1061 0 R /Parent 1041 0 R /Prev 1059 0 R /Title (physmem module) >> endobj 1061 0 obj << -/Dest [ 685 0 R /XYZ 40.01575 627.7008 0 ] /Next 1062 0 R /Parent 1044 0 R /Prev 1060 0 R /Title (pci module) +/Dest [ 690 0 R /XYZ 40.01575 295.9008 0 ] /Next 1062 0 R /Parent 1041 0 R /Prev 1060 0 R /Title (smbios module) >> endobj 1062 0 obj << -/Dest [ 689 0 R /XYZ 40.01575 387.7008 0 ] /Next 1063 0 R /Parent 1044 0 R /Prev 1061 0 R /Title (pcidb module) +/Dest [ 695 0 R /XYZ 40.01575 507.7008 0 ] /Next 1063 0 R /Parent 1041 0 R /Prev 1061 0 R /Title (smbus module) >> endobj 1063 0 obj << -/Dest [ 689 0 R /XYZ 40.01575 209.3008 0 ] /Next 1064 0 R /Parent 1044 0 R /Prev 1062 0 R /Title (physmem module) +/Dest [ 695 0 R /XYZ 40.01575 116.1008 0 ] /Next 1064 0 R /Parent 1041 0 R /Prev 1062 0 R /Title (spd module) >> endobj 1064 0 obj << -/Dest [ 692 0 R /XYZ 40.01575 363.7008 0 ] /Next 1065 0 R /Parent 1044 0 R /Prev 1063 0 R /Title (smbios module) +/Dest [ 708 0 R /XYZ 40.01575 123.7008 0 ] /Next 1065 0 R /Parent 1041 0 R /Prev 1063 0 R /Title (spi module) >> endobj 1065 0 obj << -/Dest [ 700 0 R /XYZ 40.01575 567.7008 0 ] /Next 1066 0 R /Parent 1044 0 R /Prev 1064 0 R /Title (smbus module) +/Dest [ 711 0 R /XYZ 40.01575 579.7008 0 ] /Next 1066 0 R /Parent 1041 0 R /Prev 1064 0 R /Title (spi_descriptor module) >> endobj 1066 0 obj << -/Dest [ 700 0 R /XYZ 40.01575 176.1008 0 ] /Next 1067 0 R /Parent 1044 0 R /Prev 1065 0 R /Title (spd module) +/Dest [ 711 0 R /XYZ 40.01575 371.1008 0 ] /Next 1067 0 R /Parent 1041 0 R /Prev 1065 0 R /Title (spi_jedec_ids module) >> endobj 1067 0 obj << -/Dest [ 709 0 R /XYZ 40.01575 171.7008 0 ] /Next 1068 0 R /Parent 1044 0 R /Prev 1066 0 R /Title (spi module) +/Dest [ 711 0 R /XYZ 40.01575 195.5008 0 ] /Next 1068 0 R /Parent 1041 0 R /Prev 1066 0 R /Title (spi_uefi module) >> endobj 1068 0 obj << -/Dest [ 712 0 R /XYZ 40.01575 579.7008 0 ] /Next 1069 0 R /Parent 1044 0 R /Prev 1067 0 R /Title (spi_descriptor module) +/Dest [ 712 0 R /XYZ 40.01575 94.50079 0 ] /Next 1069 0 R /Parent 1041 0 R /Prev 1067 0 R /Title (tpm module) >> endobj 1069 0 obj << -/Dest [ 712 0 R /XYZ 40.01575 371.1008 0 ] /Next 1070 0 R /Parent 1044 0 R /Prev 1068 0 R /Title (spi_jedec_ids module) +/Dest [ 716 0 R /XYZ 40.01575 351.7008 0 ] /Next 1070 0 R /Parent 1041 0 R /Prev 1068 0 R /Title (tpm12_commands module) >> endobj 1070 0 obj << -/Dest [ 712 0 R /XYZ 40.01575 195.5008 0 ] /Next 1071 0 R /Parent 1044 0 R /Prev 1069 0 R /Title (spi_uefi module) +/Dest [ 724 0 R /XYZ 40.01575 699.7008 0 ] /Next 1071 0 R /Parent 1041 0 R /Prev 1069 0 R /Title (tpm_eventlog module) >> endobj 1071 0 obj << -/Dest [ 713 0 R /XYZ 40.01575 94.50079 0 ] /Next 1072 0 R /Parent 1044 0 R /Prev 1070 0 R /Title (tpm module) +/Dest [ 724 0 R /XYZ 40.01575 156.1008 0 ] /Next 1072 0 R /Parent 1041 0 R /Prev 1070 0 R /Title (ucode module) >> endobj 1072 0 obj << -/Dest [ 717 0 R /XYZ 40.01575 315.7008 0 ] /Next 1073 0 R /Parent 1044 0 R /Prev 1071 0 R /Title (tpm12_commands module) +/Dest [ 727 0 R /XYZ 40.01575 454.7008 0 ] /Next 1073 0 R /Parent 1041 0 R /Prev 1071 0 R /Title (uefi module) >> endobj 1073 0 obj << -/Dest [ 725 0 R /XYZ 40.01575 663.7008 0 ] /Next 1074 0 R /Parent 1044 0 R /Prev 1072 0 R /Title (tpm_eventlog module) +/Dest [ 729 0 R /XYZ 40.01575 327.7008 0 ] /Next 1074 0 R /Parent 1041 0 R /Prev 1072 0 R /Title (uefi_common module) >> endobj 1074 0 obj << -/Dest [ 725 0 R /XYZ 40.01575 120.1008 0 ] /Next 1075 0 R /Parent 1044 0 R /Prev 1073 0 R /Title (ucode module) +/Dest [ 744 0 R /XYZ 40.01575 435.7008 0 ] /Next 1075 0 R /Parent 1041 0 R /Prev 1073 0 R /Title (uefi_fv module) >> endobj 1075 0 obj << -/Dest [ 728 0 R /XYZ 40.01575 435.5008 0 ] /Next 1076 0 R /Parent 1044 0 R /Prev 1074 0 R /Title (uefi module) +/Dest [ 749 0 R /XYZ 40.01575 507.7008 0 ] /Next 1076 0 R /Parent 1041 0 R /Prev 1074 0 R /Title (uefi_platform module) >> endobj 1076 0 obj << -/Dest [ 730 0 R /XYZ 40.01575 303.7008 0 ] /Next 1077 0 R /Parent 1044 0 R /Prev 1075 0 R /Title (uefi_common module) +/Dest [ 754 0 R /XYZ 40.01575 267.7008 0 ] /Next 1077 0 R /Parent 1041 0 R /Prev 1075 0 R /Title (uefi_search module) >> endobj 1077 0 obj << -/Dest [ 745 0 R /XYZ 40.01575 411.7008 0 ] /Next 1078 0 R /Parent 1044 0 R /Prev 1076 0 R /Title (uefi_fv module) +/Dest [ 754 0 R /XYZ 40.01575 116.7008 0 ] /Next 1078 0 R /Parent 1041 0 R /Prev 1076 0 R /Title (virtmem module) >> endobj 1078 0 obj << -/Dest [ 750 0 R /XYZ 40.01575 483.7008 0 ] /Next 1079 0 R /Parent 1044 0 R /Prev 1077 0 R /Title (uefi_platform module) +/Dest [ 756 0 R /XYZ 40.01575 387.5008 0 ] /Parent 1041 0 R /Prev 1077 0 R /Title (vmm module) >> endobj 1079 0 obj << -/Dest [ 755 0 R /XYZ 40.01575 243.7008 0 ] /Next 1080 0 R /Parent 1044 0 R /Prev 1078 0 R /Title (uefi_search module) +/Count 25 /Dest [ 757 0 R /XYZ 40.01575 723.7008 0 ] /First 1080 0 R /Last 1085 0 R /Next 1105 0 R /Parent 955 0 R + /Prev 1040 0 R /Title (OS Helpers & Drivers) >> endobj 1080 0 obj << -/Dest [ 757 0 R /XYZ 40.01575 775.7008 0 ] /Next 1081 0 R /Parent 1044 0 R /Prev 1079 0 R /Title (virtmem module) +/Count 4 /Dest [ 757 0 R /XYZ 40.01575 653.7008 0 ] /First 1081 0 R /Last 1083 0 R /Next 1085 0 R /Parent 1079 0 R + /Title (OS Helpers and Drivers) >> endobj 1081 0 obj << -/Dest [ 757 0 R /XYZ 40.01575 271.9008 0 ] /Parent 1044 0 R /Prev 1080 0 R /Title (vmm module) +/Dest [ 757 0 R /XYZ 40.01575 586.1008 0 ] /Next 1082 0 R /Parent 1080 0 R /Title (Mostly invoked by HAL modules) >> endobj 1082 0 obj << -/Count 25 /Dest [ 758 0 R /XYZ 40.01575 579.7008 0 ] /First 1083 0 R /Last 1088 0 R /Next 1108 0 R /Parent 958 0 R - /Prev 1043 0 R /Title (OS Helpers & Drivers) +/Dest [ 757 0 R /XYZ 40.01575 518.5008 0 ] /Next 1083 0 R /Parent 1080 0 R /Prev 1081 0 R /Title (Helpers import from BaseHelper) >> endobj 1083 0 obj << -/Count 4 /Dest [ 758 0 R /XYZ 40.01575 509.7008 0 ] /First 1084 0 R /Last 1086 0 R /Next 1088 0 R /Parent 1082 0 R - /Title (OS Helpers and Drivers) +/Count 1 /Dest [ 757 0 R /XYZ 40.01575 432.9008 0 ] /First 1084 0 R /Last 1084 0 R /Parent 1080 0 R /Prev 1082 0 R + /Title (Create a New Helper) >> endobj 1084 0 obj << -/Dest [ 758 0 R /XYZ 40.01575 442.1008 0 ] /Next 1085 0 R /Parent 1083 0 R /Title (Mostly invoked by HAL modules) +/Dest [ 757 0 R /XYZ 40.01575 365.3008 0 ] /Parent 1083 0 R /Title (Example) >> endobj 1085 0 obj << -/Dest [ 758 0 R /XYZ 40.01575 374.5008 0 ] /Next 1086 0 R /Parent 1083 0 R /Prev 1084 0 R /Title (Helpers import from BaseHelper) +/Count 19 /Dest [ 759 0 R /XYZ 40.01575 775.7008 0 ] /First 1086 0 R /Last 1104 0 R /Parent 1079 0 R /Prev 1080 0 R + /Title (helper package) >> endobj 1086 0 obj << -/Count 1 /Dest [ 758 0 R /XYZ 40.01575 288.9008 0 ] /First 1087 0 R /Last 1087 0 R /Parent 1083 0 R /Prev 1085 0 R - /Title (Create a New Helper) +/Count 1 /Dest [ 759 0 R /XYZ 40.01575 726.1008 0 ] /First 1087 0 R /Last 1087 0 R /Next 1088 0 R /Parent 1085 0 R + /Title (dal package) >> endobj 1087 0 obj << -/Dest [ 758 0 R /XYZ 40.01575 221.3008 0 ] /Parent 1086 0 R /Title (Example) +/Dest [ 759 0 R /XYZ 40.01575 676.5008 0 ] /Parent 1086 0 R /Title (dalhelper module) >> endobj 1088 0 obj << -/Count 19 /Dest [ 760 0 R /XYZ 40.01575 625.3008 0 ] /First 1089 0 R /Last 1107 0 R /Parent 1082 0 R /Prev 1083 0 R - /Title (helper package) +/Count 1 /Dest [ 762 0 R /XYZ 40.01575 775.7008 0 ] /First 1089 0 R /Last 1089 0 R /Next 1090 0 R /Parent 1085 0 R + /Prev 1086 0 R /Title (efi package) >> endobj 1089 0 obj << -/Count 1 /Dest [ 760 0 R /XYZ 40.01575 575.7008 0 ] /First 1090 0 R /Last 1090 0 R /Next 1091 0 R /Parent 1088 0 R - /Title (dal package) +/Dest [ 762 0 R /XYZ 40.01575 726.1008 0 ] /Parent 1088 0 R /Title (efihelper module) >> endobj 1090 0 obj << -/Dest [ 760 0 R /XYZ 40.01575 526.1008 0 ] /Parent 1089 0 R /Title (dalhelper module) +/Count 1 /Dest [ 764 0 R /XYZ 40.01575 363.7008 0 ] /First 1091 0 R /Last 1091 0 R /Next 1092 0 R /Parent 1085 0 R + /Prev 1088 0 R /Title (file package) >> endobj 1091 0 obj << -/Count 1 /Dest [ 763 0 R /XYZ 40.01575 639.7008 0 ] /First 1092 0 R /Last 1092 0 R /Next 1093 0 R /Parent 1088 0 R - /Prev 1089 0 R /Title (efi package) +/Dest [ 764 0 R /XYZ 40.01575 314.1008 0 ] /Parent 1090 0 R /Title (filehelper module) >> endobj 1092 0 obj << -/Dest [ 763 0 R /XYZ 40.01575 590.1008 0 ] /Parent 1091 0 R /Title (efihelper module) +/Count 3 /Dest [ 766 0 R /XYZ 40.01575 471.7008 0 ] /First 1093 0 R /Last 1095 0 R /Next 1096 0 R /Parent 1085 0 R + /Prev 1090 0 R /Title (linux package) >> endobj 1093 0 obj << -/Count 1 /Dest [ 764 0 R /XYZ 40.01575 207.7008 0 ] /First 1094 0 R /Last 1094 0 R /Next 1095 0 R /Parent 1088 0 R - /Prev 1091 0 R /Title (file package) +/Dest [ 766 0 R /XYZ 40.01575 422.1008 0 ] /Next 1094 0 R /Parent 1092 0 R /Title (cpuid module) >> endobj 1094 0 obj << -/Dest [ 764 0 R /XYZ 40.01575 158.1008 0 ] /Parent 1093 0 R /Title (filehelper module) +/Dest [ 766 0 R /XYZ 40.01575 150.5008 0 ] /Next 1095 0 R /Parent 1092 0 R /Prev 1093 0 R /Title (legacy_pci module) >> endobj 1095 0 obj << -/Count 3 /Dest [ 767 0 R /XYZ 40.01575 315.7008 0 ] /First 1096 0 R /Last 1098 0 R /Next 1099 0 R /Parent 1088 0 R - /Prev 1093 0 R /Title (linux package) +/Dest [ 768 0 R /XYZ 40.01575 639.7008 0 ] /Parent 1092 0 R /Prev 1094 0 R /Title (linuxhelper module) >> endobj 1096 0 obj << -/Dest [ 767 0 R /XYZ 40.01575 266.1008 0 ] /Next 1097 0 R /Parent 1095 0 R /Title (cpuid module) +/Count 1 /Dest [ 773 0 R /XYZ 40.01575 775.7008 0 ] /First 1097 0 R /Last 1097 0 R /Next 1098 0 R /Parent 1085 0 R + /Prev 1092 0 R /Title (osx package) >> endobj 1097 0 obj << -/Dest [ 769 0 R /XYZ 40.01575 711.7008 0 ] /Next 1098 0 R /Parent 1095 0 R /Prev 1096 0 R /Title (legacy_pci module) +/Dest [ 773 0 R /XYZ 40.01575 726.1008 0 ] /Parent 1096 0 R /Title (osxhelper module) >> endobj 1098 0 obj << -/Dest [ 769 0 R /XYZ 40.01575 488.1008 0 ] /Parent 1095 0 R /Prev 1097 0 R /Title (linuxhelper module) +/Count 1 /Dest [ 775 0 R /XYZ 40.01575 639.7008 0 ] /First 1099 0 R /Last 1099 0 R /Next 1100 0 R /Parent 1085 0 R + /Prev 1096 0 R /Title (rwe package) >> endobj 1099 0 obj << -/Count 1 /Dest [ 774 0 R /XYZ 40.01575 639.7008 0 ] /First 1100 0 R /Last 1100 0 R /Next 1101 0 R /Parent 1088 0 R - /Prev 1095 0 R /Title (osx package) +/Dest [ 775 0 R /XYZ 40.01575 590.1008 0 ] /Parent 1098 0 R /Title (rwehelper module) >> endobj 1100 0 obj << -/Dest [ 774 0 R /XYZ 40.01575 590.1008 0 ] /Parent 1099 0 R /Title (osxhelper module) +/Count 1 /Dest [ 775 0 R /XYZ 40.01575 540.5008 0 ] /First 1101 0 R /Last 1101 0 R /Next 1102 0 R /Parent 1085 0 R + /Prev 1098 0 R /Title (win package) >> endobj 1101 0 obj << -/Count 1 /Dest [ 776 0 R /XYZ 40.01575 519.7008 0 ] /First 1102 0 R /Last 1102 0 R /Next 1103 0 R /Parent 1088 0 R - /Prev 1099 0 R /Title (rwe package) +/Dest [ 775 0 R /XYZ 40.01575 490.9008 0 ] /Parent 1100 0 R /Title (win32helper module) >> endobj 1102 0 obj << -/Dest [ 776 0 R /XYZ 40.01575 470.1008 0 ] /Parent 1101 0 R /Title (rwehelper module) +/Dest [ 775 0 R /XYZ 40.01575 441.3008 0 ] /Next 1103 0 R /Parent 1085 0 R /Prev 1100 0 R /Title (basehelper module) >> endobj 1103 0 obj << -/Count 1 /Dest [ 776 0 R /XYZ 40.01575 420.5008 0 ] /First 1104 0 R /Last 1104 0 R /Next 1105 0 R /Parent 1088 0 R - /Prev 1101 0 R /Title (win package) +/Dest [ 777 0 R /XYZ 40.01575 687.7008 0 ] /Next 1104 0 R /Parent 1085 0 R /Prev 1102 0 R /Title (helpers module) >> endobj 1104 0 obj << -/Dest [ 776 0 R /XYZ 40.01575 370.9008 0 ] /Parent 1103 0 R /Title (win32helper module) +/Dest [ 777 0 R /XYZ 40.01575 638.1008 0 ] /Parent 1085 0 R /Prev 1103 0 R /Title (oshelper module) >> endobj 1105 0 obj << -/Dest [ 776 0 R /XYZ 40.01575 321.3008 0 ] /Next 1106 0 R /Parent 1088 0 R /Prev 1103 0 R /Title (basehelper module) +/Count 2 /Dest [ 780 0 R /XYZ 40.01575 699.7008 0 ] /First 1106 0 R /Last 1106 0 R /Parent 955 0 R /Prev 1079 0 R + /Title (Fuzzing) >> endobj 1106 0 obj << -/Dest [ 779 0 R /XYZ 40.01575 567.7008 0 ] /Next 1107 0 R /Parent 1088 0 R /Prev 1105 0 R /Title (helpers module) +/Count 1 /Dest [ 780 0 R /XYZ 40.01575 647.7008 0 ] /First 1107 0 R /Last 1107 0 R /Parent 1105 0 R /Title (fuzzing package) >> endobj 1107 0 obj << -/Dest [ 779 0 R /XYZ 40.01575 518.1008 0 ] /Parent 1088 0 R /Prev 1106 0 R /Title (oshelper module) +/Dest [ 780 0 R /XYZ 40.01575 598.1008 0 ] /Parent 1106 0 R /Title (primitives module) >> endobj 1108 0 obj << -/Count 2 /Dest [ 783 0 R /XYZ 40.01575 411.7008 0 ] /First 1109 0 R /Last 1109 0 R /Parent 958 0 R /Prev 1082 0 R - /Title (Fuzzing) +/Dest [ 797 0 R /XYZ 40.01575 567.7008 0 ] /Next 1109 0 R /Parent 953 0 R /Prev 955 0 R /Title (CHIPSEC_MAIN Program Flow) >> endobj 1109 0 obj << -/Count 1 /Dest [ 783 0 R /XYZ 40.01575 359.7008 0 ] /First 1110 0 R /Last 1110 0 R /Parent 1108 0 R /Title (fuzzing package) +/Dest [ 797 0 R /XYZ 40.01575 363.3008 0 ] /Next 1110 0 R /Parent 953 0 R /Prev 1108 0 R /Title (CHIPSEC_UTIL Program Flow) >> endobj 1110 0 obj << -/Dest [ 783 0 R /XYZ 40.01575 310.1008 0 ] /Parent 1109 0 R /Title (primitives module) +/Dest [ 797 0 R /XYZ 40.01575 176.9008 0 ] /Next 1111 0 R /Parent 953 0 R /Prev 1109 0 R /Title (Auxiliary components) >> endobj 1111 0 obj << -/Dest [ 798 0 R /XYZ 40.01575 291.7008 0 ] /Next 1112 0 R /Parent 956 0 R /Prev 958 0 R /Title (CHIPSEC_MAIN Program Flow) +/Dest [ 797 0 R /XYZ 40.01575 86.50079 0 ] /Parent 953 0 R /Prev 1110 0 R /Title (Executable build scripts) >> endobj 1112 0 obj << -/Dest [ 798 0 R /XYZ 40.01575 87.30079 0 ] /Next 1113 0 R /Parent 956 0 R /Prev 1111 0 R /Title (CHIPSEC_UTIL Program Flow) +/Count 79 /Dest [ 798 0 R /XYZ 40.01575 717.7008 0 ] /First 1113 0 R /Last 1114 0 R /Next 1192 0 R /Parent 952 0 R + /Prev 953 0 R /Title (CHIPSEC Modules) >> endobj 1113 0 obj << -/Dest [ 802 0 R /XYZ 40.01575 615.7008 0 ] /Next 1114 0 R /Parent 956 0 R /Prev 1112 0 R /Title (Auxiliary components) +/Dest [ 798 0 R /XYZ 40.01575 660.9008 0 ] /Next 1114 0 R /Parent 1112 0 R /Title (Introduction) >> endobj 1114 0 obj << -/Dest [ 802 0 R /XYZ 40.01575 525.3008 0 ] /Parent 956 0 R /Prev 1113 0 R /Title (Executable build scripts) +/Count 77 /Dest [ 802 0 R /XYZ 40.01575 484.9008 0 ] /First 1115 0 R /Last 1115 0 R /Parent 1112 0 R /Prev 1113 0 R + /Title (Modules) >> endobj 1115 0 obj << -/Count 79 /Dest [ 802 0 R /XYZ 40.01575 446.9008 0 ] /First 1116 0 R /Last 1117 0 R /Next 1195 0 R /Parent 955 0 R - /Prev 956 0 R /Title (CHIPSEC Modules) +/Count 76 /Dest [ 802 0 R /XYZ 40.01575 430.5008 0 ] /First 1116 0 R /Last 1153 0 R /Parent 1114 0 R /Title (modules package) >> endobj 1116 0 obj << -/Dest [ 802 0 R /XYZ 40.01575 390.1008 0 ] /Next 1117 0 R /Parent 1115 0 R /Title (Introduction) +/Dest [ 802 0 R /XYZ 40.01575 378.5008 0 ] /Next 1117 0 R /Parent 1115 0 R /Title (bdw package) >> endobj 1117 0 obj << -/Count 77 /Dest [ 807 0 R /XYZ 40.01575 775.7008 0 ] /First 1118 0 R /Last 1118 0 R /Parent 1115 0 R /Prev 1116 0 R - /Title (Modules) +/Dest [ 802 0 R /XYZ 40.01575 328.9008 0 ] /Next 1118 0 R /Parent 1115 0 R /Prev 1116 0 R /Title (byt package) >> endobj 1118 0 obj << -/Count 76 /Dest [ 807 0 R /XYZ 40.01575 721.3008 0 ] /First 1119 0 R /Last 1156 0 R /Parent 1117 0 R /Title (modules package) +/Count 31 /Dest [ 802 0 R /XYZ 40.01575 279.3008 0 ] /First 1119 0 R /Last 1149 0 R /Next 1150 0 R /Parent 1115 0 R + /Prev 1117 0 R /Title (common package) >> endobj 1119 0 obj << -/Dest [ 807 0 R /XYZ 40.01575 669.3008 0 ] /Next 1120 0 R /Parent 1118 0 R /Title (bdw package) +/Count 3 /Dest [ 802 0 R /XYZ 40.01575 229.7008 0 ] /First 1120 0 R /Last 1122 0 R /Next 1123 0 R /Parent 1118 0 R + /Title (cpu package) >> endobj 1120 0 obj << -/Dest [ 807 0 R /XYZ 40.01575 619.7008 0 ] /Next 1121 0 R /Parent 1118 0 R /Prev 1119 0 R /Title (byt package) +/Dest [ 802 0 R /XYZ 40.01575 180.1008 0 ] /Next 1121 0 R /Parent 1119 0 R /Title (cpu_info module) >> endobj 1121 0 obj << -/Count 31 /Dest [ 807 0 R /XYZ 40.01575 570.1008 0 ] /First 1122 0 R /Last 1152 0 R /Next 1153 0 R /Parent 1118 0 R - /Prev 1120 0 R /Title (common package) +/Dest [ 803 0 R /XYZ 40.01575 723.7008 0 ] /Next 1122 0 R /Parent 1119 0 R /Prev 1120 0 R /Title (ia_untrusted module) >> endobj 1122 0 obj << -/Count 3 /Dest [ 807 0 R /XYZ 40.01575 520.5008 0 ] /First 1123 0 R /Last 1125 0 R /Next 1126 0 R /Parent 1121 0 R - /Title (cpu package) +/Dest [ 803 0 R /XYZ 40.01575 524.1008 0 ] /Parent 1119 0 R /Prev 1121 0 R /Title (spectre_v2 module) >> endobj 1123 0 obj << -/Dest [ 807 0 R /XYZ 40.01575 470.9008 0 ] /Next 1124 0 R /Parent 1122 0 R /Title (cpu_info module) +/Count 1 /Dest [ 812 0 R /XYZ 40.01575 775.7008 0 ] /First 1124 0 R /Last 1124 0 R /Next 1125 0 R /Parent 1118 0 R + /Prev 1119 0 R /Title (secureboot package) >> endobj 1124 0 obj << -/Dest [ 807 0 R /XYZ 40.01575 295.3008 0 ] /Next 1125 0 R /Parent 1122 0 R /Prev 1123 0 R /Title (ia_untrusted module) +/Dest [ 812 0 R /XYZ 40.01575 726.1008 0 ] /Parent 1123 0 R /Title (variables module) >> endobj 1125 0 obj << -/Dest [ 808 0 R /XYZ 40.01575 775.7008 0 ] /Parent 1122 0 R /Prev 1124 0 R /Title (spectre_v2 module) +/Count 2 /Dest [ 812 0 R /XYZ 40.01575 454.5008 0 ] /First 1126 0 R /Last 1127 0 R /Next 1128 0 R /Parent 1118 0 R + /Prev 1123 0 R /Title (uefi package) >> endobj 1126 0 obj << -/Count 1 /Dest [ 815 0 R /XYZ 40.01575 291.7008 0 ] /First 1127 0 R /Last 1127 0 R /Next 1128 0 R /Parent 1121 0 R - /Prev 1122 0 R /Title (secureboot package) +/Dest [ 812 0 R /XYZ 40.01575 404.9008 0 ] /Next 1127 0 R /Parent 1125 0 R /Title (access_uefispec module) >> endobj 1127 0 obj << -/Dest [ 815 0 R /XYZ 40.01575 242.1008 0 ] /Parent 1126 0 R /Title (variables module) +/Dest [ 818 0 R /XYZ 40.01575 687.7008 0 ] /Parent 1125 0 R /Prev 1126 0 R /Title (s3bootscript module) >> endobj 1128 0 obj << -/Count 2 /Dest [ 822 0 R /XYZ 40.01575 675.7008 0 ] /First 1129 0 R /Last 1130 0 R /Next 1131 0 R /Parent 1121 0 R - /Prev 1126 0 R /Title (uefi package) +/Dest [ 825 0 R /XYZ 40.01575 775.7008 0 ] /Next 1129 0 R /Parent 1118 0 R /Prev 1125 0 R /Title (bios_kbrd_buffer module) >> endobj 1129 0 obj << -/Dest [ 822 0 R /XYZ 40.01575 626.1008 0 ] /Next 1130 0 R /Parent 1128 0 R /Title (access_uefispec module) +/Dest [ 825 0 R /XYZ 40.01575 528.1008 0 ] /Next 1130 0 R /Parent 1118 0 R /Prev 1128 0 R /Title (bios_smi module) >> endobj 1130 0 obj << -/Dest [ 822 0 R /XYZ 40.01575 360.5008 0 ] /Parent 1128 0 R /Prev 1129 0 R /Title (s3bootscript module) +/Dest [ 825 0 R /XYZ 40.01575 238.5008 0 ] /Next 1131 0 R /Parent 1118 0 R /Prev 1129 0 R /Title (bios_ts module) >> endobj 1131 0 obj << -/Dest [ 828 0 R /XYZ 40.01575 579.7008 0 ] /Next 1132 0 R /Parent 1121 0 R /Prev 1128 0 R /Title (bios_kbrd_buffer module) +/Dest [ 828 0 R /XYZ 40.01575 723.7008 0 ] /Next 1132 0 R /Parent 1118 0 R /Prev 1130 0 R /Title (bios_wp module) >> endobj 1132 0 obj << -/Dest [ 828 0 R /XYZ 40.01575 332.1008 0 ] /Next 1133 0 R /Parent 1121 0 R /Prev 1131 0 R /Title (bios_smi module) +/Dest [ 828 0 R /XYZ 40.01575 266.1008 0 ] /Next 1133 0 R /Parent 1118 0 R /Prev 1131 0 R /Title (debugenabled module) >> endobj 1133 0 obj << -/Dest [ 832 0 R /XYZ 40.01575 775.7008 0 ] /Next 1134 0 R /Parent 1121 0 R /Prev 1132 0 R /Title (bios_ts module) +/Dest [ 834 0 R /XYZ 40.01575 627.7008 0 ] /Next 1134 0 R /Parent 1118 0 R /Prev 1132 0 R /Title (ia32cfg module) >> endobj 1134 0 obj << -/Dest [ 832 0 R /XYZ 40.01575 558.1008 0 ] /Next 1135 0 R /Parent 1121 0 R /Prev 1133 0 R /Title (bios_wp module) +/Dest [ 834 0 R /XYZ 40.01575 398.1008 0 ] /Next 1135 0 R /Parent 1118 0 R /Prev 1133 0 R /Title (me_mfg_mode module) >> endobj 1135 0 obj << -/Dest [ 832 0 R /XYZ 40.01575 100.5008 0 ] /Next 1136 0 R /Parent 1121 0 R /Prev 1134 0 R /Title (debugenabled module) +/Dest [ 838 0 R /XYZ 40.01575 355.7008 0 ] /Next 1136 0 R /Parent 1118 0 R /Prev 1134 0 R /Title (memconfig module) >> endobj 1136 0 obj << -/Dest [ 836 0 R /XYZ 40.01575 471.7008 0 ] /Next 1137 0 R /Parent 1121 0 R /Prev 1135 0 R /Title (ia32cfg module) +/Dest [ 838 0 R /XYZ 40.01575 144.1008 0 ] /Next 1137 0 R /Parent 1118 0 R /Prev 1135 0 R /Title (memlock module) >> endobj 1137 0 obj << -/Dest [ 836 0 R /XYZ 40.01575 242.1008 0 ] /Next 1138 0 R /Parent 1121 0 R /Prev 1136 0 R /Title (me_mfg_mode module) +/Dest [ 840 0 R /XYZ 40.01575 420.5008 0 ] /Next 1138 0 R /Parent 1118 0 R /Prev 1136 0 R /Title (remap module) >> endobj 1138 0 obj << -/Dest [ 840 0 R /XYZ 40.01575 206.1008 0 ] /Next 1139 0 R /Parent 1121 0 R /Prev 1137 0 R /Title (memconfig module) +/Dest [ 844 0 R /XYZ 40.01575 775.7008 0 ] /Next 1139 0 R /Parent 1118 0 R /Prev 1137 0 R /Title (rtclock module) >> endobj 1139 0 obj << -/Dest [ 844 0 R /XYZ 40.01575 687.7008 0 ] /Next 1140 0 R /Parent 1121 0 R /Prev 1138 0 R /Title (memlock module) +/Dest [ 844 0 R /XYZ 40.01575 564.1008 0 ] /Next 1140 0 R /Parent 1118 0 R /Prev 1138 0 R /Title (sgx_check module) >> endobj 1140 0 obj << -/Dest [ 844 0 R /XYZ 40.01575 392.1008 0 ] /Next 1141 0 R /Parent 1121 0 R /Prev 1139 0 R /Title (remap module) +/Dest [ 844 0 R /XYZ 40.01575 364.5008 0 ] /Next 1141 0 R /Parent 1118 0 R /Prev 1139 0 R /Title (smm module) >> endobj 1141 0 obj << -/Dest [ 844 0 R /XYZ 40.01575 174.5008 0 ] /Next 1142 0 R /Parent 1121 0 R /Prev 1140 0 R /Title (rtclock module) +/Dest [ 850 0 R /XYZ 40.01575 687.7008 0 ] /Next 1142 0 R /Parent 1118 0 R /Prev 1140 0 R /Title (smm_code_chk module) >> endobj 1142 0 obj << -/Dest [ 848 0 R /XYZ 40.01575 675.7008 0 ] /Next 1143 0 R /Parent 1121 0 R /Prev 1141 0 R /Title (sgx_check module) +/Dest [ 850 0 R /XYZ 40.01575 452.1008 0 ] /Next 1143 0 R /Parent 1118 0 R /Prev 1141 0 R /Title (smm_dma module) >> endobj 1143 0 obj << -/Dest [ 848 0 R /XYZ 40.01575 476.1008 0 ] /Next 1144 0 R /Parent 1121 0 R /Prev 1142 0 R /Title (smm module) +/Dest [ 854 0 R /XYZ 40.01575 775.7008 0 ] /Next 1144 0 R /Parent 1118 0 R /Prev 1142 0 R /Title (smrr module) >> endobj 1144 0 obj << -/Dest [ 848 0 R /XYZ 40.01575 192.5008 0 ] /Next 1145 0 R /Parent 1121 0 R /Prev 1143 0 R /Title (smm_code_chk module) +/Dest [ 854 0 R /XYZ 40.01575 498.1008 0 ] /Next 1145 0 R /Parent 1118 0 R /Prev 1143 0 R /Title (spd_wd module) >> endobj 1145 0 obj << -/Dest [ 857 0 R /XYZ 40.01575 675.7008 0 ] /Next 1146 0 R /Parent 1121 0 R /Prev 1144 0 R /Title (smm_dma module) +/Dest [ 854 0 R /XYZ 40.01575 106.5008 0 ] /Next 1146 0 R /Parent 1118 0 R /Prev 1144 0 R /Title (spi_access module) >> endobj 1146 0 obj << -/Dest [ 857 0 R /XYZ 40.01575 320.1008 0 ] /Next 1147 0 R /Parent 1121 0 R /Prev 1145 0 R /Title (smrr module) +/Dest [ 858 0 R /XYZ 40.01575 615.7008 0 ] /Next 1147 0 R /Parent 1118 0 R /Prev 1145 0 R /Title (spi_desc module) >> endobj 1147 0 obj << -/Dest [ 858 0 R /XYZ 40.01575 775.7008 0 ] /Next 1148 0 R /Parent 1121 0 R /Prev 1146 0 R /Title (spd_wd module) +/Dest [ 858 0 R /XYZ 40.01575 362.1008 0 ] /Next 1148 0 R /Parent 1118 0 R /Prev 1146 0 R /Title (spi_fdopss module) >> endobj 1148 0 obj << -/Dest [ 858 0 R /XYZ 40.01575 384.1008 0 ] /Next 1149 0 R /Parent 1121 0 R /Prev 1147 0 R /Title (spi_access module) +/Dest [ 858 0 R /XYZ 40.01575 150.5008 0 ] /Next 1149 0 R /Parent 1118 0 R /Prev 1147 0 R /Title (spi_lock module) >> endobj 1149 0 obj << -/Dest [ 858 0 R /XYZ 40.01575 184.5008 0 ] /Next 1150 0 R /Parent 1121 0 R /Prev 1148 0 R /Title (spi_desc module) +/Dest [ 860 0 R /XYZ 40.01575 591.7008 0 ] /Parent 1118 0 R /Prev 1148 0 R /Title (wsmt module) >> endobj 1150 0 obj << -/Dest [ 863 0 R /XYZ 40.01575 651.7008 0 ] /Next 1151 0 R /Parent 1121 0 R /Prev 1149 0 R /Title (spi_fdopss module) +/Dest [ 860 0 R /XYZ 40.01575 356.1008 0 ] /Next 1151 0 R /Parent 1115 0 R /Prev 1118 0 R /Title (hsw package) >> endobj 1151 0 obj << -/Dest [ 863 0 R /XYZ 40.01575 440.1008 0 ] /Next 1152 0 R /Parent 1121 0 R /Prev 1150 0 R /Title (spi_lock module) +/Dest [ 860 0 R /XYZ 40.01575 306.5008 0 ] /Next 1152 0 R /Parent 1115 0 R /Prev 1150 0 R /Title (ivb package) >> endobj 1152 0 obj << -/Dest [ 863 0 R /XYZ 40.01575 168.5008 0 ] /Parent 1121 0 R /Prev 1151 0 R /Title (wsmt module) +/Dest [ 860 0 R /XYZ 40.01575 256.9008 0 ] /Next 1153 0 R /Parent 1115 0 R /Prev 1151 0 R /Title (snb package) >> endobj 1153 0 obj << -/Dest [ 869 0 R /XYZ 40.01575 651.7008 0 ] /Next 1154 0 R /Parent 1118 0 R /Prev 1121 0 R /Title (hsw package) +/Count 38 /Dest [ 860 0 R /XYZ 40.01575 207.3008 0 ] /First 1154 0 R /Last 1167 0 R /Parent 1115 0 R /Prev 1152 0 R + /Title (tools package) >> endobj 1154 0 obj << -/Dest [ 869 0 R /XYZ 40.01575 602.1008 0 ] /Next 1155 0 R /Parent 1118 0 R /Prev 1153 0 R /Title (ivb package) +/Count 1 /Dest [ 860 0 R /XYZ 40.01575 157.7008 0 ] /First 1155 0 R /Last 1155 0 R /Next 1156 0 R /Parent 1153 0 R + /Title (cpu package) >> endobj 1155 0 obj << -/Dest [ 869 0 R /XYZ 40.01575 552.5008 0 ] /Next 1156 0 R /Parent 1118 0 R /Prev 1154 0 R /Title (snb package) +/Dest [ 860 0 R /XYZ 40.01575 108.1008 0 ] /Parent 1154 0 R /Title (sinkhole module) >> endobj 1156 0 obj << -/Count 38 /Dest [ 869 0 R /XYZ 40.01575 502.9008 0 ] /First 1157 0 R /Last 1170 0 R /Parent 1118 0 R /Prev 1155 0 R - /Title (tools package) +/Count 1 /Dest [ 868 0 R /XYZ 40.01575 507.7008 0 ] /First 1157 0 R /Last 1157 0 R /Next 1158 0 R /Parent 1153 0 R + /Prev 1154 0 R /Title (secureboot package) >> endobj 1157 0 obj << -/Count 1 /Dest [ 869 0 R /XYZ 40.01575 453.3008 0 ] /First 1158 0 R /Last 1158 0 R /Next 1159 0 R /Parent 1156 0 R - /Title (cpu package) +/Dest [ 868 0 R /XYZ 40.01575 458.1008 0 ] /Parent 1156 0 R /Title (te module) >> endobj 1158 0 obj << -/Dest [ 869 0 R /XYZ 40.01575 403.7008 0 ] /Parent 1157 0 R /Title (sinkhole module) +/Count 2 /Dest [ 870 0 R /XYZ 40.01575 399.7008 0 ] /First 1159 0 R /Last 1160 0 R /Next 1161 0 R /Parent 1153 0 R + /Prev 1156 0 R /Title (smm package) >> endobj 1159 0 obj << -/Count 1 /Dest [ 872 0 R /XYZ 40.01575 775.7008 0 ] /First 1160 0 R /Last 1160 0 R /Next 1161 0 R /Parent 1156 0 R - /Prev 1157 0 R /Title (secureboot package) +/Dest [ 870 0 R /XYZ 40.01575 350.1008 0 ] /Next 1160 0 R /Parent 1158 0 R /Title (rogue_mmio_bar module) >> endobj 1160 0 obj << -/Dest [ 872 0 R /XYZ 40.01575 726.1008 0 ] /Parent 1159 0 R /Title (te module) +/Dest [ 872 0 R /XYZ 40.01575 651.7008 0 ] /Parent 1158 0 R /Prev 1159 0 R /Title (smm_ptr module) >> endobj 1161 0 obj << -/Count 2 /Dest [ 875 0 R /XYZ 40.01575 639.7008 0 ] /First 1162 0 R /Last 1163 0 R /Next 1164 0 R /Parent 1156 0 R - /Prev 1159 0 R /Title (smm package) +/Count 5 /Dest [ 874 0 R /XYZ 40.01575 495.7008 0 ] /First 1162 0 R /Last 1166 0 R /Next 1167 0 R /Parent 1153 0 R + /Prev 1158 0 R /Title (uefi package) >> endobj 1162 0 obj << -/Dest [ 875 0 R /XYZ 40.01575 590.1008 0 ] /Next 1163 0 R /Parent 1161 0 R /Title (rogue_mmio_bar module) +/Dest [ 874 0 R /XYZ 40.01575 446.1008 0 ] /Next 1163 0 R /Parent 1161 0 R /Title (reputation module) >> endobj 1163 0 obj << -/Dest [ 875 0 R /XYZ 40.01575 188.5008 0 ] /Parent 1161 0 R /Prev 1162 0 R /Title (smm_ptr module) +/Dest [ 875 0 R /XYZ 40.01575 723.7008 0 ] /Next 1164 0 R /Parent 1161 0 R /Prev 1162 0 R /Title (s3script_modify module) >> endobj 1164 0 obj << -/Count 5 /Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /First 1165 0 R /Last 1169 0 R /Next 1170 0 R /Parent 1156 0 R - /Prev 1161 0 R /Title (uefi package) +/Dest [ 876 0 R /XYZ 40.01575 435.7008 0 ] /Next 1165 0 R /Parent 1161 0 R /Prev 1163 0 R /Title (scan_blocked module) >> endobj 1165 0 obj << -/Dest [ 878 0 R /XYZ 40.01575 650.1008 0 ] /Next 1166 0 R /Parent 1164 0 R /Title (reputation module) +/Dest [ 877 0 R /XYZ 40.01575 603.7008 0 ] /Next 1166 0 R /Parent 1161 0 R /Prev 1164 0 R /Title (scan_image module) >> endobj 1166 0 obj << -/Dest [ 878 0 R /XYZ 40.01575 213.5008 0 ] /Next 1167 0 R /Parent 1164 0 R /Prev 1165 0 R /Title (s3script_modify module) +/Dest [ 878 0 R /XYZ 40.01575 699.7008 0 ] /Parent 1161 0 R /Prev 1165 0 R /Title (uefivar_fuzz module) >> endobj 1167 0 obj << -/Dest [ 880 0 R /XYZ 40.01575 603.7008 0 ] /Next 1168 0 R /Parent 1164 0 R /Prev 1166 0 R /Title (scan_blocked module) +/Count 24 /Dest [ 880 0 R /XYZ 40.01575 775.7008 0 ] /First 1168 0 R /Last 1191 0 R /Parent 1153 0 R /Prev 1161 0 R + /Title (vmm package) >> endobj 1168 0 obj << -/Dest [ 881 0 R /XYZ 40.01575 775.7008 0 ] /Next 1169 0 R /Parent 1164 0 R /Prev 1167 0 R /Title (scan_image module) +/Count 7 /Dest [ 880 0 R /XYZ 40.01575 726.1008 0 ] /First 1169 0 R /Last 1175 0 R /Next 1176 0 R /Parent 1167 0 R + /Title (hv package) >> endobj 1169 0 obj << -/Dest [ 881 0 R /XYZ 40.01575 156.9008 0 ] /Parent 1164 0 R /Prev 1168 0 R /Title (uefivar_fuzz module) +/Dest [ 880 0 R /XYZ 40.01575 676.5008 0 ] /Next 1170 0 R /Parent 1168 0 R /Title (define module) >> endobj 1170 0 obj << -/Count 24 /Dest [ 882 0 R /XYZ 40.01575 346.5008 0 ] /First 1171 0 R /Last 1194 0 R /Parent 1156 0 R /Prev 1164 0 R - /Title (vmm package) +/Dest [ 880 0 R /XYZ 40.01575 512.9008 0 ] /Next 1171 0 R /Parent 1168 0 R /Prev 1169 0 R /Title (hypercall module) >> endobj 1171 0 obj << -/Count 7 /Dest [ 882 0 R /XYZ 40.01575 296.9008 0 ] /First 1172 0 R /Last 1178 0 R /Next 1179 0 R /Parent 1170 0 R - /Title (hv package) +/Dest [ 883 0 R /XYZ 40.01575 699.7008 0 ] /Next 1172 0 R /Parent 1168 0 R /Prev 1170 0 R /Title (hypercallfuzz module) >> endobj 1172 0 obj << -/Dest [ 882 0 R /XYZ 40.01575 247.3008 0 ] /Next 1173 0 R /Parent 1171 0 R /Title (define module) +/Dest [ 883 0 R /XYZ 40.01575 337.1008 0 ] /Next 1173 0 R /Parent 1168 0 R /Prev 1171 0 R /Title (synth_dev module) >> endobj 1173 0 obj << -/Dest [ 885 0 R /XYZ 40.01575 775.7008 0 ] /Next 1174 0 R /Parent 1171 0 R /Prev 1172 0 R /Title (hypercall module) +/Dest [ 887 0 R /XYZ 40.01575 639.7008 0 ] /Next 1174 0 R /Parent 1168 0 R /Prev 1172 0 R /Title (synth_kbd module) >> endobj 1174 0 obj << -/Dest [ 885 0 R /XYZ 40.01575 264.1008 0 ] /Next 1175 0 R /Parent 1171 0 R /Prev 1173 0 R /Title (hypercallfuzz module) +/Dest [ 887 0 R /XYZ 40.01575 355.1008 0 ] /Next 1175 0 R /Parent 1168 0 R /Prev 1173 0 R /Title (vmbus module) >> endobj 1175 0 obj << -/Dest [ 888 0 R /XYZ 40.01575 615.7008 0 ] /Next 1176 0 R /Parent 1171 0 R /Prev 1174 0 R /Title (synth_dev module) +/Dest [ 892 0 R /XYZ 40.01575 423.7008 0 ] /Parent 1168 0 R /Prev 1174 0 R /Title (vmbusfuzz module) >> endobj 1176 0 obj << -/Dest [ 888 0 R /XYZ 40.01575 200.1008 0 ] /Next 1177 0 R /Parent 1171 0 R /Prev 1175 0 R /Title (synth_kbd module) +/Count 1 /Dest [ 895 0 R /XYZ 40.01575 775.7008 0 ] /First 1177 0 R /Last 1177 0 R /Next 1178 0 R /Parent 1167 0 R + /Prev 1168 0 R /Title (vbox package) >> endobj 1177 0 obj << -/Dest [ 892 0 R /XYZ 40.01575 615.7008 0 ] /Next 1178 0 R /Parent 1171 0 R /Prev 1176 0 R /Title (vmbus module) +/Dest [ 895 0 R /XYZ 40.01575 726.1008 0 ] /Parent 1176 0 R /Title (vbox_crash_apicbase module) >> endobj 1178 0 obj << -/Dest [ 897 0 R /XYZ 40.01575 699.7008 0 ] /Parent 1171 0 R /Prev 1177 0 R /Title (vmbusfuzz module) +/Count 4 /Dest [ 895 0 R /XYZ 40.01575 553.5008 0 ] /First 1179 0 R /Last 1182 0 R /Next 1183 0 R /Parent 1167 0 R + /Prev 1176 0 R /Title (xen package) >> endobj 1179 0 obj << -/Count 1 /Dest [ 897 0 R /XYZ 40.01575 337.1008 0 ] /First 1180 0 R /Last 1180 0 R /Next 1181 0 R /Parent 1170 0 R - /Prev 1171 0 R /Title (vbox package) +/Dest [ 895 0 R /XYZ 40.01575 503.9008 0 ] /Next 1180 0 R /Parent 1178 0 R /Title (define module) >> endobj 1180 0 obj << -/Dest [ 897 0 R /XYZ 40.01575 287.5008 0 ] /Parent 1179 0 R /Title (vbox_crash_apicbase module) +/Dest [ 895 0 R /XYZ 40.01575 292.3008 0 ] /Next 1181 0 R /Parent 1178 0 R /Prev 1179 0 R /Title (hypercall module) >> endobj 1181 0 obj << -/Count 4 /Dest [ 899 0 R /XYZ 40.01575 775.7008 0 ] /First 1182 0 R /Last 1185 0 R /Next 1186 0 R /Parent 1170 0 R - /Prev 1179 0 R /Title (xen package) +/Dest [ 897 0 R /XYZ 40.01575 651.7008 0 ] /Next 1182 0 R /Parent 1178 0 R /Prev 1180 0 R /Title (hypercallfuzz module) >> endobj 1182 0 obj << -/Dest [ 899 0 R /XYZ 40.01575 726.1008 0 ] /Next 1183 0 R /Parent 1181 0 R /Title (define module) +/Dest [ 897 0 R /XYZ 40.01575 193.1008 0 ] /Parent 1178 0 R /Prev 1181 0 R /Title (xsa188 module) >> endobj 1183 0 obj << -/Dest [ 899 0 R /XYZ 40.01575 514.5008 0 ] /Next 1184 0 R /Parent 1181 0 R /Prev 1182 0 R /Title (hypercall module) +/Dest [ 900 0 R /XYZ 40.01575 723.7008 0 ] /Next 1184 0 R /Parent 1167 0 R /Prev 1178 0 R /Title (common module) >> endobj 1184 0 obj << -/Dest [ 899 0 R /XYZ 40.01575 170.9008 0 ] /Next 1185 0 R /Parent 1181 0 R /Prev 1183 0 R /Title (hypercallfuzz module) +/Dest [ 902 0 R /XYZ 40.01575 651.7008 0 ] /Next 1185 0 R /Parent 1167 0 R /Prev 1183 0 R /Title (cpuid_fuzz module) >> endobj 1185 0 obj << -/Dest [ 901 0 R /XYZ 40.01575 414.7008 0 ] /Parent 1181 0 R /Prev 1184 0 R /Title (xsa188 module) +/Dest [ 902 0 R /XYZ 40.01575 467.1008 0 ] /Next 1186 0 R /Parent 1167 0 R /Prev 1184 0 R /Title (ept_finder module) >> endobj 1186 0 obj << -/Dest [ 901 0 R /XYZ 40.01575 226.1008 0 ] /Next 1187 0 R /Parent 1170 0 R /Prev 1181 0 R /Title (common module) +/Dest [ 902 0 R /XYZ 40.01575 96.50079 0 ] /Next 1187 0 R /Parent 1167 0 R /Prev 1185 0 R /Title (hypercallfuzz module) >> endobj 1187 0 obj << -/Dest [ 904 0 R /XYZ 40.01575 159.7008 0 ] /Next 1188 0 R /Parent 1170 0 R /Prev 1186 0 R /Title (cpuid_fuzz module) +/Dest [ 903 0 R /XYZ 40.01575 423.7008 0 ] /Next 1188 0 R /Parent 1167 0 R /Prev 1186 0 R /Title (iofuzz module) >> endobj 1188 0 obj << -/Dest [ 906 0 R /XYZ 40.01575 675.7008 0 ] /Next 1189 0 R /Parent 1170 0 R /Prev 1187 0 R /Title (ept_finder module) +/Dest [ 903 0 R /XYZ 40.01575 239.1008 0 ] /Next 1189 0 R /Parent 1167 0 R /Prev 1187 0 R /Title (msr_fuzz module) >> endobj 1189 0 obj << -/Dest [ 906 0 R /XYZ 40.01575 305.1008 0 ] /Next 1190 0 R /Parent 1170 0 R /Prev 1188 0 R /Title (hypercallfuzz module) +/Dest [ 904 0 R /XYZ 40.01575 775.7008 0 ] /Next 1190 0 R /Parent 1167 0 R /Prev 1188 0 R /Title (pcie_fuzz module) >> endobj 1190 0 obj << -/Dest [ 907 0 R /XYZ 40.01575 627.7008 0 ] /Next 1191 0 R /Parent 1170 0 R /Prev 1189 0 R /Title (iofuzz module) +/Dest [ 904 0 R /XYZ 40.01575 375.1008 0 ] /Next 1191 0 R /Parent 1167 0 R /Prev 1189 0 R /Title (pcie_overlap_fuzz module) >> endobj 1191 0 obj << -/Dest [ 907 0 R /XYZ 40.01575 443.1008 0 ] /Next 1192 0 R /Parent 1170 0 R /Prev 1190 0 R /Title (msr_fuzz module) +/Dest [ 906 0 R /XYZ 40.01575 775.7008 0 ] /Parent 1167 0 R /Prev 1190 0 R /Title (venom module) >> endobj 1192 0 obj << -/Dest [ 907 0 R /XYZ 40.01575 258.5008 0 ] /Next 1193 0 R /Parent 1170 0 R /Prev 1191 0 R /Title (pcie_fuzz module) +/Dest [ 906 0 R /XYZ 40.01575 579.1008 0 ] /Parent 952 0 R /Prev 1112 0 R /Title (Writing Your Own Modules) >> endobj 1193 0 obj << -/Dest [ 909 0 R /XYZ 40.01575 555.7008 0 ] /Next 1194 0 R /Parent 1170 0 R /Prev 1192 0 R /Title (pcie_overlap_fuzz module) ->> -endobj -1194 0 obj -<< -/Dest [ 909 0 R /XYZ 40.01575 239.1008 0 ] /Parent 1170 0 R /Prev 1193 0 R /Title (venom module) ->> -endobj -1195 0 obj -<< -/Dest [ 911 0 R /XYZ 40.01575 775.7008 0 ] /Parent 955 0 R /Prev 1115 0 R /Title (Writing Your Own Modules) ->> -endobj -1196 0 obj -<< /Count 145 /Kids [ 5 0 R 80 0 R 160 0 R 239 0 R 318 0 R 397 0 R 476 0 R 489 0 R 499 0 R 512 0 R 520 0 R 522 0 R 533 0 R 536 0 R 541 0 R 546 0 R 548 0 R 549 0 R 550 0 R 551 0 R 552 0 R 553 0 R 555 0 R 556 0 R 558 0 R 562 0 R 567 0 R 570 0 R 574 0 R 581 0 R 586 0 R 590 0 R 592 0 R 593 0 R 594 0 R 595 0 R 596 0 R 597 0 R 598 0 R 599 0 R - 600 0 R 601 0 R 602 0 R 603 0 R 604 0 R 605 0 R 606 0 R 607 0 R 609 0 R 615 0 R - 634 0 R 641 0 R 646 0 R 653 0 R 655 0 R 658 0 R 660 0 R 662 0 R 665 0 R 667 0 R - 669 0 R 671 0 R 672 0 R 679 0 R 682 0 R 685 0 R 689 0 R 692 0 R 700 0 R 709 0 R - 711 0 R 712 0 R 713 0 R 717 0 R 725 0 R 728 0 R 730 0 R 736 0 R 739 0 R 740 0 R - 741 0 R 745 0 R 750 0 R 754 0 R 755 0 R 757 0 R 758 0 R 760 0 R 761 0 R 763 0 R - 764 0 R 766 0 R 767 0 R 769 0 R 770 0 R 771 0 R 772 0 R 774 0 R 775 0 R 776 0 R - 777 0 R 779 0 R 780 0 R 783 0 R 791 0 R 798 0 R 802 0 R 803 0 R 804 0 R 805 0 R - 806 0 R 807 0 R 808 0 R 815 0 R 822 0 R 828 0 R 832 0 R 836 0 R 840 0 R 844 0 R - 848 0 R 857 0 R 858 0 R 863 0 R 869 0 R 872 0 R 875 0 R 876 0 R 878 0 R 879 0 R - 880 0 R 881 0 R 882 0 R 885 0 R 888 0 R 892 0 R 894 0 R 897 0 R 899 0 R 901 0 R - 904 0 R 906 0 R 907 0 R 909 0 R 911 0 R ] /Type /Pages + 600 0 R 601 0 R 602 0 R 603 0 R 604 0 R 605 0 R 606 0 R 607 0 R 609 0 R 616 0 R + 634 0 R 642 0 R 647 0 R 653 0 R 655 0 R 658 0 R 661 0 R 663 0 R 665 0 R 667 0 R + 669 0 R 671 0 R 675 0 R 680 0 R 684 0 R 687 0 R 690 0 R 695 0 R 708 0 R 710 0 R + 711 0 R 712 0 R 716 0 R 724 0 R 727 0 R 729 0 R 736 0 R 738 0 R 739 0 R 740 0 R + 744 0 R 749 0 R 753 0 R 754 0 R 756 0 R 757 0 R 759 0 R 760 0 R 762 0 R 764 0 R + 765 0 R 766 0 R 768 0 R 769 0 R 770 0 R 771 0 R 773 0 R 774 0 R 775 0 R 776 0 R + 777 0 R 778 0 R 780 0 R 789 0 R 797 0 R 798 0 R 799 0 R 800 0 R 801 0 R 802 0 R + 803 0 R 809 0 R 812 0 R 818 0 R 825 0 R 828 0 R 834 0 R 838 0 R 840 0 R 844 0 R + 850 0 R 854 0 R 858 0 R 860 0 R 868 0 R 870 0 R 872 0 R 874 0 R 875 0 R 876 0 R + 877 0 R 878 0 R 880 0 R 883 0 R 887 0 R 889 0 R 892 0 R 895 0 R 897 0 R 900 0 R + 902 0 R 903 0 R 904 0 R 906 0 R 908 0 R ] /Type /Pages >> endobj -1197 0 obj +1194 0 obj << -/Length 890 +/Length 892 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -7141,7 +7127,7 @@ n -10 0 525.2441 24 re B* Q q 0 .443137 .772549 rg -BT 1 0 0 1 0 3 Tm /F2 15 Tf 18 TL 212.1795 0 Td (version 1.7.0) Tj T* -212.1795 0 Td ET +BT 1 0 0 1 0 3 Tm /F2 15 Tf 18 TL 212.1795 0 Td (version 1.7.1) Tj T* -212.1795 0 Td ET Q Q q @@ -7165,7 +7151,7 @@ q 1 0 0 1 40.01575 523.9114 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL 226.767 0 Td (July 29, 2021) Tj T* -226.767 0 Td ET +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL 219.552 0 Td (August 27, 2021) Tj T* -219.552 0 Td ET Q Q q @@ -7174,7 +7160,7 @@ Q endstream endobj -1198 0 obj +1195 0 obj << /Length 8592 >> @@ -7699,7 +7685,7 @@ Q endstream endobj -1199 0 obj +1196 0 obj << /Length 8955 >> @@ -8232,7 +8218,7 @@ Q endstream endobj -1200 0 obj +1197 0 obj << /Length 8770 >> @@ -8448,7 +8434,7 @@ q 1 0 0 1 443.2441 417 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (48) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (47) Tj T* -60.88 0 Td ET Q Q q @@ -8474,7 +8460,7 @@ q 1 0 0 1 443.2441 381 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (49) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (48) Tj T* -60.88 0 Td ET Q Q q @@ -8500,7 +8486,7 @@ q 1 0 0 1 443.2441 345 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (50) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (49) Tj T* -60.88 0 Td ET Q Q q @@ -8526,7 +8512,7 @@ q 1 0 0 1 443.2441 309 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (51) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (50) Tj T* -60.88 0 Td ET Q Q q @@ -8552,7 +8538,7 @@ q 1 0 0 1 443.2441 273 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (52) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (51) Tj T* -60.88 0 Td ET Q Q q @@ -8565,7 +8551,7 @@ q 1 0 0 1 443.2441 255 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (53) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (52) Tj T* -60.88 0 Td ET Q Q q @@ -8578,7 +8564,7 @@ q 1 0 0 1 443.2441 237 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (55) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (54) Tj T* -60.88 0 Td ET Q Q q @@ -8604,7 +8590,7 @@ q 1 0 0 1 443.2441 201 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (58) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (57) Tj T* -60.88 0 Td ET Q Q q @@ -8617,7 +8603,7 @@ q 1 0 0 1 443.2441 183 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (59) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (58) Tj T* -60.88 0 Td ET Q Q q @@ -8643,7 +8629,7 @@ q 1 0 0 1 443.2441 147 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (60) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (59) Tj T* -60.88 0 Td ET Q Q q @@ -8656,7 +8642,7 @@ q 1 0 0 1 443.2441 129 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (61) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (60) Tj T* -60.88 0 Td ET Q Q q @@ -8669,7 +8655,7 @@ q 1 0 0 1 443.2441 111 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (61) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (60) Tj T* -60.88 0 Td ET Q Q q @@ -8682,7 +8668,7 @@ q 1 0 0 1 443.2441 93 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (62) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (61) Tj T* -60.88 0 Td ET Q Q q @@ -8695,7 +8681,7 @@ q 1 0 0 1 443.2441 75 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (64) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (63) Tj T* -60.88 0 Td ET Q Q q @@ -8708,7 +8694,7 @@ q 1 0 0 1 443.2441 57 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (64) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (63) Tj T* -60.88 0 Td ET Q Q q @@ -8721,7 +8707,7 @@ q 1 0 0 1 443.2441 39 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (64) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (63) Tj T* -60.88 0 Td ET Q Q q @@ -8734,7 +8720,7 @@ q 1 0 0 1 443.2441 21 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (65) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (64) Tj T* -60.88 0 Td ET Q Q q @@ -8747,7 +8733,7 @@ q 1 0 0 1 443.2441 3 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (66) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (65) Tj T* -60.88 0 Td ET Q Q q @@ -8764,7 +8750,7 @@ Q endstream endobj -1201 0 obj +1198 0 obj << /Length 8838 >> @@ -8785,7 +8771,7 @@ q 1 0 0 1 443.2441 687 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (67) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (66) Tj T* -60.88 0 Td ET Q Q q @@ -8798,7 +8784,7 @@ q 1 0 0 1 443.2441 669 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (67) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (66) Tj T* -60.88 0 Td ET Q Q q @@ -8811,7 +8797,7 @@ q 1 0 0 1 443.2441 651 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (68) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (67) Tj T* -60.88 0 Td ET Q Q q @@ -8824,7 +8810,7 @@ q 1 0 0 1 443.2441 633 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (69) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (68) Tj T* -60.88 0 Td ET Q Q q @@ -8837,7 +8823,7 @@ q 1 0 0 1 443.2441 615 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (74) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (73) Tj T* -60.88 0 Td ET Q Q q @@ -8850,7 +8836,7 @@ q 1 0 0 1 443.2441 597 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (75) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (74) Tj T* -60.88 0 Td ET Q Q q @@ -8863,7 +8849,7 @@ q 1 0 0 1 443.2441 579 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (77) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (76) Tj T* -60.88 0 Td ET Q Q q @@ -8876,7 +8862,7 @@ q 1 0 0 1 443.2441 561 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (76) Tj T* -60.88 0 Td ET Q Q q @@ -8889,7 +8875,7 @@ q 1 0 0 1 443.2441 543 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (77) Tj T* -60.88 0 Td ET Q Q q @@ -8902,7 +8888,7 @@ q 1 0 0 1 443.2441 525 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8915,7 +8901,7 @@ q 1 0 0 1 443.2441 507 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8928,7 +8914,7 @@ q 1 0 0 1 443.2441 489 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8941,7 +8927,7 @@ q 1 0 0 1 443.2441 471 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8954,7 +8940,7 @@ q 1 0 0 1 443.2441 453 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8967,7 +8953,7 @@ q 1 0 0 1 443.2441 435 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (78) Tj T* -60.88 0 Td ET Q Q q @@ -8980,7 +8966,7 @@ q 1 0 0 1 443.2441 417 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (80) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET Q Q q @@ -8993,7 +8979,7 @@ q 1 0 0 1 443.2441 399 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (80) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET Q Q q @@ -9006,7 +8992,7 @@ q 1 0 0 1 443.2441 381 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (80) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (79) Tj T* -60.88 0 Td ET Q Q q @@ -9019,7 +9005,7 @@ q 1 0 0 1 443.2441 363 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (82) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (81) Tj T* -60.88 0 Td ET Q Q q @@ -9032,7 +9018,7 @@ q 1 0 0 1 443.2441 345 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (82) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (81) Tj T* -60.88 0 Td ET Q Q q @@ -9045,7 +9031,7 @@ q 1 0 0 1 443.2441 327 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (83) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (82) Tj T* -60.88 0 Td ET Q Q q @@ -9058,7 +9044,7 @@ q 1 0 0 1 443.2441 309 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (83) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (82) Tj T* -60.88 0 Td ET Q Q q @@ -9071,7 +9057,7 @@ q 1 0 0 1 443.2441 291 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (85) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (84) Tj T* -60.88 0 Td ET Q Q q @@ -9084,7 +9070,7 @@ q 1 0 0 1 443.2441 273 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (85) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (84) Tj T* -60.88 0 Td ET Q Q q @@ -9097,7 +9083,7 @@ q 1 0 0 1 443.2441 255 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (86) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (84) Tj T* -60.88 0 Td ET Q Q q @@ -9110,7 +9096,7 @@ q 1 0 0 1 443.2441 237 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (86) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (85) Tj T* -60.88 0 Td ET Q Q q @@ -9123,7 +9109,7 @@ q 1 0 0 1 443.2441 219 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (90) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (89) Tj T* -60.88 0 Td ET Q Q q @@ -9136,7 +9122,7 @@ q 1 0 0 1 443.2441 201 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (90) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (89) Tj T* -60.88 0 Td ET Q Q q @@ -9149,7 +9135,7 @@ q 1 0 0 1 443.2441 183 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (92) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (91) Tj T* -60.88 0 Td ET Q Q q @@ -9162,7 +9148,7 @@ q 1 0 0 1 443.2441 165 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (92) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (91) Tj T* -60.88 0 Td ET Q Q q @@ -9175,7 +9161,7 @@ q 1 0 0 1 443.2441 147 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (92) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (91) Tj T* -60.88 0 Td ET Q Q q @@ -9188,7 +9174,7 @@ q 1 0 0 1 443.2441 129 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (92) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (91) Tj T* -60.88 0 Td ET Q Q q @@ -9201,7 +9187,7 @@ q 1 0 0 1 443.2441 111 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (92) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (91) Tj T* -60.88 0 Td ET Q Q q @@ -9214,7 +9200,7 @@ q 1 0 0 1 443.2441 93 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (94) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (93) Tj T* -60.88 0 Td ET Q Q q @@ -9227,7 +9213,7 @@ q 1 0 0 1 443.2441 75 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (94) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (93) Tj T* -60.88 0 Td ET Q Q q @@ -9240,7 +9226,7 @@ q 1 0 0 1 443.2441 57 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (96) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (95) Tj T* -60.88 0 Td ET Q Q q @@ -9253,7 +9239,7 @@ q 1 0 0 1 443.2441 39 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (96) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (95) Tj T* -60.88 0 Td ET Q Q q @@ -9266,7 +9252,7 @@ q 1 0 0 1 443.2441 21 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (96) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (95) Tj T* -60.88 0 Td ET Q Q q @@ -9279,7 +9265,7 @@ q 1 0 0 1 443.2441 3 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (98) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (97) Tj T* -60.88 0 Td ET Q Q q @@ -9296,7 +9282,7 @@ Q endstream endobj -1202 0 obj +1199 0 obj << /Length 8862 >> @@ -9317,7 +9303,7 @@ q 1 0 0 1 443.2441 687 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (98) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (97) Tj T* -60.88 0 Td ET Q Q q @@ -9330,7 +9316,7 @@ q 1 0 0 1 443.2441 669 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (99) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (97) Tj T* -60.88 0 Td ET Q Q q @@ -9343,7 +9329,7 @@ q 1 0 0 1 443.2441 651 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (99) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (97) Tj T* -60.88 0 Td ET Q Q q @@ -9356,7 +9342,7 @@ q 1 0 0 1 443.2441 633 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (99) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (98) Tj T* -60.88 0 Td ET Q Q q @@ -9369,7 +9355,7 @@ q 1 0 0 1 443.2441 615 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (99) Tj T* -60.88 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 60.88 0 Td (98) Tj T* -60.88 0 Td ET Q Q q @@ -9382,7 +9368,7 @@ q 1 0 0 1 443.2441 597 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9395,7 +9381,7 @@ q 1 0 0 1 443.2441 579 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9408,7 +9394,7 @@ q 1 0 0 1 443.2441 561 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9421,7 +9407,7 @@ q 1 0 0 1 443.2441 543 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9434,7 +9420,7 @@ q 1 0 0 1 443.2441 525 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9447,7 +9433,7 @@ q 1 0 0 1 443.2441 507 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9460,7 +9446,7 @@ q 1 0 0 1 443.2441 489 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (102) Tj T* -55.32 0 Td ET Q Q q @@ -9473,7 +9459,7 @@ q 1 0 0 1 443.2441 471 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (104) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (103) Tj T* -55.32 0 Td ET Q Q q @@ -9486,7 +9472,7 @@ q 1 0 0 1 443.2441 453 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (105) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (103) Tj T* -55.32 0 Td ET Q Q q @@ -9499,7 +9485,7 @@ q 1 0 0 1 443.2441 435 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (106) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (105) Tj T* -55.32 0 Td ET Q Q q @@ -9512,7 +9498,7 @@ q 1 0 0 1 443.2441 417 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (106) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (105) Tj T* -55.32 0 Td ET Q Q q @@ -9525,7 +9511,7 @@ q 1 0 0 1 443.2441 399 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (105) Tj T* -55.32 0 Td ET Q Q q @@ -9538,7 +9524,7 @@ q 1 0 0 1 443.2441 381 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (105) Tj T* -55.32 0 Td ET Q Q q @@ -9551,7 +9537,7 @@ q 1 0 0 1 443.2441 363 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (106) Tj T* -55.32 0 Td ET Q Q q @@ -9564,7 +9550,7 @@ q 1 0 0 1 443.2441 345 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (108) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET Q Q q @@ -9577,7 +9563,7 @@ q 1 0 0 1 443.2441 327 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (108) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET Q Q q @@ -9590,7 +9576,7 @@ q 1 0 0 1 443.2441 309 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (109) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (107) Tj T* -55.32 0 Td ET Q Q q @@ -9603,7 +9589,7 @@ q 1 0 0 1 443.2441 291 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (109) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (108) Tj T* -55.32 0 Td ET Q Q q @@ -9616,7 +9602,7 @@ q 1 0 0 1 443.2441 273 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (109) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (108) Tj T* -55.32 0 Td ET Q Q q @@ -9629,7 +9615,7 @@ q 1 0 0 1 443.2441 255 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (110) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (109) Tj T* -55.32 0 Td ET Q Q q @@ -9642,7 +9628,7 @@ q 1 0 0 1 443.2441 237 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (110) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (109) Tj T* -55.32 0 Td ET Q Q q @@ -9655,7 +9641,7 @@ q 1 0 0 1 443.2441 219 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (111) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (110) Tj T* -55.32 0 Td ET Q Q q @@ -9668,7 +9654,7 @@ q 1 0 0 1 443.2441 201 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (112) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (110) Tj T* -55.32 0 Td ET Q Q q @@ -9681,7 +9667,7 @@ q 1 0 0 1 443.2441 183 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (112) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (111) Tj T* -55.32 0 Td ET Q Q q @@ -9707,7 +9693,7 @@ q 1 0 0 1 443.2441 147 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (113) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (112) Tj T* -55.32 0 Td ET Q Q q @@ -9720,7 +9706,7 @@ q 1 0 0 1 443.2441 129 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (113) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (112) Tj T* -55.32 0 Td ET Q Q q @@ -9746,7 +9732,7 @@ q 1 0 0 1 443.2441 93 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (114) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (113) Tj T* -55.32 0 Td ET Q Q q @@ -9772,7 +9758,7 @@ q 1 0 0 1 443.2441 57 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (115) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (114) Tj T* -55.32 0 Td ET Q Q q @@ -9785,7 +9771,7 @@ q 1 0 0 1 443.2441 39 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (115) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (114) Tj T* -55.32 0 Td ET Q Q q @@ -9811,7 +9797,7 @@ q 1 0 0 1 443.2441 3 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (115) Tj T* -55.32 0 Td ET Q Q q @@ -9828,7 +9814,7 @@ Q endstream endobj -1203 0 obj +1200 0 obj << /Length 8852 >> @@ -9849,7 +9835,7 @@ q 1 0 0 1 443.2441 687 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (115) Tj T* -55.32 0 Td ET Q Q q @@ -9875,7 +9861,7 @@ q 1 0 0 1 443.2441 651 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9888,7 +9874,7 @@ q 1 0 0 1 443.2441 633 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9901,7 +9887,7 @@ q 1 0 0 1 443.2441 615 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9914,7 +9900,7 @@ q 1 0 0 1 443.2441 597 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9928,7 +9914,7 @@ q 1 0 0 1 443.2441 579 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9941,7 +9927,7 @@ q 1 0 0 1 443.2441 561 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (116) Tj T* -55.32 0 Td ET Q Q q @@ -9954,7 +9940,7 @@ q 1 0 0 1 443.2441 543 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (118) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET Q Q q @@ -9967,7 +9953,7 @@ q 1 0 0 1 443.2441 525 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (118) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (117) Tj T* -55.32 0 Td ET Q Q q @@ -9980,7 +9966,7 @@ q 1 0 0 1 443.2441 507 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (119) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (118) Tj T* -55.32 0 Td ET Q Q q @@ -9993,7 +9979,7 @@ q 1 0 0 1 443.2441 489 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (119) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (118) Tj T* -55.32 0 Td ET Q Q q @@ -10019,7 +10005,7 @@ q 1 0 0 1 443.2441 453 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (121) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (120) Tj T* -55.32 0 Td ET Q Q q @@ -10032,7 +10018,7 @@ q 1 0 0 1 443.2441 435 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (121) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (120) Tj T* -55.32 0 Td ET Q Q q @@ -10058,7 +10044,7 @@ q 1 0 0 1 443.2441 399 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (123) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (122) Tj T* -55.32 0 Td ET Q Q q @@ -10071,7 +10057,7 @@ q 1 0 0 1 443.2441 381 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (124) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (123) Tj T* -55.32 0 Td ET Q Q q @@ -10136,7 +10122,7 @@ q 1 0 0 1 443.2441 291 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (126) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (125) Tj T* -55.32 0 Td ET Q Q q @@ -10162,7 +10148,7 @@ q 1 0 0 1 443.2441 255 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (127) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (126) Tj T* -55.32 0 Td ET Q Q q @@ -10188,7 +10174,7 @@ q 1 0 0 1 443.2441 219 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (128) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (127) Tj T* -55.32 0 Td ET Q Q q @@ -10201,7 +10187,7 @@ q 1 0 0 1 443.2441 201 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (130) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (129) Tj T* -55.32 0 Td ET Q Q q @@ -10240,7 +10226,7 @@ q 1 0 0 1 443.2441 147 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (131) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (130) Tj T* -55.32 0 Td ET Q Q q @@ -10253,7 +10239,7 @@ q 1 0 0 1 443.2441 129 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (131) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (130) Tj T* -55.32 0 Td ET Q Q q @@ -10266,7 +10252,7 @@ q 1 0 0 1 443.2441 111 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (131) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (130) Tj T* -55.32 0 Td ET Q Q q @@ -10292,7 +10278,7 @@ q 1 0 0 1 443.2441 75 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (132) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (131) Tj T* -55.32 0 Td ET Q Q q @@ -10331,7 +10317,7 @@ q 1 0 0 1 443.2441 21 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (134) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (133) Tj T* -55.32 0 Td ET Q Q q @@ -10344,7 +10330,7 @@ q 1 0 0 1 443.2441 3 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (134) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (133) Tj T* -55.32 0 Td ET Q Q q @@ -10361,7 +10347,7 @@ Q endstream endobj -1204 0 obj +1201 0 obj << /Length 1573 >> @@ -10382,7 +10368,7 @@ q 1 0 0 1 443.2441 93 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (135) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (134) Tj T* -55.32 0 Td ET Q Q q @@ -10395,7 +10381,7 @@ q 1 0 0 1 443.2441 75 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (135) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (134) Tj T* -55.32 0 Td ET Q Q q @@ -10421,7 +10407,7 @@ q 1 0 0 1 443.2441 39 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (136) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (135) Tj T* -55.32 0 Td ET Q Q q @@ -10447,7 +10433,7 @@ q 1 0 0 1 443.2441 3 cm q 0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (137) Tj T* -55.32 0 Td ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 55.32 0 Td (136) Tj T* -55.32 0 Td ET Q Q q @@ -10467,7 +10453,7 @@ Q endstream endobj -1205 0 obj +1202 0 obj << /Length 4513 >> @@ -10667,7 +10653,7 @@ Q endstream endobj -1206 0 obj +1203 0 obj << /Length 6073 >> @@ -11039,7 +11025,7 @@ Q endstream endobj -1207 0 obj +1204 0 obj << /Length 7930 >> @@ -11579,7 +11565,7 @@ Q endstream endobj -1208 0 obj +1205 0 obj << /Length 10688 >> @@ -12456,7 +12442,7 @@ Q endstream endobj -1209 0 obj +1206 0 obj << /Length 6183 >> @@ -12872,7 +12858,7 @@ Q endstream endobj -1210 0 obj +1207 0 obj << /Length 6337 >> @@ -13283,7 +13269,7 @@ Q endstream endobj -1211 0 obj +1208 0 obj << /Length 6203 >> @@ -13669,7 +13655,7 @@ Q endstream endobj -1212 0 obj +1209 0 obj << /Length 6576 >> @@ -14132,7 +14118,7 @@ Q endstream endobj -1213 0 obj +1210 0 obj << /Length 6564 >> @@ -14501,7 +14487,7 @@ Q endstream endobj -1214 0 obj +1211 0 obj << /Length 3260 >> @@ -14681,7 +14667,7 @@ Q endstream endobj -1215 0 obj +1212 0 obj << /Length 5069 >> @@ -14828,7 +14814,7 @@ Q endstream endobj -1216 0 obj +1213 0 obj << /Length 7954 >> @@ -15262,7 +15248,7 @@ Q endstream endobj -1217 0 obj +1214 0 obj << /Length 5890 >> @@ -15529,7 +15515,7 @@ Q endstream endobj -1218 0 obj +1215 0 obj << /Length 7126 >> @@ -15872,7 +15858,7 @@ Q endstream endobj -1219 0 obj +1216 0 obj << /Length 4068 >> @@ -16123,7 +16109,7 @@ Q endstream endobj -1220 0 obj +1217 0 obj << /Length 6001 >> @@ -16480,7 +16466,7 @@ Q endstream endobj -1221 0 obj +1218 0 obj << /Length 5845 >> @@ -16797,7 +16783,7 @@ Q endstream endobj -1222 0 obj +1219 0 obj << /Length 5235 >> @@ -17118,7 +17104,7 @@ Q endstream endobj -1223 0 obj +1220 0 obj << /Length 4554 >> @@ -17328,7 +17314,7 @@ Q endstream endobj -1224 0 obj +1221 0 obj << /Length 6169 >> @@ -17666,7 +17652,7 @@ Q endstream endobj -1225 0 obj +1222 0 obj << /Length 4844 >> @@ -17886,7 +17872,7 @@ Q endstream endobj -1226 0 obj +1223 0 obj << /Length 6060 >> @@ -18241,7 +18227,7 @@ Q endstream endobj -1227 0 obj +1224 0 obj << /Length 5681 >> @@ -18574,7 +18560,7 @@ Q endstream endobj -1228 0 obj +1225 0 obj << /Length 5116 >> @@ -18859,7 +18845,7 @@ Q endstream endobj -1229 0 obj +1226 0 obj << /Length 6114 >> @@ -19190,7 +19176,7 @@ Q endstream endobj -1230 0 obj +1227 0 obj << /Length 6133 >> @@ -19487,7 +19473,7 @@ Q endstream endobj -1231 0 obj +1228 0 obj << /Length 5404 >> @@ -19785,7 +19771,7 @@ Q endstream endobj -1232 0 obj +1229 0 obj << /Length 6726 >> @@ -20151,7 +20137,7 @@ Q endstream endobj -1233 0 obj +1230 0 obj << /Length 5973 >> @@ -20445,7 +20431,7 @@ Q endstream endobj -1234 0 obj +1231 0 obj << /Length 6836 >> @@ -20776,7 +20762,7 @@ Q endstream endobj -1235 0 obj +1232 0 obj << /Length 6465 >> @@ -21049,7 +21035,7 @@ Q endstream endobj -1236 0 obj +1233 0 obj << /Length 6324 >> @@ -21363,7 +21349,7 @@ Q endstream endobj -1237 0 obj +1234 0 obj << /Length 6542 >> @@ -21632,7 +21618,7 @@ Q endstream endobj -1238 0 obj +1235 0 obj << /Length 6334 >> @@ -21899,7 +21885,7 @@ Q endstream endobj -1239 0 obj +1236 0 obj << /Length 5379 >> @@ -22153,7 +22139,7 @@ Q endstream endobj -1240 0 obj +1237 0 obj << /Length 6318 >> @@ -22463,7 +22449,7 @@ Q endstream endobj -1241 0 obj +1238 0 obj << /Length 5783 >> @@ -22753,7 +22739,7 @@ Q endstream endobj -1242 0 obj +1239 0 obj << /Length 6030 >> @@ -23050,7 +23036,7 @@ Q endstream endobj -1243 0 obj +1240 0 obj << /Length 6409 >> @@ -23294,7 +23280,7 @@ Q endstream endobj -1244 0 obj +1241 0 obj << /Length 6077 >> @@ -23551,7 +23537,7 @@ Q endstream endobj -1245 0 obj +1242 0 obj << /Length 5797 >> @@ -23823,9 +23809,9 @@ Q endstream endobj -1246 0 obj +1243 0 obj << -/Length 9485 +/Length 9912 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -23930,28 +23916,11 @@ Q q 1 0 0 1 40.01575 499.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (AcpiRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 487.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 481.7008 cm -Q -q -1 0 0 1 40.01575 463.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RSDP) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (table_content) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 50.01575 487.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -23959,16 +23928,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 445.7008 cm +1 0 0 1 50.01575 481.7008 cm Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 50.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_RSDP_valid) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 378.1008 cm +1 0 0 1 40.01575 414.1008 cm q 1 1 1 RG .3 w @@ -23980,22 +23949,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (acpi_tables module) Tj T* ET Q Q q -1 0 0 1 40.01575 360.1008 cm +1 0 0 1 40.01575 396.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (HAL component decoding various ACPI tables) Tj T* ET Q Q q -1 0 0 1 40.01575 354.1008 cm +1 0 0 1 40.01575 390.1008 cm Q q -1 0 0 1 40.01575 336.1008 cm +1 0 0 1 40.01575 372.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 324.1008 cm +1 0 0 1 50.01575 360.1008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -24003,25 +23972,25 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 318.1008 cm +1 0 0 1 50.01575 354.1008 cm Q q -1 0 0 1 50.01575 300.1008 cm +1 0 0 1 50.01575 336.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 294.1008 cm +1 0 0 1 40.01575 330.1008 cm Q q -1 0 0 1 40.01575 252.1008 cm +1 0 0 1 40.01575 288.1008 cm q BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_GICC_CPU) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CPUIntNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ParkingProtocolVersion) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PerformanceInterruptGSIV) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ParkedAddress) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PhysicalAddress) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GICV) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GICH) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (VGICMaintenanceINterrupt) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GICRBaseAddress) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MPIDR) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 240.1008 cm +1 0 0 1 50.01575 276.1008 cm q .933333 1 .8 rg n 33.35 0 288 12 re f* @@ -24029,16 +23998,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 234.1008 cm +1 0 0 1 40.01575 270.1008 cm Q q -1 0 0 1 40.01575 204.1008 cm +1 0 0 1 40.01575 240.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_GIC_DISTRIBUTOR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PhysicalBaseAddress) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (SystemVectorBase) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved2) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 192.1008 cm +1 0 0 1 50.01575 228.1008 cm q .933333 1 .8 rg n 33.35 0 330 12 re f* @@ -24046,16 +24015,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 186.1008 cm +1 0 0 1 40.01575 222.1008 cm Q q -1 0 0 1 40.01575 156.1008 cm +1 0 0 1 40.01575 192.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_GIC_MSI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GICMSIFrameID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PhysicalBaseAddress) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (SPICount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SPIBase) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 144.1008 cm +1 0 0 1 50.01575 180.1008 cm q .933333 1 .8 rg n 33.35 0 282 12 re f* @@ -24063,20 +24032,37 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 138.1008 cm +1 0 0 1 40.01575 174.1008 cm +Q +q +1 0 0 1 40.01575 144.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_GIC_REDISTRIBUTOR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DiscoverRangeBaseAdd) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DiscoverRangeLength) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 132.1008 cm +q +.933333 1 .8 rg +n 33.35 0 342 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GIC_REDISTRIBUTOR) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 126.1008 cm Q q 1 0 0 1 40.01575 108.1008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_GIC_REDISTRIBUTOR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DiscoverRangeBaseAdd) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DiscoverRangeLength) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Bus) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Source) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 96.10079 cm q .933333 1 .8 rg -n 33.35 0 342 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_GIC_REDISTRIBUTOR) Tj T* ET +n 33.35 0 390 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE) Tj T* ET Q Q q @@ -24085,7 +24071,7 @@ Q q 1 0 0 1 40.01575 72.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Bus) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Source) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_IOAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICAddr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (\)) Tj T* ET Q Q q @@ -24104,9 +24090,9 @@ Q endstream endobj -1247 0 obj +1244 0 obj << -/Length 13168 +/Length 12830 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -24114,8 +24100,8 @@ q 1 0 0 1 50.01575 763.7008 cm q .933333 1 .8 rg -n 33.35 0 390 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_INTERRUPT_SOURSE_OVERRIDE) Tj T* ET +n 33.35 0 276 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOAPIC) Tj T* ET Q Q q @@ -24124,15 +24110,15 @@ Q q 1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_IOAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICAddr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_IOSAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOSAPICAddress) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 727.7008 cm q .933333 1 .8 rg -n 33.35 0 276 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOAPIC) Tj T* ET +n 33.35 0 282 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOSAPIC) Tj T* ET Q Q q @@ -24141,15 +24127,15 @@ Q q 1 0 0 1 40.01575 703.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_IOSAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOSAPICAddress) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalAPICAddress) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 691.7008 cm q .933333 1 .8 rg -n 33.35 0 282 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_IOSAPIC) Tj T* ET +n 33.35 0 372 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE) Tj T* ET Q Q q @@ -24158,15 +24144,15 @@ Q q 1 0 0 1 40.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalAPICAddress) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_LAPIC_NMI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcessorID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalAPICLINT) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 655.7008 cm q .933333 1 .8 rg -n 33.35 0 372 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_ADDRESS_OVERRIDE) Tj T* ET +n 33.35 0 294 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_NMI) Tj T* ET Q Q q @@ -24175,15 +24161,15 @@ Q q 1 0 0 1 40.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_LAPIC_NMI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcessorID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalAPICLINT) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_Lx2APIC_NMI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Localx2APICLINT) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 619.7008 cm q .933333 1 .8 rg -n 33.35 0 294 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_LAPIC_NMI) Tj T* ET +n 33.35 0 306 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_Lx2APIC_NMI) Tj T* ET Q Q q @@ -24192,28 +24178,11 @@ Q q 1 0 0 1 40.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_Lx2APIC_NMI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Localx2APICLINT) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 583.7008 cm -q -.933333 1 .8 rg -n 33.35 0 306 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_Lx2APIC_NMI) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 577.7008 cm -Q -q -1 0 0 1 40.01575 559.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_NMI_SOURCE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSysIntBase) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 50.01575 583.7008 cm q .933333 1 .8 rg n 33.35 0 300 12 re f* @@ -24221,16 +24190,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 541.7008 cm +1 0 0 1 40.01575 577.7008 cm Q q -1 0 0 1 40.01575 511.7008 cm +1 0 0 1 40.01575 547.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PLATFORM_INTERRUPT_SOURCES) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InterruptType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProcID) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ProcEID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IOSAPICVector) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GlobalSystemInterrupt) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PlatIntSourceFlags) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 499.7008 cm +1 0 0 1 50.01575 535.7008 cm q .933333 1 .8 rg n 33.35 0 396 12 re f* @@ -24238,16 +24207,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 493.7008 cm +1 0 0 1 40.01575 529.7008 cm Q q -1 0 0 1 40.01575 475.7008 cm +1 0 0 1 40.01575 511.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PROCESSOR_LAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (APICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 463.7008 cm +1 0 0 1 50.01575 499.7008 cm q .933333 1 .8 rg n 33.35 0 330 12 re f* @@ -24255,20 +24224,37 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 457.7008 cm +1 0 0 1 40.01575 493.7008 cm +Q +q +1 0 0 1 40.01575 463.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PROCESSOR_LSAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalSAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalSAPICEID) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUIDValue) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUIDString) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 451.7008 cm +q +.933333 1 .8 rg +n 33.35 0 336 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_LSAPIC) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 445.7008 cm Q q 1 0 0 1 40.01575 427.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PROCESSOR_LSAPIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalSAPICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocalSAPICEID) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUIDValue) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUIDString) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PROCESSOR_Lx2APIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (x2APICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUID) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 415.7008 cm q .933333 1 .8 rg -n 33.35 0 336 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_LSAPIC) Tj T* ET +n 33.35 0 342 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_Lx2APIC) Tj T* ET Q Q q @@ -24277,15 +24263,15 @@ Q q 1 0 0 1 40.01575 391.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_APIC_PROCESSOR_Lx2APIC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (x2APICID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIProcUID) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_ANDD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIDevNum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIObjectName) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 379.7008 cm q .933333 1 .8 rg -n 33.35 0 342 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_APIC_PROCESSOR_Lx2APIC) Tj T* ET +n 33.35 0 264 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ANDD) Tj T* ET Q Q q @@ -24294,7 +24280,7 @@ Q q 1 0 0 1 40.01575 355.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_ANDD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIDevNum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ACPIObjectName) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_ATSR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SegmentNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceScope) Tj 0 0 0 rg (\)) Tj T* ET Q Q q @@ -24302,41 +24288,41 @@ q q .933333 1 .8 rg n 33.35 0 264 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ANDD) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ATSR) Tj T* ET Q Q q 1 0 0 1 40.01575 337.7008 cm Q q -1 0 0 1 40.01575 319.7008 cm +1 0 0 1 40.01575 307.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_ATSR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SegmentNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceScope) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_DRHD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SegmentNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RegisterBaseAddr) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DeviceScope) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 307.7008 cm +1 0 0 1 50.01575 295.7008 cm q .933333 1 .8 rg n 33.35 0 264 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_ATSR) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DRHD) Tj T* ET Q Q q -1 0 0 1 40.01575 301.7008 cm +1 0 0 1 40.01575 289.7008 cm Q q 1 0 0 1 40.01575 271.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_DRHD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SegmentNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RegisterBaseAddr) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DeviceScope) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_DeviceScope) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EnumerationID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StartBusNum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Path) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 259.7008 cm q .933333 1 .8 rg -n 33.35 0 264 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DRHD) Tj T* ET +n 33.35 0 306 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DeviceScope) Tj T* ET Q Q q @@ -24345,28 +24331,11 @@ Q q 1 0 0 1 40.01575 235.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_DeviceScope) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EnumerationID) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StartBusNum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Path) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 223.7008 cm -q -.933333 1 .8 rg -n 33.35 0 306 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE_DMAR_DeviceScope) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 217.7008 cm -Q -q -1 0 0 1 40.01575 199.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_RHSA) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RegisterBaseAddr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProximityDomain) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 187.7008 cm +1 0 0 1 50.01575 223.7008 cm q .933333 1 .8 rg n 33.35 0 264 12 re f* @@ -24374,16 +24343,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 181.7008 cm +1 0 0 1 40.01575 217.7008 cm Q q -1 0 0 1 40.01575 151.7008 cm +1 0 0 1 40.01575 187.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ACPI_TABLE_DMAR_RMRR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SegmentNumber) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RMRBaseAddr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RMRLimitAddr) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DeviceScope) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 139.7008 cm +1 0 0 1 50.01575 175.7008 cm q .933333 1 .8 rg n 33.35 0 264 12 re f* @@ -24391,16 +24360,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 40.01575 133.7008 cm +1 0 0 1 40.01575 169.7008 cm Q q -1 0 0 1 40.01575 115.7008 cm +1 0 0 1 40.01575 151.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (APIC) Tj T* ET Q Q q -1 0 0 1 50.01575 103.7008 cm +1 0 0 1 50.01575 139.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -24408,16 +24377,31 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 97.70079 cm +1 0 0 1 50.01575 133.7008 cm Q q -1 0 0 1 50.01575 79.70079 cm +1 0 0 1 50.01575 115.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_structure_APIC) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (DataStructure) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 73.70079 cm +1 0 0 1 50.01575 109.7008 cm +Q +q +1 0 0 1 50.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 85.70079 cm +Q +q +1 0 0 1 40.01575 67.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BERT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -24435,91 +24419,76 @@ Q endstream endobj -1248 0 obj +1245 0 obj << -/Length 7297 +/Length 7215 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BERT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 727.7008 cm -q .933333 1 .8 rg n 33.35 0 204 12 re f* BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 721.7008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 703.7008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 697.7008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 679.7008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseErrorBlock) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 673.7008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 655.7008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseGenErrorEntries) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 649.7008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 631.7008 cm +1 0 0 1 50.01575 667.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseSectionType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 625.7008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 607.7008 cm +1 0 0 1 50.01575 643.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseTime) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 601.7008 cm +1 0 0 1 40.01575 637.7008 cm Q q -1 0 0 1 40.01575 583.7008 cm +1 0 0 1 40.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BGRT) Tj T* ET Q Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 50.01575 607.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -24527,12 +24496,334 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q +1 0 0 1 50.01575 601.7008 cm +Q +q +1 0 0 1 50.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 577.7008 cm +Q +q +1 0 0 1 40.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (DMAR) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 547.7008 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 517.7008 cm +Q +q +1 0 0 1 40.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EINJ) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 487.7008 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 457.7008 cm +Q +q +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 433.7008 cm +Q +q +1 0 0 1 50.01575 415.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInjection) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 409.7008 cm +Q +q +1 0 0 1 50.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInjectionActionTable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_contents) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (numInjections) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 385.7008 cm +Q +q +1 0 0 1 40.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ERST) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 355.7008 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 349.7008 cm +Q +q +1 0 0 1 50.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 325.7008 cm +Q +q +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseActionTable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (instrCountEntry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 301.7008 cm +Q +q +1 0 0 1 50.01575 283.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 277.7008 cm +Q +q +1 0 0 1 50.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInstructionEntry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 253.7008 cm +Q +q +1 0 0 1 40.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FADT) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 223.7008 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 217.7008 cm +Q +q +1 0 0 1 50.01575 199.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_DSDT_address_to_use) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 193.7008 cm +Q +q +1 0 0 1 50.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 169.7008 cm +Q +q +1 0 0 1 40.01575 151.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (GAS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (table_content) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 139.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 133.7008 cm +Q +q +1 0 0 1 50.01575 115.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_info) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 109.7008 cm +Q +q +1 0 0 1 40.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HEST) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 79.70079 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (44) Tj T* ET +Q +Q + +endstream +endobj +1246 0 obj +<< +/Length 8442 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (machineBankParser) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAMCES) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAMCS) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseErrEntry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseGHESS) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseNMIStructure) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseNotify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 565.7008 cm Q q 1 0 0 1 50.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parsePCIe) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -24541,7 +24832,7 @@ Q q 1 0 0 1 40.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (DMAR) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MSCT) Tj T* ET Q Q q @@ -24562,38 +24853,38 @@ BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Q Q q -1 0 0 1 40.01575 481.7008 cm +1 0 0 1 50.01575 481.7008 cm Q q -1 0 0 1 40.01575 463.7008 cm +1 0 0 1 50.01575 463.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EINJ) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseProx) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (val) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 50.01575 457.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseProxDomInfoStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_contents) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (num) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 445.7008 cm +1 0 0 1 40.01575 433.7008 cm Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 40.01575 415.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (NFIT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (header) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 421.7008 cm -Q -q 1 0 0 1 50.01575 403.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET Q Q q @@ -24602,7 +24893,7 @@ Q q 1 0 0 1 50.01575 379.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInjection) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (flushHintAddrStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -24611,77 +24902,70 @@ Q q 1 0 0 1 50.01575 355.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInjectionActionTable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_contents) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (numInjections) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (interleave) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 349.7008 cm +1 0 0 1 50.01575 349.7008 cm Q q -1 0 0 1 40.01575 331.7008 cm +1 0 0 1 50.01575 331.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ERST) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvdimmBlockDataWindowsRegionStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 319.7008 cm +1 0 0 1 50.01575 325.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvdimmControlRegionStructMark) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 313.7008 cm +1 0 0 1 50.01575 301.7008 cm Q q -1 0 0 1 50.01575 295.7008 cm +1 0 0 1 50.01575 283.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 289.7008 cm +1 0 0 1 50.01575 277.7008 cm Q q -1 0 0 1 50.01575 271.7008 cm +1 0 0 1 50.01575 259.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseActionTable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (instrCountEntry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseMAP) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 265.7008 cm +1 0 0 1 50.01575 253.7008 cm Q q -1 0 0 1 50.01575 247.7008 cm +1 0 0 1 50.01575 235.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseSPA) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 241.7008 cm +1 0 0 1 50.01575 229.7008 cm Q q -1 0 0 1 50.01575 223.7008 cm +1 0 0 1 50.01575 211.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseInstructionEntry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseStructures) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 217.7008 cm -Q -q -1 0 0 1 40.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FADT) Tj T* ET -Q +1 0 0 1 50.01575 205.7008 cm Q q 1 0 0 1 50.01575 187.7008 cm q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (platCapStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -24690,335 +24974,20 @@ Q q 1 0 0 1 50.01575 163.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_DSDT_address_to_use) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 157.7008 cm -Q -q -1 0 0 1 50.01575 139.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 133.7008 cm -Q -q -1 0 0 1 40.01575 115.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (GAS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (table_content) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 103.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_info) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (44) Tj T* ET -Q -Q - -endstream -endobj -1249 0 obj -<< -/Length 8442 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HEST) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 751.7008 cm -q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 745.7008 cm -Q -q -1 0 0 1 50.01575 727.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (machineBankParser) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 721.7008 cm -Q -q -1 0 0 1 50.01575 703.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 697.7008 cm -Q -q -1 0 0 1 50.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAMCES) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 673.7008 cm -Q -q -1 0 0 1 50.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAMCS) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseErrEntry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseGHESS) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseNMIStructure) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 553.7008 cm -Q -q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseNotify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parsePCIe) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 505.7008 cm -Q -q -1 0 0 1 40.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MSCT) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 475.7008 cm -q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 445.7008 cm -Q -q -1 0 0 1 50.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseProx) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (val) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 421.7008 cm -Q -q -1 0 0 1 50.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseProxDomInfoStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_contents) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (num) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 397.7008 cm -Q -q -1 0 0 1 40.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (NFIT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (header) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 367.7008 cm -q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 361.7008 cm -Q -q -1 0 0 1 50.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (flushHintAddrStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (interleave) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 313.7008 cm -Q -q -1 0 0 1 50.01575 295.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvdimmBlockDataWindowsRegionStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvdimmControlRegionStructMark) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 241.7008 cm -Q -q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseMAP) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseSPA) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseStructures) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (platCapStruct) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (smbiosManagementInfo) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tableLen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 121.7008 cm +1 0 0 1 40.01575 157.7008 cm Q q -1 0 0 1 40.01575 103.7008 cm +1 0 0 1 40.01575 139.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RASF) Tj T* ET Q Q q -1 0 0 1 50.01575 91.70079 cm +1 0 0 1 50.01575 127.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -25026,16 +24995,33 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 85.70079 cm +1 0 0 1 50.01575 121.7008 cm Q q -1 0 0 1 50.01575 67.70079 cm +1 0 0 1 50.01575 103.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 66.18898 cm +1 0 0 1 40.01575 97.70079 cm +Q +q +1 0 0 1 40.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RSDT) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 67.70079 cm +q +.933333 1 .8 rg +n 33.35 0 204 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -25053,46 +25039,29 @@ Q endstream endobj -1250 0 obj +1247 0 obj << -/Length 6318 +/Length 6133 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RSDT) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 751.7008 cm -q -.933333 1 .8 rg -n 33.35 0 204 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.acpi_tables.ACPI_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 745.7008 cm -Q -q -1 0 0 1 50.01575 727.7008 cm +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 721.7008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 40.01575 703.7008 cm +1 0 0 1 40.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPMI) Tj T* ET Q Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 727.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -25100,52 +25069,52 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 721.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 703.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 50.01575 697.7008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 50.01575 679.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseAddress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 50.01575 673.7008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 50.01575 655.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseNonUID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm +1 0 0 1 50.01575 649.7008 cm Q q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 50.01575 631.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parseUID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 589.7008 cm +1 0 0 1 40.01575 625.7008 cm Q q -1 0 0 1 40.01575 571.7008 cm +1 0 0 1 40.01575 607.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UEFI_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 559.7008 cm +1 0 0 1 50.01575 595.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -25153,34 +25122,34 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 553.7008 cm +1 0 0 1 50.01575 589.7008 cm Q q -1 0 0 1 50.01575 535.7008 cm +1 0 0 1 50.01575 571.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_commbuf_info) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 529.7008 cm +1 0 0 1 50.01575 565.7008 cm Q q -1 0 0 1 50.01575 511.7008 cm +1 0 0 1 50.01575 547.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 505.7008 cm +1 0 0 1 40.01575 541.7008 cm Q q -1 0 0 1 40.01575 487.7008 cm +1 0 0 1 40.01575 523.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (WSMT) Tj T* ET Q Q q -1 0 0 1 50.01575 475.7008 cm +1 0 0 1 50.01575 511.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -25188,52 +25157,52 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 469.7008 cm +1 0 0 1 50.01575 505.7008 cm Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 50.01575 487.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (COMM_BUFFER_NESTED_PTR_PROTECTION) Tj /F4 10 Tf ( = 2) Tj T* ET Q Q q -1 0 0 1 50.01575 445.7008 cm +1 0 0 1 50.01575 481.7008 cm Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 50.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FIXED_COMM_BUFFERS) Tj /F4 10 Tf ( = 1) Tj T* ET Q Q q -1 0 0 1 50.01575 421.7008 cm +1 0 0 1 50.01575 457.7008 cm Q q -1 0 0 1 50.01575 403.7008 cm +1 0 0 1 50.01575 439.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SYSTEM_RESOURCE_PROTECTION) Tj /F4 10 Tf ( = 4) Tj T* ET Q Q q -1 0 0 1 50.01575 397.7008 cm +1 0 0 1 50.01575 433.7008 cm Q q -1 0 0 1 50.01575 379.7008 cm +1 0 0 1 50.01575 415.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 373.7008 cm +1 0 0 1 40.01575 409.7008 cm Q q -1 0 0 1 40.01575 355.7008 cm +1 0 0 1 40.01575 391.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XSDT) Tj T* ET Q Q q -1 0 0 1 50.01575 343.7008 cm +1 0 0 1 50.01575 379.7008 cm q .933333 1 .8 rg n 33.35 0 204 12 re f* @@ -25241,16 +25210,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.a Q Q q -1 0 0 1 50.01575 337.7008 cm +1 0 0 1 50.01575 373.7008 cm Q q -1 0 0 1 50.01575 319.7008 cm +1 0 0 1 50.01575 355.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_content) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 270.1008 cm +1 0 0 1 40.01575 306.1008 cm q 1 1 1 RG .3 w @@ -25262,20 +25231,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cmos module) Tj T* ET Q Q q -1 0 0 1 40.01575 252.1008 cm +1 0 0 1 40.01575 288.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (CMOS memory specific functions \(dump, read/write\)) Tj T* ET Q Q q -1 0 0 1 40.01575 236.1008 cm +1 0 0 1 40.01575 272.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 159.1008 cm +1 0 0 1 40.01575 195.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -25305,16 +25274,16 @@ Q Q Q q -1 0 0 1 40.01575 153.1008 cm +1 0 0 1 40.01575 189.1008 cm Q q -1 0 0 1 40.01575 135.1008 cm +1 0 0 1 40.01575 171.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CMOS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 123.1008 cm +1 0 0 1 50.01575 159.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -25322,25 +25291,34 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 117.1008 cm +1 0 0 1 50.01575 153.1008 cm Q q -1 0 0 1 50.01575 99.10079 cm +1 0 0 1 50.01575 135.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 93.10079 cm +1 0 0 1 50.01575 129.1008 cm Q q -1 0 0 1 50.01575 75.10079 cm +1 0 0 1 50.01575 111.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_high) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 69.10079 cm +1 0 0 1 50.01575 105.1008 cm +Q +q +1 0 0 1 50.01575 87.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_low) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 81.10079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -25358,16 +25336,16 @@ Q endstream endobj -1251 0 obj +1248 0 obj << -/Length 6185 +/Length 6110 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_low) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cmos_high) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -25376,7 +25354,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cmos_high) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cmos_low) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -25385,7 +25363,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cmos_low) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cmos_high) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -25394,54 +25372,11 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cmos_high) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cmos_low) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 661.7008 cm -Q -q -1 0 0 1 40.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (CmosAccessError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 631.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 625.7008 cm -Q -q -1 0 0 1 40.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (CmosRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 595.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 546.1008 cm +1 0 0 1 40.01575 642.1008 cm q 1 1 1 RG .3 w @@ -25453,22 +25388,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpu module) Tj T* ET Q Q q -1 0 0 1 40.01575 528.1008 cm +1 0 0 1 40.01575 624.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (CPU related functionality) Tj T* ET Q Q q -1 0 0 1 40.01575 522.1008 cm +1 0 0 1 40.01575 618.1008 cm Q q -1 0 0 1 40.01575 504.1008 cm +1 0 0 1 40.01575 600.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CPU) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 492.1008 cm +1 0 0 1 50.01575 588.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -25476,12 +25411,48 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q +1 0 0 1 50.01575 582.1008 cm +Q +q +1 0 0 1 50.01575 564.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRR_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 558.1008 cm +Q +q +1 0 0 1 50.01575 540.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_vmm) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 534.1008 cm +Q +q +1 0 0 1 50.01575 516.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 510.1008 cm +Q +q +1 0 0 1 50.01575 492.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cr3) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_fname) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 486.1008 cm Q q 1 0 0 1 50.01575 468.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRR_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_page_tables_all) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25490,7 +25461,7 @@ Q q 1 0 0 1 50.01575 444.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_vmm) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRAM) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25499,7 +25470,7 @@ Q q 1 0 0 1 50.01575 420.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRR) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25508,7 +25479,7 @@ Q q 1 0 0 1 50.01575 396.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cr3) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_fname) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRR_SMRAM) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25517,7 +25488,7 @@ Q q 1 0 0 1 50.01575 372.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_page_tables_all) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_TSEG) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25526,7 +25497,7 @@ Q q 1 0 0 1 50.01575 348.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRAM) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_topology) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25535,7 +25506,7 @@ Q q 1 0 0 1 50.01575 324.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRR) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_logical_processor_per_core) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25544,7 +25515,7 @@ Q q 1 0 0 1 50.01575 300.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMRR_SMRAM) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_logical_processor_per_package) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25553,7 +25524,7 @@ Q q 1 0 0 1 50.01575 276.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_TSEG) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_physical_processor_per_package) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25562,7 +25533,7 @@ Q q 1 0 0 1 50.01575 252.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_topology) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_sockets_from_APIC_table) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25571,7 +25542,7 @@ Q q 1 0 0 1 50.01575 228.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_logical_processor_per_core) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_threads_from_APIC_table) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25580,7 +25551,7 @@ Q q 1 0 0 1 50.01575 204.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_logical_processor_per_package) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_HT_active) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -25589,7 +25560,7 @@ Q q 1 0 0 1 50.01575 180.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_physical_processor_per_package) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -25598,40 +25569,35 @@ Q q 1 0 0 1 50.01575 156.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_sockets_from_APIC_table) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 150.1008 cm +1 0 0 1 40.01575 106.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* Q q -1 0 0 1 50.01575 132.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_number_threads_from_APIC_table) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpuid module) Tj T* ET Q Q q -1 0 0 1 50.01575 126.1008 cm -Q +1 0 0 1 40.01575 88.50079 cm q -1 0 0 1 50.01575 108.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_HT_active) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (CPUID information) Tj T* ET Q Q q -1 0 0 1 50.01575 102.1008 cm -Q +1 0 0 1 40.01575 72.50079 cm q -1 0 0 1 50.01575 84.10079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 50.01575 78.10079 cm -Q -q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -25647,62 +25613,14 @@ Q endstream endobj -1252 0 obj +1249 0 obj << -/Length 6508 +/Length 6383 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (CPURuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 727.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 678.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpuid module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 660.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (CPUID information) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 644.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 624.7008 cm +1 0 0 1 40.01575 756.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -25718,7 +25636,7 @@ q .666667 .8 .6 RG .3 w .933333 1 .8 rg -n -4 0 494.4441 15.6 re B* +n -4 0 488.4441 15.6 re B* Q q BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( cpuid\(0\)) Tj T* ET @@ -25732,16 +25650,16 @@ Q Q Q q -1 0 0 1 40.01575 618.7008 cm +1 0 0 1 40.01575 750.3008 cm Q q -1 0 0 1 40.01575 600.7008 cm +1 0 0 1 40.01575 732.3008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CpuID) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 588.7008 cm +1 0 0 1 50.01575 720.3008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -25749,33 +25667,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 582.7008 cm +1 0 0 1 50.01575 714.3008 cm Q q -1 0 0 1 50.01575 564.7008 cm +1 0 0 1 50.01575 696.3008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 558.7008 cm -Q -q -1 0 0 1 40.01575 540.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (CpuIDRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 528.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 479.1008 cm +1 0 0 1 40.01575 646.7008 cm q 1 1 1 RG .3 w @@ -25787,20 +25688,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ec module) Tj T* ET Q Q q -1 0 0 1 40.01575 461.1008 cm +1 0 0 1 40.01575 628.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to Embedded Controller \(EC\)) Tj T* ET Q Q q -1 0 0 1 40.01575 443.1008 cm +1 0 0 1 40.01575 610.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 349.9008 cm +1 0 0 1 40.01575 517.5008 cm q q 1 0 0 1 0 0 cm @@ -25820,16 +25721,16 @@ Q Q Q q -1 0 0 1 40.01575 335.9008 cm +1 0 0 1 40.01575 503.5008 cm Q q -1 0 0 1 40.01575 317.9008 cm +1 0 0 1 40.01575 485.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EC) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 305.9008 cm +1 0 0 1 50.01575 473.5008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -25837,88 +25738,138 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 299.9008 cm +1 0 0 1 50.01575 467.5008 cm Q q -1 0 0 1 50.01575 281.9008 cm +1 0 0 1 50.01575 449.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_data) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 275.9008 cm +1 0 0 1 50.01575 443.5008 cm Q q -1 0 0 1 50.01575 257.9008 cm +1 0 0 1 50.01575 425.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_idx) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 251.9008 cm +1 0 0 1 50.01575 419.5008 cm Q q -1 0 0 1 50.01575 233.9008 cm +1 0 0 1 50.01575 401.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 227.9008 cm +1 0 0 1 50.01575 395.5008 cm Q q -1 0 0 1 50.01575 209.9008 cm +1 0 0 1 50.01575 377.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_memory_extended) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (word_offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 203.9008 cm +1 0 0 1 50.01575 371.5008 cm Q q -1 0 0 1 50.01575 185.9008 cm +1 0 0 1 50.01575 353.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 179.9008 cm +1 0 0 1 50.01575 347.5008 cm Q q -1 0 0 1 50.01575 161.9008 cm +1 0 0 1 50.01575 329.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_command) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (command) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 155.9008 cm +1 0 0 1 50.01575 323.5008 cm Q q -1 0 0 1 50.01575 137.9008 cm +1 0 0 1 50.01575 305.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 131.9008 cm +1 0 0 1 50.01575 299.5008 cm Q q -1 0 0 1 50.01575 113.9008 cm +1 0 0 1 50.01575 281.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_idx) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 107.9008 cm +1 0 0 1 50.01575 275.5008 cm Q q -1 0 0 1 50.01575 89.90079 cm +1 0 0 1 50.01575 257.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 83.90079 cm +1 0 0 1 50.01575 251.5008 cm +Q +q +1 0 0 1 50.01575 233.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_memory_extended) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (word_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 227.5008 cm +Q +q +1 0 0 1 50.01575 209.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 159.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hal_base module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 141.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Base for HAL Components) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 135.9008 cm +Q +q +1 0 0 1 40.01575 117.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HALBase) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 105.9008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -25936,64 +25887,14 @@ Q endstream endobj -1253 0 obj +1250 0 obj << -/Length 6732 +/Length 7193 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_memory_extended) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (word_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 690.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hal_base module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 672.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Base for HAL Components) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 666.1008 cm -Q -q -1 0 0 1 40.01575 648.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HALBase) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 636.1008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 586.5008 cm +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -26005,20 +25906,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (igd module) Tj T* ET Q Q q -1 0 0 1 40.01575 568.5008 cm +1 0 0 1 40.01575 748.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Working with Intel processor Integrated Graphics Device \(IGD\)) Tj T* ET Q Q q -1 0 0 1 40.01575 552.5008 cm +1 0 0 1 40.01575 732.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 533.1008 cm +1 0 0 1 40.01575 712.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -26048,16 +25949,16 @@ Q Q Q q -1 0 0 1 40.01575 527.1008 cm +1 0 0 1 40.01575 706.7008 cm Q q -1 0 0 1 40.01575 509.1008 cm +1 0 0 1 40.01575 688.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (IGD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 497.1008 cm +1 0 0 1 50.01575 676.7008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -26065,208 +25966,169 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 491.1008 cm +1 0 0 1 50.01575 670.7008 cm Q q -1 0 0 1 50.01575 473.1008 cm +1 0 0 1 50.01575 652.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_GGTT_PTEs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 467.1008 cm +1 0 0 1 50.01575 646.7008 cm Q q -1 0 0 1 50.01575 449.1008 cm +1 0 0 1 50.01575 628.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GGTT_PTE_from_PA) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 443.1008 cm +1 0 0 1 50.01575 622.7008 cm Q q -1 0 0 1 50.01575 425.1008 cm +1 0 0 1 50.01575 604.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GGTT_PTE_from_PA_gen8) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 419.1008 cm +1 0 0 1 50.01575 598.7008 cm Q q -1 0 0 1 50.01575 401.1008 cm +1 0 0 1 50.01575 580.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GGTT_PTE_from_PA_legacy) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 395.1008 cm +1 0 0 1 50.01575 574.7008 cm Q q -1 0 0 1 50.01575 377.1008 cm +1 0 0 1 50.01575 556.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GGTT_base) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 371.1008 cm +1 0 0 1 50.01575 550.7008 cm Q q -1 0 0 1 50.01575 353.1008 cm +1 0 0 1 50.01575 532.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GMADR) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 347.1008 cm +1 0 0 1 50.01575 526.7008 cm Q q -1 0 0 1 50.01575 329.1008 cm +1 0 0 1 50.01575 508.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GTTMMADR) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 323.1008 cm +1 0 0 1 50.01575 502.7008 cm Q q -1 0 0 1 50.01575 305.1008 cm +1 0 0 1 50.01575 484.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_PA_from_PTE) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 299.1008 cm +1 0 0 1 50.01575 478.7008 cm Q q -1 0 0 1 50.01575 281.1008 cm +1 0 0 1 50.01575 460.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_PA_from_PTE_gen8) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 275.1008 cm +1 0 0 1 50.01575 454.7008 cm Q q -1 0 0 1 50.01575 257.1008 cm +1 0 0 1 50.01575 436.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_PA_from_PTE_legacy) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 251.1008 cm +1 0 0 1 50.01575 430.7008 cm Q q -1 0 0 1 50.01575 233.1008 cm +1 0 0 1 50.01575 412.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_PTE_size) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 227.1008 cm +1 0 0 1 50.01575 406.7008 cm Q q -1 0 0 1 50.01575 209.1008 cm +1 0 0 1 50.01575 388.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (gfx_aperture_dma_read_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_num) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 203.1008 cm +1 0 0 1 50.01575 382.7008 cm Q q -1 0 0 1 50.01575 185.1008 cm +1 0 0 1 50.01575 364.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_device_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 179.1008 cm +1 0 0 1 50.01575 358.7008 cm Q q -1 0 0 1 50.01575 161.1008 cm +1 0 0 1 50.01575 340.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 155.1008 cm +1 0 0 1 50.01575 334.7008 cm Q q -1 0 0 1 50.01575 137.1008 cm +1 0 0 1 50.01575 316.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_legacy_gen) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 131.1008 cm +1 0 0 1 50.01575 310.7008 cm Q q -1 0 0 1 50.01575 113.1008 cm +1 0 0 1 50.01575 292.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_GGTT_PTE) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_num) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 107.1008 cm +1 0 0 1 50.01575 286.7008 cm Q q -1 0 0 1 50.01575 89.10079 cm +1 0 0 1 50.01575 268.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_GGTT_PTE) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_num) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pte) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 83.10079 cm +1 0 0 1 50.01575 262.7008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (49) Tj T* ET -Q -Q - -endstream -endobj -1254 0 obj -<< -/Length 8647 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 50.01575 244.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_GGTT_PTE_from_PA) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_num) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (IGDRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 727.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 678.1008 cm +1 0 0 1 40.01575 195.1008 cm q 1 1 1 RG .3 w @@ -26278,20 +26140,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (interrupts module) Tj T* ET Q Q q -1 0 0 1 40.01575 660.1008 cm +1 0 0 1 40.01575 177.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Functionality encapsulating interrupt generation CPU Interrupts specific functions \(SMI, NMI\)) Tj T* ET Q Q q -1 0 0 1 40.01575 644.1008 cm +1 0 0 1 40.01575 161.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 615.1008 cm +1 0 0 1 40.01575 132.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -26321,16 +26183,16 @@ Q Q Q q -1 0 0 1 40.01575 609.1008 cm +1 0 0 1 40.01575 126.1008 cm Q q -1 0 0 1 40.01575 591.1008 cm +1 0 0 1 40.01575 108.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Interrupts) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 579.1008 cm +1 0 0 1 50.01575 96.10079 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -26338,70 +26200,92 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 573.1008 cm +1 0 0 1 50.01575 90.10079 cm Q q -1 0 0 1 50.01575 555.1008 cm +1 0 0 1 50.01575 72.10079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_ACPI_SMI_Buffer) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 549.1008 cm +1 0 0 1 50.01575 66.18898 cm Q q -1 0 0 1 50.01575 531.1008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (49) Tj T* ET +Q +Q + +endstream +endobj +1251 0 obj +<< +/Length 8942 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_smmc) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (end) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 525.1008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 507.1008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_ACPI_SMI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smi_num) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (invoc_reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 501.1008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 483.1008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_NMI) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 477.1008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 459.1008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_SMI_APMC) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_port_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_data_port_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 453.1008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 435.1008 cm +1 0 0 1 50.01575 667.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_SW_SMI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_port_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_data_port_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 429.1008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 411.1008 cm +1 0 0 1 50.01575 643.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_smmc_SMI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (smmc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (payload) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (payload_loc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CommandPort) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (DataPort) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 361.5008 cm +1 0 0 1 40.01575 594.1008 cm q 1 1 1 RG .3 w @@ -26413,20 +26297,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (io module) Tj T* ET Q Q q -1 0 0 1 40.01575 343.5008 cm +1 0 0 1 40.01575 576.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to Port I/O) Tj T* ET Q Q q -1 0 0 1 40.01575 327.5008 cm +1 0 0 1 40.01575 560.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 260.1008 cm +1 0 0 1 40.01575 492.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -26456,16 +26340,16 @@ Q Q Q q -1 0 0 1 40.01575 254.1008 cm +1 0 0 1 40.01575 486.7008 cm Q q -1 0 0 1 40.01575 236.1008 cm +1 0 0 1 40.01575 468.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PortIO) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 224.1008 cm +1 0 0 1 50.01575 456.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -26473,118 +26357,79 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 218.1008 cm +1 0 0 1 50.01575 450.7008 cm Q q -1 0 0 1 50.01575 200.1008 cm +1 0 0 1 50.01575 432.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_IO) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (range_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (range_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 194.1008 cm +1 0 0 1 50.01575 426.7008 cm Q q -1 0 0 1 50.01575 176.1008 cm +1 0 0 1 50.01575 408.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_IO) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (range_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (range_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 170.1008 cm +1 0 0 1 50.01575 402.7008 cm Q q -1 0 0 1 50.01575 152.1008 cm +1 0 0 1 50.01575 384.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_port_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 146.1008 cm +1 0 0 1 50.01575 378.7008 cm Q q -1 0 0 1 50.01575 128.1008 cm +1 0 0 1 50.01575 360.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_port_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 122.1008 cm +1 0 0 1 50.01575 354.7008 cm Q q -1 0 0 1 50.01575 104.1008 cm +1 0 0 1 50.01575 336.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_port_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 98.10079 cm +1 0 0 1 50.01575 330.7008 cm Q q -1 0 0 1 50.01575 80.10079 cm +1 0 0 1 50.01575 312.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_port_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 74.10079 cm +1 0 0 1 50.01575 306.7008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (50) Tj T* ET -Q -Q - -endstream -endobj -1255 0 obj -<< -/Length 7412 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 50.01575 288.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_port_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 50.01575 282.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 50.01575 264.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_port_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 733.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (PortIORuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 654.1008 cm +1 0 0 1 40.01575 215.1008 cm q 1 1 1 RG .3 w @@ -26596,20 +26441,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (iobar module) Tj T* ET Q Q q -1 0 0 1 40.01575 636.1008 cm +1 0 0 1 40.01575 197.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (I/O BAR access \(dump, read/write\)) Tj T* ET Q Q q -1 0 0 1 40.01575 620.1008 cm +1 0 0 1 40.01575 181.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 571.9008 cm +1 0 0 1 40.01575 132.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -26639,16 +26484,16 @@ Q Q Q q -1 0 0 1 40.01575 565.9008 cm +1 0 0 1 40.01575 126.9008 cm Q q -1 0 0 1 40.01575 547.9008 cm +1 0 0 1 40.01575 108.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (IOBAR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 535.9008 cm +1 0 0 1 50.01575 96.90079 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -26656,113 +26501,101 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 529.9008 cm +1 0 0 1 50.01575 90.90079 cm Q q -1 0 0 1 50.01575 511.9008 cm +1 0 0 1 50.01575 72.90079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_IO_BAR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 505.9008 cm +1 0 0 1 50.01575 66.90079 cm Q q -1 0 0 1 50.01575 487.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (50) Tj T* ET +Q +Q + +endstream +endobj +1252 0 obj +<< +/Length 6760 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_IO_BAR_base_address) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 481.9008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 463.9008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IO_BAR_defined) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 457.9008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 439.9008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IO_BAR_enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 433.9008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 415.9008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_IO_BARs) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 409.9008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 391.9008 cm +1 0 0 1 50.01575 667.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_IO_BAR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 385.9008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 367.9008 cm +1 0 0 1 50.01575 643.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_IO_BAR_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 361.9008 cm +1 0 0 1 50.01575 637.7008 cm Q q -1 0 0 1 50.01575 343.9008 cm +1 0 0 1 50.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_IO_BAR_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 337.9008 cm -Q -q -1 0 0 1 40.01575 319.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (IOBARNotFoundError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 307.9008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 301.9008 cm -Q -q -1 0 0 1 40.01575 283.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (IOBARRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 271.9008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 222.3008 cm +1 0 0 1 40.01575 570.1008 cm q 1 1 1 RG .3 w @@ -26774,22 +26607,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (iommu module) Tj T* ET Q Q q -1 0 0 1 40.01575 204.3008 cm +1 0 0 1 40.01575 552.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to IOMMU engines) Tj T* ET Q Q q -1 0 0 1 40.01575 198.3008 cm +1 0 0 1 40.01575 546.1008 cm Q q -1 0 0 1 40.01575 180.3008 cm +1 0 0 1 40.01575 528.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (IOMMU) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 168.3008 cm +1 0 0 1 50.01575 516.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -26797,43 +26630,156 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 162.3008 cm +1 0 0 1 50.01575 510.1008 cm Q q -1 0 0 1 50.01575 144.3008 cm +1 0 0 1 50.01575 492.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_IOMMU_configuration) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 138.3008 cm +1 0 0 1 50.01575 486.1008 cm Q q -1 0 0 1 50.01575 120.3008 cm +1 0 0 1 50.01575 468.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_IOMMU_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 114.3008 cm +1 0 0 1 50.01575 462.1008 cm Q q -1 0 0 1 50.01575 96.30079 cm +1 0 0 1 50.01575 444.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_IOMMU_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 90.30079 cm +1 0 0 1 50.01575 438.1008 cm Q q -1 0 0 1 50.01575 72.30079 cm +1 0 0 1 50.01575 420.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_IOMMU_Base_Address) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 66.30079 cm +1 0 0 1 50.01575 414.1008 cm +Q +q +1 0 0 1 50.01575 396.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IOMMU_Engine_Enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 390.1008 cm +Q +q +1 0 0 1 50.01575 372.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IOMMU_Translation_Enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 366.1008 cm +Q +q +1 0 0 1 50.01575 348.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_IOMMU_Translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (te) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 298.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (mmio module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 280.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to MMIO \(Memory Mapped IO\) BARs and Memory-Mapped PCI Configuration Space \(MMCFG\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 264.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 90.30079 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 161.2 Tm T* ET +q +1 0 0 1 20 126 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 488.4441 44.4 re B* +Q +q +BT 1 0 0 1 0 30.4 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_MMIO_reg\(cs, bar_base, 0x0, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_MMIO_reg\(cs, bar_base, 0x0, 0xFFFFFFFF, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( read_MMIO\( cs, bar_base, 0x1000 \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_MMIO\( cs, bar_base, 0x1000 \)) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 20 100 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Access MMIO by BAR name:) Tj T* ET +Q +Q +q +1 0 0 1 20 26 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 488.4441 73.2 re B* +Q +q +BT 1 0 0 1 0 59.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_MMIO_BAR_reg\( cs, 'MCHBAR', 0x0, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_MMIO_BAR_reg\( cs, 'MCHBAR', 0x0, 0xFFFFFFFF, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( get_MMIO_BAR_base_address\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( is_MMIO_BAR_enabled\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( is_MMIO_BAR_programmed\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_MMIO_BAR\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( list_MMIO_BARs\( cs \)) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Access Memory Mapped Config Space:) Tj T* ET +Q +Q +q +Q +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -26851,138 +26797,18 @@ Q endstream endobj -1256 0 obj +1253 0 obj << -/Length 7528 +/Length 10228 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IOMMU_Engine_Enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_IOMMU_Translation_Enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_IOMMU_Translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iommu_engine) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (te) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 709.7008 cm -Q -q -1 0 0 1 40.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (IOMMUError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 679.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 630.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (mmio module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 612.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to MMIO \(Memory Mapped IO\) BARs and Memory-Mapped PCI Configuration Space \(MMCFG\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 596.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 386.3008 cm +1 0 0 1 40.01575 737.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 196.8 Tm T* ET -q -1 0 0 1 20 161.6 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 494.4441 44.4 re B* -Q -q -BT 1 0 0 1 0 30.4 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_MMIO_reg\(cs, bar_base, 0x0, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_MMIO_reg\(cs, bar_base, 0x0, 0xFFFFFFFF, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( read_MMIO\( cs, bar_base, 0x1000 \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_MMIO\( cs, bar_base, 0x1000 \)) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 20 135.6 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Access MMIO by BAR name:) Tj T* ET -Q -Q -q -1 0 0 1 20 61.6 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 494.4441 73.2 re B* -Q -q -BT 1 0 0 1 0 59.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_MMIO_BAR_reg\( cs, 'MCHBAR', 0x0, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_MMIO_BAR_reg\( cs, 'MCHBAR', 0x0, 0xFFFFFFFF, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( get_MMIO_BAR_base_address\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( is_MMIO_BAR_enabled\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( is_MMIO_BAR_programmed\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_MMIO_BAR\( cs, 'MCHBAR' \)) Tj T* (>) Tj (>) Tj (>) Tj ( list_MMIO_BARs\( cs \)) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 20 35.6 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Access Memory Mapped Config Space:) Tj T* ET -Q -Q +BT 1 0 0 1 0 25.6 Tm T* ET q 1 0 0 1 20 0 cm q @@ -26994,7 +26820,7 @@ q .666667 .8 .6 RG .3 w .933333 1 .8 rg -n -4 0 494.4441 34.8 re B* +n -4 0 488.4441 34.8 re B* Q q BT 1 0 0 1 0 20.8 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( get_MMCFG_base_address\(cs\)) Tj T* (>) Tj (>) Tj (>) Tj ( read_mmcfg_reg\( cs, 0, 0, 0, 0x10, 4 \)) Tj T* (>) Tj (>) Tj (>) Tj ( read_mmcfg_reg\( cs, 0, 0, 0, 0x10, 4, 0xFFFFFFFF \)) Tj T* ET @@ -27008,16 +26834,16 @@ Q Q Q q -1 0 0 1 40.01575 380.3008 cm +1 0 0 1 40.01575 731.1008 cm Q q -1 0 0 1 40.01575 362.3008 cm +1 0 0 1 40.01575 713.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MMIO) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 350.3008 cm +1 0 0 1 50.01575 701.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -27025,106 +26851,233 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 344.3008 cm +1 0 0 1 50.01575 695.1008 cm Q q -1 0 0 1 50.01575 326.3008 cm +1 0 0 1 50.01575 677.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_MMIO) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 320.3008 cm +1 0 0 1 50.01575 671.1008 cm Q q -1 0 0 1 50.01575 302.3008 cm +1 0 0 1 50.01575 653.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_MMIO_BAR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 296.3008 cm +1 0 0 1 50.01575 647.1008 cm Q q -1 0 0 1 50.01575 278.3008 cm +1 0 0 1 50.01575 629.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_MMCFG_base_address) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 272.3008 cm +1 0 0 1 50.01575 623.1008 cm Q q -1 0 0 1 50.01575 254.3008 cm +1 0 0 1 50.01575 605.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_MMIO_BAR_base_address) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 248.3008 cm +1 0 0 1 50.01575 599.1008 cm Q q -1 0 0 1 50.01575 230.3008 cm +1 0 0 1 50.01575 581.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_MMIO_BAR_defined) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 224.3008 cm +1 0 0 1 50.01575 575.1008 cm Q q -1 0 0 1 50.01575 206.3008 cm +1 0 0 1 50.01575 557.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_MMIO_BAR_enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 200.3008 cm +1 0 0 1 50.01575 551.1008 cm Q q -1 0 0 1 50.01575 182.3008 cm +1 0 0 1 50.01575 533.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_MMIO_BAR_programmed) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 176.3008 cm +1 0 0 1 50.01575 527.1008 cm Q q -1 0 0 1 50.01575 158.3008 cm +1 0 0 1 50.01575 509.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_MMIO_BARs) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 152.3008 cm +1 0 0 1 50.01575 503.1008 cm Q q -1 0 0 1 50.01575 134.3008 cm +1 0 0 1 50.01575 485.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 128.3008 cm +1 0 0 1 50.01575 479.1008 cm Q q -1 0 0 1 50.01575 110.3008 cm +1 0 0 1 50.01575 461.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_BAR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 104.3008 cm +1 0 0 1 50.01575 455.1008 cm Q q -1 0 0 1 50.01575 86.30079 cm +1 0 0 1 50.01575 437.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_BAR_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 80.30079 cm +1 0 0 1 50.01575 431.1008 cm +Q +q +1 0 0 1 50.01575 413.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 407.1008 cm +Q +q +1 0 0 1 50.01575 389.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 383.1008 cm +Q +q +1 0 0 1 50.01575 365.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 359.1008 cm +Q +q +1 0 0 1 50.01575 341.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 335.1008 cm +Q +q +1 0 0 1 50.01575 317.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmcfg_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 311.1008 cm +Q +q +1 0 0 1 50.01575 293.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_BAR_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 287.1008 cm +Q +q +1 0 0 1 50.01575 269.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 263.1008 cm +Q +q +1 0 0 1 50.01575 245.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 239.1008 cm +Q +q +1 0 0 1 50.01575 221.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 215.1008 cm +Q +q +1 0 0 1 50.01575 197.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 191.1008 cm +Q +q +1 0 0 1 50.01575 173.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmcfg_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 123.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (msgbus module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 105.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to message bus \(IOSF sideband\) interface registers on Intel SoCs) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 87.50079 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 81.50079 cm +Q +q +1 0 0 1 40.01575 81.50079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -27142,141 +27095,14 @@ Q endstream endobj -1257 0 obj +1254 0 obj << -/Length 9032 +/Length 5741 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_MMIO_reg_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmcfg_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_BAR_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_MMIO_reg_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmcfg_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 474.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (msgbus module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 456.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to message bus \(IOSF sideband\) interface registers on Intel SoCs) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 438.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 432.1008 cm -Q -q -1 0 0 1 40.01575 432.1008 cm -Q -q -1 0 0 1 40.01575 408.1008 cm +1 0 0 1 40.01575 751.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -27298,17 +27124,17 @@ Q Q Q q -1 0 0 1 40.01575 408.1008 cm +1 0 0 1 40.01575 751.7008 cm Q q -1 0 0 1 40.01575 392.1008 cm +1 0 0 1 40.01575 735.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 334.3008 cm +1 0 0 1 40.01575 677.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -27338,16 +27164,16 @@ Q Q Q q -1 0 0 1 40.01575 328.3008 cm +1 0 0 1 40.01575 671.9008 cm Q q -1 0 0 1 40.01575 310.3008 cm +1 0 0 1 40.01575 653.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MessageBusOpcode) Tj T* ET Q Q q -1 0 0 1 50.01575 298.3008 cm +1 0 0 1 50.01575 641.9008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -27355,88 +27181,222 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 292.3008 cm +1 0 0 1 50.01575 635.9008 cm Q q -1 0 0 1 50.01575 274.3008 cm +1 0 0 1 50.01575 617.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_CFG_READ) Tj /F4 10 Tf ( = 4) Tj T* ET Q Q q -1 0 0 1 50.01575 268.3008 cm +1 0 0 1 50.01575 611.9008 cm Q q -1 0 0 1 50.01575 250.3008 cm +1 0 0 1 50.01575 593.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_CFG_WRITE) Tj /F4 10 Tf ( = 5) Tj T* ET Q Q q -1 0 0 1 50.01575 244.3008 cm +1 0 0 1 50.01575 587.9008 cm Q q -1 0 0 1 50.01575 226.3008 cm +1 0 0 1 50.01575 569.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_CR_READ) Tj /F4 10 Tf ( = 6) Tj T* ET Q Q q -1 0 0 1 50.01575 220.3008 cm +1 0 0 1 50.01575 563.9008 cm Q q -1 0 0 1 50.01575 202.3008 cm +1 0 0 1 50.01575 545.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_CR_WRITE) Tj /F4 10 Tf ( = 7) Tj T* ET Q Q q -1 0 0 1 50.01575 196.3008 cm +1 0 0 1 50.01575 539.9008 cm Q q -1 0 0 1 50.01575 178.3008 cm +1 0 0 1 50.01575 521.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_ESRAM_READ) Tj /F4 10 Tf ( = 18) Tj T* ET Q Q q -1 0 0 1 50.01575 172.3008 cm +1 0 0 1 50.01575 515.9008 cm Q q -1 0 0 1 50.01575 154.3008 cm +1 0 0 1 50.01575 497.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_ESRAM_WRITE) Tj /F4 10 Tf ( = 19) Tj T* ET Q Q q -1 0 0 1 50.01575 148.3008 cm +1 0 0 1 50.01575 491.9008 cm Q q -1 0 0 1 50.01575 130.3008 cm +1 0 0 1 50.01575 473.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_IO_READ) Tj /F4 10 Tf ( = 2) Tj T* ET Q Q q -1 0 0 1 50.01575 124.3008 cm +1 0 0 1 50.01575 467.9008 cm Q q -1 0 0 1 50.01575 106.3008 cm +1 0 0 1 50.01575 449.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_IO_WRITE) Tj /F4 10 Tf ( = 3) Tj T* ET Q Q q -1 0 0 1 50.01575 100.3008 cm +1 0 0 1 50.01575 443.9008 cm Q q -1 0 0 1 50.01575 82.30079 cm +1 0 0 1 50.01575 425.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_MMIO_READ) Tj /F4 10 Tf ( = 0) Tj T* ET Q Q q -1 0 0 1 50.01575 76.30079 cm +1 0 0 1 50.01575 419.9008 cm +Q +q +1 0 0 1 50.01575 401.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_MMIO_WRITE) Tj /F4 10 Tf ( = 1) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 395.9008 cm +Q +q +1 0 0 1 50.01575 377.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_REG_READ) Tj /F4 10 Tf ( = 16) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 371.9008 cm +Q +q +1 0 0 1 50.01575 353.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_REG_WRITE) Tj /F4 10 Tf ( = 17) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 347.9008 cm +Q +q +1 0 0 1 40.01575 329.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MessageBusPort_Atom) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 317.9008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 311.9008 cm +Q +q +1 0 0 1 50.01575 293.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_AUNIT) Tj /F4 10 Tf ( = 0) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 287.9008 cm +Q +q +1 0 0 1 50.01575 269.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_BUNIT) Tj /F4 10 Tf ( = 3) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 263.9008 cm +Q +q +1 0 0 1 50.01575 245.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_CPU) Tj /F4 10 Tf ( = 2) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 239.9008 cm +Q +q +1 0 0 1 50.01575 221.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_GFX) Tj /F4 10 Tf ( = 6) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 215.9008 cm +Q +q +1 0 0 1 50.01575 197.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_PCIE) Tj /F4 10 Tf ( = 166) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 191.9008 cm +Q +q +1 0 0 1 50.01575 173.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_PMC) Tj /F4 10 Tf ( = 4) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 167.9008 cm +Q +q +1 0 0 1 50.01575 149.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SATA) Tj /F4 10 Tf ( = 163) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 143.9008 cm +Q +q +1 0 0 1 50.01575 125.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SMC) Tj /F4 10 Tf ( = 1) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 119.9008 cm +Q +q +1 0 0 1 50.01575 101.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SMI) Tj /F4 10 Tf ( = 12) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 95.90079 cm +Q +q +1 0 0 1 50.01575 77.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_USB) Tj /F4 10 Tf ( = 67) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 71.90079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -27454,47 +27414,20 @@ Q endstream endobj -1258 0 obj +1255 0 obj << -/Length 6899 +/Length 8256 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_MMIO_WRITE) Tj /F4 10 Tf ( = 1) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MessageBusPort_Quark) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_REG_READ) Tj /F4 10 Tf ( = 16) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MB_OPCODE_REG_WRITE) Tj /F4 10 Tf ( = 17) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 709.7008 cm -Q -q -1 0 0 1 40.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MessageBusPort_Atom) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 679.7008 cm +1 0 0 1 50.01575 751.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -27502,12 +27435,39 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q +1 0 0 1 50.01575 745.7008 cm +Q +q +1 0 0 1 50.01575 727.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_HB) Tj /F4 10 Tf ( = 3) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 721.7008 cm +Q +q +1 0 0 1 50.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_HBA) Tj /F4 10 Tf ( = 0) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 697.7008 cm +Q +q +1 0 0 1 50.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_MM) Tj /F4 10 Tf ( = 5) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 673.7008 cm Q q 1 0 0 1 50.01575 655.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_AUNIT) Tj /F4 10 Tf ( = 0) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_RMU) Tj /F4 10 Tf ( = 4) Tj T* ET Q Q q @@ -27516,154 +27476,20 @@ Q q 1 0 0 1 50.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_BUNIT) Tj /F4 10 Tf ( = 3) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_CPU) Tj /F4 10 Tf ( = 2) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_GFX) Tj /F4 10 Tf ( = 6) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_PCIE) Tj /F4 10 Tf ( = 166) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 553.7008 cm -Q -q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_PMC) Tj /F4 10 Tf ( = 4) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SATA) Tj /F4 10 Tf ( = 163) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SMC) Tj /F4 10 Tf ( = 1) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SMI) Tj /F4 10 Tf ( = 12) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_USB) Tj /F4 10 Tf ( = 67) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 433.7008 cm -Q -q -1 0 0 1 40.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MessageBusPort_Quark) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 403.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_HB) Tj /F4 10 Tf ( = 3) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 373.7008 cm -Q -q -1 0 0 1 50.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_HBA) Tj /F4 10 Tf ( = 0) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 349.7008 cm -Q -q -1 0 0 1 50.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_MM) Tj /F4 10 Tf ( = 5) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_RMU) Tj /F4 10 Tf ( = 4) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 301.7008 cm -Q -q -1 0 0 1 50.01575 283.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UNIT_SOC) Tj /F4 10 Tf ( = 49) Tj T* ET Q Q q -1 0 0 1 40.01575 277.7008 cm +1 0 0 1 40.01575 625.7008 cm Q q -1 0 0 1 40.01575 259.7008 cm +1 0 0 1 40.01575 607.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MsgBus) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 247.7008 cm +1 0 0 1 50.01575 595.7008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -27671,109 +27497,70 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 241.7008 cm +1 0 0 1 50.01575 589.7008 cm Q q -1 0 0 1 50.01575 223.7008 cm +1 0 0 1 50.01575 571.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mm_msgbus_reg_read) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 217.7008 cm +1 0 0 1 50.01575 565.7008 cm Q q -1 0 0 1 50.01575 199.7008 cm +1 0 0 1 50.01575 547.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mm_msgbus_reg_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 193.7008 cm +1 0 0 1 50.01575 541.7008 cm Q q -1 0 0 1 50.01575 175.7008 cm +1 0 0 1 50.01575 523.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (opcode) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 169.7008 cm +1 0 0 1 50.01575 517.7008 cm Q q -1 0 0 1 50.01575 151.7008 cm +1 0 0 1 50.01575 499.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_reg_read) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 145.7008 cm +1 0 0 1 50.01575 493.7008 cm Q q -1 0 0 1 50.01575 127.7008 cm +1 0 0 1 50.01575 475.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_reg_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 121.7008 cm +1 0 0 1 50.01575 469.7008 cm Q q -1 0 0 1 50.01575 103.7008 cm +1 0 0 1 50.01575 451.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (opcode) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 97.70079 cm +1 0 0 1 50.01575 445.7008 cm Q q -1 0 0 1 50.01575 79.70079 cm +1 0 0 1 50.01575 427.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (register) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (opcode) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (54) Tj T* ET -Q -Q - -endstream -endobj -1259 0 obj -<< -/Length 7167 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MsgBusRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 751.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 702.1008 cm +1 0 0 1 40.01575 378.1008 cm q 1 1 1 RG .3 w @@ -27785,20 +27572,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (msr module) Tj T* ET Q Q q -1 0 0 1 40.01575 684.1008 cm +1 0 0 1 40.01575 360.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to CPU resources \(for each CPU thread\): Model Specific Registers \(MSR\), IDT/GDT) Tj T* ET Q Q q -1 0 0 1 40.01575 668.1008 cm +1 0 0 1 40.01575 344.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 571.9008 cm +1 0 0 1 40.01575 247.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -27828,16 +27615,16 @@ Q Q Q q -1 0 0 1 40.01575 565.9008 cm +1 0 0 1 40.01575 241.9008 cm Q q -1 0 0 1 40.01575 547.9008 cm +1 0 0 1 40.01575 223.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Msr) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 535.9008 cm +1 0 0 1 50.01575 211.9008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -27845,141 +27632,146 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 529.9008 cm +1 0 0 1 50.01575 205.9008 cm Q q -1 0 0 1 50.01575 511.9008 cm +1 0 0 1 50.01575 187.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (GDT) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (num_entries) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 505.9008 cm +1 0 0 1 50.01575 181.9008 cm Q q -1 0 0 1 50.01575 487.9008 cm +1 0 0 1 50.01575 163.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (GDT_all) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_entries) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 481.9008 cm +1 0 0 1 50.01575 157.9008 cm Q q -1 0 0 1 50.01575 463.9008 cm +1 0 0 1 50.01575 139.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IDT) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (num_entries) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 457.9008 cm +1 0 0 1 50.01575 133.9008 cm Q q -1 0 0 1 50.01575 439.9008 cm +1 0 0 1 50.01575 115.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IDT_all) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_entries) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 433.9008 cm +1 0 0 1 50.01575 109.9008 cm Q q -1 0 0 1 50.01575 415.9008 cm +1 0 0 1 50.01575 91.90079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_Descriptor_Table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (num_entries) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 409.9008 cm +1 0 0 1 50.01575 85.90079 cm Q q -1 0 0 1 50.01575 391.9008 cm +1 0 0 1 50.01575 67.90079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_Desc_Table_Register) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 385.9008 cm +1 0 0 1 50.01575 66.18898 cm Q q -1 0 0 1 50.01575 367.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (54) Tj T* ET +Q +Q + +endstream +endobj +1256 0 obj +<< +/Length 8682 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_GDTR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 361.9008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 343.9008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_IDTR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 337.9008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 319.9008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_LDTR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 313.9008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 295.9008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_core_count) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 289.9008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 271.9008 cm +1 0 0 1 50.01575 667.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_thread_count) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 265.9008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 247.9008 cm +1 0 0 1 50.01575 643.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 241.9008 cm +1 0 0 1 50.01575 637.7008 cm Q q -1 0 0 1 50.01575 223.9008 cm +1 0 0 1 50.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 217.9008 cm -Q -q -1 0 0 1 40.01575 199.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MsrRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 187.9008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 138.3008 cm +1 0 0 1 40.01575 570.1008 cm q 1 1 1 RG .3 w @@ -27991,32 +27783,204 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (paging module) Tj T* ET Q Q q -1 0 0 1 40.01575 126.3008 cm +1 0 0 1 40.01575 558.1008 cm Q q -1 0 0 1 40.01575 108.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (InvalidMemoryAddress) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 96.30079 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 90.30079 cm -Q -q -1 0 0 1 40.01575 72.30079 cm +1 0 0 1 40.01575 540.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_4level_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 50.01575 528.1008 cm +q +.933333 1 .8 rg +n 33.35 0 162 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 522.1008 cm +Q +q +1 0 0 1 50.01575 504.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 498.1008 cm +Q +q +1 0 0 1 50.01575 480.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_virt_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pde_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 474.1008 cm +Q +q +1 0 0 1 50.01575 456.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 450.1008 cm +Q +q +1 0 0 1 50.01575 432.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_present) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 426.1008 cm +Q +q +1 0 0 1 50.01575 408.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_entry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (lvl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (perm) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 402.1008 cm +Q +q +1 0 0 1 50.01575 384.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_entry_by_virt_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 378.1008 cm +Q +q +1 0 0 1 50.01575 360.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 354.1008 cm +Q +q +1 0 0 1 50.01575 336.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pd) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 330.1008 cm +Q +q +1 0 0 1 50.01575 312.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pdpt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 306.1008 cm +Q +q +1 0 0 1 50.01575 288.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pml4) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 282.1008 cm +Q +q +1 0 0 1 50.01575 264.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pde_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 258.1008 cm +Q +q +1 0 0 1 40.01575 240.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_extended_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 228.1008 cm +q +.933333 1 .8 rg +n 33.35 0 234 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_4level_page_tables) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 222.1008 cm +Q +q +1 0 0 1 50.01575 204.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 198.1008 cm +Q +q +1 0 0 1 50.01575 180.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 174.1008 cm +Q +q +1 0 0 1 50.01575 156.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_present) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 150.1008 cm +Q +q +1 0 0 1 50.01575 132.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_bigpage_1G) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 126.1008 cm +Q +q +1 0 0 1 50.01575 108.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt_and_show_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 102.1008 cm +Q +q +1 0 0 1 40.01575 84.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_ia32e_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 72.10079 cm +q +.933333 1 .8 rg +n 33.35 0 234 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_4level_page_tables) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -28032,18 +27996,16 @@ Q endstream endobj -1260 0 obj +1257 0 obj << -/Length 8973 +/Length 8711 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -.933333 1 .8 rg -n 33.35 0 162 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28052,7 +28014,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28061,105 +28023,106 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_virt_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pde_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pte_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_present) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 40.01575 709.7008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_entry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (lvl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (perm) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_pae_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm -Q +1 0 0 1 50.01575 679.7008 cm q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_entry_by_virt_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 228 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_ia32e_page_tables) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm +1 0 0 1 50.01575 673.7008 cm Q q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 50.01575 655.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 50.01575 649.7008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 50.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pd) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pdpt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 50.01575 625.7008 cm Q q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pdpt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm +1 0 0 1 50.01575 607.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pml4) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 517.7008 cm +1 0 0 1 40.01575 601.7008 cm Q q -1 0 0 1 50.01575 499.7008 cm +1 0 0 1 40.01575 583.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pdpte_index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pde_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 493.7008 cm +1 0 0 1 50.01575 559.7008 cm +q +.933333 1 .8 rg +n 33.35 12 324 12 re f* +.933333 1 .8 rg +n 0 0 192 12 re f* +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging_with_2nd_level_translation) Tj /F1 10 Tf (,) Tj T* /F6 10 Tf (chipsec.hal.paging.c_translation) Tj T* ET +Q Q q -1 0 0 1 40.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_extended_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +1 0 0 1 50.01575 553.7008 cm Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_misconfig) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 529.7008 cm +Q +q +1 0 0 1 50.01575 511.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_canonical) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_field) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm Q q 1 0 0 1 50.01575 463.7008 cm q -.933333 1 .8 rg -n 33.35 0 234 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_4level_page_tables) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_configuration) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28168,7 +28131,7 @@ Q q 1 0 0 1 50.01575 439.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28177,7 +28140,7 @@ Q q 1 0 0 1 50.01575 415.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_entries) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (info) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (8) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28186,7 +28149,7 @@ Q q 1 0 0 1 50.01575 391.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_present) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28195,7 +28158,7 @@ Q q 1 0 0 1 50.01575 367.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_bigpage_1G) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt_and_show_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28204,33 +28167,33 @@ Q q 1 0 0 1 50.01575 343.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt_and_show_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (save_configuration) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 337.7008 cm +1 0 0 1 50.01575 337.7008 cm Q q -1 0 0 1 40.01575 319.7008 cm +1 0 0 1 50.01575 319.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_ia32e_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_field) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 307.7008 cm -q -.933333 1 .8 rg -n 33.35 0 234 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_4level_page_tables) Tj T* ET -Q +1 0 0 1 40.01575 313.7008 cm Q q -1 0 0 1 50.01575 301.7008 cm +1 0 0 1 40.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging_memory_access) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 50.01575 283.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q @@ -28239,79 +28202,85 @@ Q q 1 0 0 1 50.01575 259.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_bigpage) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 253.7008 cm +1 0 0 1 40.01575 253.7008 cm Q q -1 0 0 1 50.01575 235.7008 cm +1 0 0 1 40.01575 235.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_present) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging_with_2nd_level_translation) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 229.7008 cm +1 0 0 1 50.01575 223.7008 cm +q +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging_memory_access) Tj T* ET +Q Q q -1 0 0 1 40.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_pae_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q +1 0 0 1 50.01575 217.7008 cm Q q 1 0 0 1 50.01575 199.7008 cm q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 193.7008 cm +Q +q +1 0 0 1 40.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_reverse_translation) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (translation) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 163.7008 cm +q .933333 1 .8 rg -n 33.35 0 228 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_ia32e_page_tables) Tj T* ET +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 193.7008 cm +1 0 0 1 50.01575 157.7008 cm Q q -1 0 0 1 50.01575 175.7008 cm +1 0 0 1 50.01575 139.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_reverse_translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 169.7008 cm +1 0 0 1 40.01575 133.7008 cm Q q -1 0 0 1 50.01575 151.7008 cm +1 0 0 1 40.01575 115.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pdpt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pml4e_index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_translation) Tj T* ET Q Q q -1 0 0 1 50.01575 145.7008 cm -Q +1 0 0 1 50.01575 103.7008 cm q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pml4) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 40.01575 121.7008 cm -Q -q -1 0 0 1 40.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q +1 0 0 1 50.01575 97.70079 cm Q q 1 0 0 1 50.01575 79.70079 cm q -.933333 1 .8 rg -n 33.35 12 324 12 re f* -.933333 1 .8 rg -n 0 0 192 12 re f* -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging_with_2nd_level_translation) Tj /F1 10 Tf (,) Tj T* /F6 10 Tf (chipsec.hal.paging.c_translation) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_page) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28333,16 +28302,16 @@ Q endstream endobj -1261 0 obj +1258 0 obj << -/Length 8752 +/Length 8466 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_misconfig) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (del_page) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28351,7 +28320,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_canonical) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (expand_pages) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (exp_size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28360,7 +28329,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_field) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_address_space) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -28369,7 +28338,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_configuration) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_mem_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (noattr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28378,7 +28347,7 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_pages_by_physaddr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28387,7 +28356,7 @@ Q q 1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_entries) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (info) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (8) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28396,51 +28365,51 @@ Q q 1 0 0 1 50.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (entry) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_translation_exist) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mask) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm +1 0 0 1 40.01575 613.7008 cm Q q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 40.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt_and_show_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_vtd_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm -Q +1 0 0 1 50.01575 583.7008 cm q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (save_configuration) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_extended_page_tables) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 50.01575 577.7008 cm Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 50.01575 559.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_field) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_context_entry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (source_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cee) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 541.7008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 40.01575 523.7008 cm +1 0 0 1 50.01575 535.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging_memory_access) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_ce) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ree_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 50.01575 529.7008 cm +Q +q 1 0 0 1 50.01575 511.7008 cm q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28449,245 +28418,29 @@ Q q 1 0 0 1 50.01575 487.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 481.7008 cm -Q -q -1 0 0 1 40.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_paging_with_2nd_level_translation) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 451.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_paging_memory_access) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 445.7008 cm -Q -q -1 0 0 1 50.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 421.7008 cm -Q -q -1 0 0 1 40.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_reverse_translation) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (translation) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 391.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_reverse_translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 361.7008 cm -Q -q -1 0 0 1 40.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_translation) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 331.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_page) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 301.7008 cm -Q -q -1 0 0 1 50.01575 283.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (del_page) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 277.7008 cm -Q -q -1 0 0 1 50.01575 259.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (expand_pages) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (exp_size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 253.7008 cm -Q -q -1 0 0 1 50.01575 235.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_address_space) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 229.7008 cm -Q -q -1 0 0 1 50.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_mem_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (noattr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 205.7008 cm -Q -q -1 0 0 1 50.01575 187.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_pages_by_physaddr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 181.7008 cm -Q -q -1 0 0 1 50.01575 163.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_translation) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 157.7008 cm -Q -q -1 0 0 1 50.01575 139.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_translation_exist) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mask) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 133.7008 cm -Q -q -1 0 0 1 40.01575 115.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_vtd_page_tables) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 103.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_extended_page_tables) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_context_entry) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (source_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cee) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (57) Tj T* ET -Q -Q - -endstream -endobj -1262 0 obj -<< -/Length 9766 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_ce) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ree_index) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pt_and_show_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 50.01575 481.7008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_re) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 457.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 439.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_vtd_context) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (path) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ptr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 618.1008 cm +1 0 0 1 40.01575 390.1008 cm q 1 1 1 RG .3 w @@ -28699,20 +28452,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (pci module) Tj T* ET Q Q q -1 0 0 1 40.01575 576.1008 cm +1 0 0 1 40.01575 348.1008 cm q BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to of PCI/PCIe device hierarchy - enumerating PCI/PCIe devices - read/write access to PCI configuration) Tj T* (headers/registers - enumerating PCI expansion \(option\) ROMs - identifying PCI/PCIe devices MMIO and I/O ranges) Tj T* (\(BARs\)) Tj T* ET Q Q q -1 0 0 1 40.01575 560.1008 cm +1 0 0 1 40.01575 332.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 473.5008 cm +1 0 0 1 40.01575 245.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -28742,16 +28495,16 @@ Q Q Q q -1 0 0 1 40.01575 467.5008 cm +1 0 0 1 40.01575 239.5008 cm Q q -1 0 0 1 40.01575 437.5008 cm +1 0 0 1 40.01575 209.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_XROM_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InitSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EfiSignature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EfiSubsystem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EfiMachineType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CompressType) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EfiImageHeaderOffset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PCIROffset) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 425.5008 cm +1 0 0 1 50.01575 197.5008 cm q .933333 1 .8 rg n 33.35 0 186 12 re f* @@ -28759,16 +28512,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.p Q Q q -1 0 0 1 40.01575 419.5008 cm +1 0 0 1 40.01575 191.5008 cm Q q -1 0 0 1 40.01575 401.5008 cm +1 0 0 1 40.01575 173.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PCI_XROM_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ArchSpecific) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PCIROffset) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 389.5008 cm +1 0 0 1 50.01575 161.5008 cm q .933333 1 .8 rg n 33.35 0 186 12 re f* @@ -28776,16 +28529,16 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.p Q Q q -1 0 0 1 40.01575 383.5008 cm +1 0 0 1 40.01575 155.5008 cm Q q -1 0 0 1 40.01575 365.5008 cm +1 0 0 1 40.01575 137.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Pci) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 353.5008 cm +1 0 0 1 50.01575 125.5008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -28793,106 +28546,25 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 347.5008 cm +1 0 0 1 50.01575 119.5008 cm Q q -1 0 0 1 50.01575 329.5008 cm +1 0 0 1 50.01575 101.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (calc_bar_size) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 323.5008 cm +1 0 0 1 50.01575 95.50079 cm Q q -1 0 0 1 50.01575 305.5008 cm +1 0 0 1 50.01575 77.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_pci_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 299.5008 cm -Q -q -1 0 0 1 50.01575 281.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enumerate_devices) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 275.5008 cm -Q -q -1 0 0 1 50.01575 257.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enumerate_xroms) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (try_init) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_addr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 251.5008 cm -Q -q -1 0 0 1 50.01575 233.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_XROM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (try_init) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_addr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 227.5008 cm -Q -q -1 0 0 1 50.01575 209.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_DIDVID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 203.5008 cm -Q -q -1 0 0 1 50.01575 185.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_device_bars) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bCalcSize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 179.5008 cm -Q -q -1 0 0 1 50.01575 161.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 155.5008 cm -Q -q -1 0 0 1 50.01575 137.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_XROM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 131.5008 cm -Q -q -1 0 0 1 50.01575 113.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_pci_config_all) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 107.5008 cm -Q -q -1 0 0 1 50.01575 89.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 83.50079 cm +1 0 0 1 50.01575 71.50079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -28904,22 +28576,22 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (58) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (57) Tj T* ET Q Q endstream endobj -1263 0 obj +1259 0 obj << -/Length 8265 +/Length 10004 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enumerate_devices) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -28928,7 +28600,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enumerate_xroms) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (try_init) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_addr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28937,7 +28609,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_XROM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (try_init) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_addr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28946,7 +28618,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_DIDVID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -28955,102 +28627,88 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_device_bars) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bCalcSize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 661.7008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 40.01575 643.7008 cm +1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (PciDeviceNotFoundError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_enabled) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 631.7008 cm +1 0 0 1 50.01575 637.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_XROM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xrom_dump) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 625.7008 cm -Q -q -1 0 0 1 40.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (PciRuntimeError) Tj T* ET -Q +1 0 0 1 50.01575 613.7008 cm Q q 1 0 0 1 50.01575 595.7008 cm q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_pci_config_all) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 589.7008 cm +1 0 0 1 50.01575 589.7008 cm Q q -1 0 0 1 40.01575 571.7008 cm +1 0 0 1 50.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XROM) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (bus) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (dev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fun) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (en) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (base) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 559.7008 cm +1 0 0 1 50.01575 565.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 553.7008 cm -Q -q -1 0 0 1 40.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XROM_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InitSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InitEP) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PCIROffset) Tj 0 0 0 rg (\)) Tj T* ET -Q +1 0 0 1 50.01575 541.7008 cm Q q 1 0 0 1 50.01575 523.7008 cm q -.933333 1 .8 rg -n 33.35 0 162 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.pci.XROM_HEADER) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 517.7008 cm +1 0 0 1 50.01575 517.7008 cm Q q -1 0 0 1 40.01575 499.7008 cm +1 0 0 1 50.01575 499.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_device_name_by_didvid) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (did) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 493.7008 cm +1 0 0 1 50.01575 493.7008 cm Q q -1 0 0 1 40.01575 475.7008 cm +1 0 0 1 50.01575 475.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_vendor_name_by_vid) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vid) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 469.7008 cm +1 0 0 1 50.01575 469.7008 cm Q q -1 0 0 1 40.01575 451.7008 cm +1 0 0 1 50.01575 451.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_pci_XROMs) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_xroms) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -29059,11 +28717,72 @@ Q q 1 0 0 1 40.01575 427.7008 cm q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XROM) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (bus) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (dev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fun) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (en) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (base) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 415.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 409.7008 cm +Q +q +1 0 0 1 40.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XROM_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InitSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InitEP) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PCIROffset) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 379.7008 cm +q +.933333 1 .8 rg +n 33.35 0 162 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.pci.XROM_HEADER) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 373.7008 cm +Q +q +1 0 0 1 40.01575 355.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_device_name_by_didvid) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (did) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 349.7008 cm +Q +q +1 0 0 1 40.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_vendor_name_by_vid) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vid) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 325.7008 cm +Q +q +1 0 0 1 40.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_pci_XROMs) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_xroms) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 301.7008 cm +Q +q +1 0 0 1 40.01575 283.7008 cm +q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_pci_devices) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_devices) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 378.1008 cm +1 0 0 1 40.01575 234.1008 cm q 1 1 1 RG .3 w @@ -29075,16 +28794,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (pcidb module) Tj T* ET Q Q q -1 0 0 1 40.01575 360.1008 cm +1 0 0 1 40.01575 216.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (PCI Vendor & Device ID data.) Tj T* ET Q Q q -1 0 0 1 40.01575 348.1008 cm +1 0 0 1 40.01575 204.1008 cm Q q -1 0 0 1 40.01575 255.3008 cm +1 0 0 1 40.01575 111.3008 cm q .933333 .933333 .933333 rg n 0 92.8 515.2441 -92.8 re f* @@ -29132,10 +28851,32 @@ Q Q Q q -1 0 0 1 40.01575 249.3008 cm +1 0 0 1 40.01575 105.3008 cm Q q -1 0 0 1 40.01575 199.7008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (58) Tj T* ET +Q +Q + +endstream +endobj +1260 0 obj +<< +/Length 8140 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -29147,20 +28888,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (physmem module) Tj T* ET Q Q q -1 0 0 1 40.01575 181.7008 cm +1 0 0 1 40.01575 748.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to physical memory) Tj T* ET Q Q q -1 0 0 1 40.01575 165.7008 cm +1 0 0 1 40.01575 732.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 117.5008 cm +1 0 0 1 40.01575 683.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -29190,16 +28931,16 @@ Q Q Q q -1 0 0 1 40.01575 111.5008 cm +1 0 0 1 40.01575 677.9008 cm Q q -1 0 0 1 40.01575 93.50079 cm +1 0 0 1 40.01575 659.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Memory) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 81.50079 cm +1 0 0 1 50.01575 647.9008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -29207,7 +28948,211 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 75.50079 cm +1 0 0 1 50.01575 641.9008 cm +Q +q +1 0 0 1 50.01575 623.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (18446744073709551615) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 617.9008 cm +Q +q +1 0 0 1 50.01575 599.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 593.9008 cm +Q +q +1 0 0 1 50.01575 575.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 569.9008 cm +Q +q +1 0 0 1 50.01575 551.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 545.9008 cm +Q +q +1 0 0 1 50.01575 527.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 521.9008 cm +Q +q +1 0 0 1 50.01575 503.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 497.9008 cm +Q +q +1 0 0 1 50.01575 479.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 473.9008 cm +Q +q +1 0 0 1 50.01575 455.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_mem_bit) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 449.9008 cm +Q +q +1 0 0 1 50.01575 431.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 425.9008 cm +Q +q +1 0 0 1 50.01575 407.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 401.9008 cm +Q +q +1 0 0 1 50.01575 383.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 377.9008 cm +Q +q +1 0 0 1 50.01575 359.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 353.9008 cm +Q +q +1 0 0 1 50.01575 335.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 286.3008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smbios module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 274.3008 cm +Q +q +1 0 0 1 40.01575 256.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 244.3008 cm +q +.933333 1 .8 rg +n 33.35 0 168 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 238.3008 cm +Q +q +1 0 0 1 50.01575 220.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_smbios_table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 214.3008 cm +Q +q +1 0 0 1 50.01575 196.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_decoded_structs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (struct_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (force_32bit) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 190.3008 cm +Q +q +1 0 0 1 50.01575 172.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_header) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (raw_data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 166.3008 cm +Q +q +1 0 0 1 50.01575 148.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_raw_structs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (struct_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (force_32bit) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 124.3008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns a list of raw data blobs for each SMBIOS structure. The default is to process the 64bit entries if) Tj T* (available unless specifically specified.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 112.3008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Error: None) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 106.3008 cm +Q +q +1 0 0 1 50.01575 88.30079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_string_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (raw_data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 82.30079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -29225,162 +29170,96 @@ Q endstream endobj -1264 0 obj +1261 0 obj << -/Length 8835 +/Length 8969 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (18446744073709551615) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_2_x_ENTRY_POINT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Anchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MajorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MinorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MaxSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryRev) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (FormatArea0) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea3) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea4) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IntAnchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IntCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableAddr) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (NumStructures) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BcdRev) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm -Q +1 0 0 1 50.01575 727.7008 cm q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_2_x_ENTRY_POINT) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 40.01575 721.7008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_3_x_ENTRY_POINT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Anchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MajorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MinorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Docrev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryRev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (MaxSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableAddr) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm -Q +1 0 0 1 50.01575 679.7008 cm q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_3_x_ENTRY_POINT) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 40.01575 673.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 40.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_BIOS_INFO_2_0) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (handle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (vendor_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (version_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (segment) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (release_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (rom_sz) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (bios_char) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (strings) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm -Q +1 0 0 1 50.01575 631.7008 cm q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 270 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_BIOS_INFO_2_0_ENTRY) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 40.01575 625.7008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 40.01575 607.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_STRUCT_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Handle) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm -Q -q 1 0 0 1 50.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_mem_bit) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 234 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_STRUCT_HEADER) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 40.01575 589.7008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 40.01575 559.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_SYSTEM_INFO_2_0) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (handle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (manufacturer_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (product_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (version_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (serial_str) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (strings) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm -Q -q 1 0 0 1 50.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 469.7008 cm -Q -q -1 0 0 1 40.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MemoryAccessError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 439.7008 cm -q .933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +n 33.35 0 282 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_SYSTEM_INFO_2_0_ENTRY) Tj T* ET Q Q q -1 0 0 1 40.01575 433.7008 cm -Q -q -1 0 0 1 40.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MemoryRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 403.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 354.1008 cm +1 0 0 1 40.01575 498.1008 cm q 1 1 1 RG .3 w @@ -29388,20 +29267,26 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smbios module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smbus module) Tj T* ET Q Q q -1 0 0 1 40.01575 342.1008 cm -Q +1 0 0 1 40.01575 480.1008 cm q -1 0 0 1 40.01575 324.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to SMBus Controller) Tj T* ET Q Q q -1 0 0 1 50.01575 312.1008 cm +1 0 0 1 40.01575 474.1008 cm +Q +q +1 0 0 1 40.01575 456.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBus) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 444.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -29409,52 +29294,102 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 306.1008 cm +1 0 0 1 50.01575 438.1008 cm Q q -1 0 0 1 50.01575 288.1008 cm +1 0 0 1 50.01575 420.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_smbios_table) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SMBus_info) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 282.1008 cm +1 0 0 1 50.01575 414.1008 cm Q q -1 0 0 1 50.01575 264.1008 cm +1 0 0 1 50.01575 396.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_decoded_structs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (struct_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (force_32bit) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enable_SMBus_host_controller) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 258.1008 cm +1 0 0 1 50.01575 390.1008 cm Q q -1 0 0 1 50.01575 240.1008 cm +1 0 0 1 50.01575 372.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_header) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (raw_data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMBus_Base_Address) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 234.1008 cm +1 0 0 1 50.01575 366.1008 cm Q q -1 0 0 1 50.01575 216.1008 cm +1 0 0 1 50.01575 348.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_raw_structs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (struct_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (force_32bit) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMBus_HCFG) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 192.1008 cm +1 0 0 1 50.01575 342.1008 cm +Q q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns a list of raw data blobs for each SMBIOS structure. The default is to process the 64bit entries if) Tj T* (available unless specifically specified.) Tj T* ET +1 0 0 1 50.01575 324.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 180.1008 cm +1 0 0 1 50.01575 318.1008 cm +Q q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Error: None) Tj T* ET +1 0 0 1 50.01575 300.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_host_controller_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 294.1008 cm +Q +q +1 0 0 1 50.01575 276.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 270.1008 cm +Q +q +1 0 0 1 50.01575 252.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 246.1008 cm +Q +q +1 0 0 1 50.01575 228.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 222.1008 cm +Q +q +1 0 0 1 50.01575 204.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (reset_SMBus_controller) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 198.1008 cm +Q +q +1 0 0 1 50.01575 180.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -29463,28 +29398,33 @@ Q q 1 0 0 1 50.01575 156.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_string_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (raw_data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 150.1008 cm +1 0 0 1 40.01575 106.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* Q q -1 0 0 1 40.01575 108.1008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_2_x_ENTRY_POINT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Anchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MajorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MinorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MaxSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryRev) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (FormatArea0) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea3) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FormatArea4) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IntAnchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (IntCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableAddr) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (NumStructures) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BcdRev) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spd module) Tj T* ET Q Q q -1 0 0 1 50.01575 96.10079 cm +1 0 0 1 40.01575 88.50079 cm q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_2_x_ENTRY_POINT) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to Memory \(DRAM\) Serial Presence Detect \(SPD\) EEPROM) Tj T* ET Q Q q -1 0 0 1 40.01575 90.10079 cm +1 0 0 1 40.01575 70.50079 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -29502,79 +29442,231 @@ Q endstream endobj -1265 0 obj +1262 0 obj << -/Length 7985 +/Length 10014 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 751.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_3_x_ENTRY_POINT) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Anchor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryCs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryLen) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MajorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MinorVer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Docrev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (EntryRev) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (MaxSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TableAddr) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 739.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_3_x_ENTRY_POINT) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 733.7008 cm -Q -q 1 0 0 1 40.01575 703.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_BIOS_INFO_2_0) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (handle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (vendor_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (version_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (segment) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (release_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (rom_sz) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (bios_char) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (strings) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 62 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/184) Tj 0 0 0 rg ( ) Tj 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/153) Tj 0 0 0 rg T* 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/101) Tj 0 0 0 rg ( ) Tj 0 0 .501961 rg (http://en.wikipedia.org/wiki/Serial_presence_detect) Tj T* ET Q Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 40.01575 697.7008 cm +Q +q +1 0 0 1 40.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (smbus) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 667.7008 cm q .933333 1 .8 rg -n 33.35 0 270 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_BIOS_INFO_2_0_ENTRY) Tj T* ET +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 40.01575 685.7008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 40.01575 667.7008 cm +1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_STRUCT_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Handle) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 655.7008 cm +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (detect) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_spd_rom) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getDRAMDeviceType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getModuleType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isECC) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isSPDPresent) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.7008 cm +Q +q +1 0 0 1 50.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 469.7008 cm +Q +q +1 0 0 1 50.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 421.7008 cm +Q +q +1 0 0 1 50.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 397.7008 cm +Q +q +1 0 0 1 40.01575 379.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RowAddressCount) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 367.7008 cm q .933333 1 .8 rg -n 33.35 0 234 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_STRUCT_HEADER) Tj T* ET +n 33.35 0 138 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR) Tj T* ET Q Q q -1 0 0 1 40.01575 649.7008 cm +1 0 0 1 40.01575 361.7008 cm Q q -1 0 0 1 40.01575 619.7008 cm +1 0 0 1 40.01575 343.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBIOS_SYSTEM_INFO_2_0) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (handle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (manufacturer_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (product_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (version_str) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (serial_str) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (strings) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR2) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RowAddressCount) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 607.7008 cm +1 0 0 1 50.01575 331.7008 cm q .933333 1 .8 rg -n 33.35 0 282 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.smbios.SMBIOS_SYSTEM_INFO_2_0_ENTRY) Tj T* ET +n 33.35 0 144 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR2) Tj T* ET Q Q q -1 0 0 1 40.01575 558.1008 cm +1 0 0 1 40.01575 325.7008 cm +Q +q +1 0 0 1 40.01575 295.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR3) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ChipSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Addressing) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Voltages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleOrg) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (BusWidthECC) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FTB) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MTBDivident) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MTBDivisor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (tCKMin) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RsvdD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CASLo) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CASHi) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 283.7008 cm +q +.933333 1 .8 rg +n 33.35 0 144 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR3) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 277.7008 cm +Q +q +1 0 0 1 40.01575 247.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR4) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Density) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Addressing) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PackageType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OptFeatures) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ThernalRefresh) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OptFeatures1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ReservedA) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VDD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleOrg) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BusWidthECC) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ThermSensor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleTypeExt) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 235.7008 cm +q +.933333 1 .8 rg +n 33.35 0 144 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR4) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 229.7008 cm +Q +q +1 0 0 1 40.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SPD_REVISION) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (revision) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 205.7008 cm +Q +q +1 0 0 1 40.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dram_device_type_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (dram_type) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 181.7008 cm +Q +q +1 0 0 1 40.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (module_type_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (module_type) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 114.1008 cm q 1 1 1 RG .3 w @@ -29582,169 +29674,20 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smbus module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi module) Tj T* ET Q Q q -1 0 0 1 40.01575 540.1008 cm +1 0 0 1 40.01575 96.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to SMBus Controller) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to SPI Flash parts) Tj T* ET Q Q q -1 0 0 1 40.01575 534.1008 cm -Q -q -1 0 0 1 40.01575 516.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SMBus) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 504.1008 cm -q -.933333 1 .8 rg -n 33.35 0 168 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 498.1008 cm -Q -q -1 0 0 1 50.01575 480.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SMBus_info) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 474.1008 cm -Q -q -1 0 0 1 50.01575 456.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (enable_SMBus_host_controller) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 450.1008 cm -Q -q -1 0 0 1 50.01575 432.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMBus_Base_Address) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 426.1008 cm -Q -q -1 0 0 1 50.01575 408.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SMBus_HCFG) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 402.1008 cm -Q -q -1 0 0 1 50.01575 384.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 378.1008 cm -Q -q -1 0 0 1 50.01575 360.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_host_controller_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 354.1008 cm -Q -q -1 0 0 1 50.01575 336.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_SMBus_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 330.1008 cm -Q -q -1 0 0 1 50.01575 312.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 306.1008 cm -Q -q -1 0 0 1 50.01575 288.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 282.1008 cm -Q -q -1 0 0 1 50.01575 264.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (reset_SMBus_controller) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 258.1008 cm -Q -q -1 0 0 1 50.01575 240.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 234.1008 cm -Q -q -1 0 0 1 50.01575 216.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (target_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 166.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spd module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 148.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to Memory \(DRAM\) Serial Presence Detect \(SPD\) EEPROM) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 130.5008 cm +1 0 0 1 40.01575 80.10079 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 76.50079 cm -q -BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf) Tj 0 0 0 rg T* 0 0 .501961 rg (http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf) Tj 0 0 0 rg T* ET +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q @@ -29763,256 +29706,14 @@ Q endstream endobj -1266 0 obj +1263 0 obj << -/Length 10231 +/Length 6086 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 751.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/184) Tj 0 0 0 rg ( ) Tj 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/153) Tj 0 0 0 rg T* 0 0 .501961 rg (https://www.simmtester.com/News/PublicationArticle/101) Tj 0 0 0 rg ( ) Tj 0 0 .501961 rg (http://en.wikipedia.org/wiki/Serial_presence_detect) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 745.7008 cm -Q -q -1 0 0 1 40.01575 727.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (smbus) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 715.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (detect) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_spd_rom) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getDRAMDeviceType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getModuleType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isECC) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isSPDPresent) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (160) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 445.7008 cm -Q -q -1 0 0 1 40.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RowAddressCount) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 415.7008 cm -q -.933333 1 .8 rg -n 33.35 0 138 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 409.7008 cm -Q -q -1 0 0 1 40.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR2) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RowAddressCount) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 379.7008 cm -q -.933333 1 .8 rg -n 33.35 0 144 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR2) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 373.7008 cm -Q -q -1 0 0 1 40.01575 343.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR3) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ChipSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Addressing) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Voltages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleOrg) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (BusWidthECC) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FTB) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MTBDivident) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MTBDivisor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (tCKMin) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RsvdD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CASLo) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CASHi) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 331.7008 cm -q -.933333 1 .8 rg -n 33.35 0 144 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR3) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 325.7008 cm -Q -q -1 0 0 1 40.01575 295.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPD_DDR4) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (SPDBytes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DeviceType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Density) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Addressing) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (PackageType) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OptFeatures) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ThernalRefresh) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OptFeatures1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ReservedA) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VDD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleOrg) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BusWidthECC) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ThermSensor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ModuleTypeExt) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 283.7008 cm -q -.933333 1 .8 rg -n 33.35 0 144 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.spd.SPD_DDR4) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 277.7008 cm -Q -q -1 0 0 1 40.01575 259.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SPD_REVISION) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (revision) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 253.7008 cm -Q -q -1 0 0 1 40.01575 235.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dram_device_type_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (dram_type) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 229.7008 cm -Q -q -1 0 0 1 40.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (module_type_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (module_type) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 162.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 144.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to SPI Flash parts) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 128.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 70.30079 cm +1 0 0 1 40.01575 717.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -30028,7 +29729,7 @@ q .666667 .8 .6 RG .3 w .933333 1 .8 rg -n -4 0 494.4441 54 re B* +n -4 0 488.4441 54 re B* Q q BT 1 0 0 1 0 40 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_spi\( spi_fla, length \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_spi\( spi_fla, buf \)) Tj T* (>) Tj (>) Tj (>) Tj ( erase_spi_block\( spi_fla \)) Tj T* (>) Tj (>) Tj (>) Tj ( get_SPI_JEDEC_ID\(\)) Tj T* (>) Tj (>) Tj (>) Tj ( get_SPI_JEDEC_ID_decoded\(\)) Tj T* ET @@ -30042,32 +29743,10 @@ Q Q Q q -1 0 0 1 40.01575 66.18898 cm +1 0 0 1 40.01575 705.9008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (62) Tj T* ET -Q -Q - -endstream -endobj -1267 0 obj -<< -/Length 6562 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 640.9008 cm +1 0 0 1 40.01575 571.1008 cm q .933333 .933333 .933333 rg n 0 134.8 515.2441 -134.8 re f* @@ -30122,19 +29801,19 @@ Q Q Q q -1 0 0 1 40.01575 634.9008 cm +1 0 0 1 40.01575 565.1008 cm Q q -1 0 0 1 40.01575 628.9008 cm +1 0 0 1 40.01575 559.1008 cm Q q -1 0 0 1 40.01575 610.9008 cm +1 0 0 1 40.01575 541.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SPI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 598.9008 cm +1 0 0 1 50.01575 529.1008 cm q .933333 1 .8 rg n 33.35 0 168 12 re f* @@ -30142,205 +29821,178 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.h Q Q q -1 0 0 1 50.01575 592.9008 cm +1 0 0 1 50.01575 523.1008 cm Q q -1 0 0 1 50.01575 574.9008 cm +1 0 0 1 50.01575 505.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_hardware_sequencing) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 568.9008 cm +1 0 0 1 50.01575 499.1008 cm Q q -1 0 0 1 50.01575 550.9008 cm +1 0 0 1 50.01575 481.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (disable_BIOS_write_protection) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 544.9008 cm +1 0 0 1 50.01575 475.1008 cm Q q -1 0 0 1 50.01575 526.9008 cm +1 0 0 1 50.01575 457.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_BIOS_region) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 520.9008 cm +1 0 0 1 50.01575 451.1008 cm Q q -1 0 0 1 50.01575 502.9008 cm +1 0 0 1 50.01575 433.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_BIOS_write_protection) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 496.9008 cm +1 0 0 1 50.01575 427.1008 cm Q q -1 0 0 1 50.01575 478.9008 cm +1 0 0 1 50.01575 409.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_Flash_Descriptor) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 472.9008 cm +1 0 0 1 50.01575 403.1008 cm Q q -1 0 0 1 50.01575 454.9008 cm +1 0 0 1 50.01575 385.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_Flash_Regions) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 448.9008 cm +1 0 0 1 50.01575 379.1008 cm Q q -1 0 0 1 50.01575 430.9008 cm +1 0 0 1 50.01575 361.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_Protected_Ranges) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 424.9008 cm +1 0 0 1 50.01575 355.1008 cm Q q -1 0 0 1 50.01575 406.9008 cm +1 0 0 1 50.01575 337.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_Ranges_Access_Permissions) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 400.9008 cm +1 0 0 1 50.01575 331.1008 cm Q q -1 0 0 1 50.01575 382.9008 cm +1 0 0 1 50.01575 313.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_map) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 376.9008 cm +1 0 0 1 50.01575 307.1008 cm Q q -1 0 0 1 50.01575 358.9008 cm +1 0 0 1 50.01575 289.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (display_SPI_opcode_info) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 352.9008 cm +1 0 0 1 50.01575 283.1008 cm Q q -1 0 0 1 50.01575 334.9008 cm +1 0 0 1 50.01575 265.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (erase_spi_block) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 328.9008 cm +1 0 0 1 50.01575 259.1008 cm Q q -1 0 0 1 50.01575 310.9008 cm +1 0 0 1 50.01575 241.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_JEDEC_ID) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 304.9008 cm +1 0 0 1 50.01575 235.1008 cm Q q -1 0 0 1 50.01575 286.9008 cm +1 0 0 1 50.01575 217.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_JEDEC_ID_decoded) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 280.9008 cm +1 0 0 1 50.01575 211.1008 cm Q q -1 0 0 1 50.01575 262.9008 cm +1 0 0 1 50.01575 193.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_MMIO_base) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 256.9008 cm +1 0 0 1 50.01575 187.1008 cm Q q -1 0 0 1 50.01575 238.9008 cm +1 0 0 1 50.01575 169.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_Protected_Range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pr_num) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 232.9008 cm +1 0 0 1 50.01575 163.1008 cm Q q -1 0 0 1 50.01575 214.9008 cm +1 0 0 1 50.01575 145.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_SFDP) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 208.9008 cm +1 0 0 1 50.01575 139.1008 cm Q q -1 0 0 1 50.01575 190.9008 cm +1 0 0 1 50.01575 121.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_region) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_region_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 184.9008 cm +1 0 0 1 50.01575 115.1008 cm Q q -1 0 0 1 50.01575 166.9008 cm +1 0 0 1 50.01575 97.10079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_SPI_regions) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (all_regions) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 160.9008 cm +1 0 0 1 50.01575 91.10079 cm Q q -1 0 0 1 50.01575 142.9008 cm +1 0 0 1 50.01575 73.10079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ptmesg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 136.9008 cm -Q -q -1 0 0 1 50.01575 118.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_spi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data_byte_count) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 112.9008 cm -Q -q -1 0 0 1 50.01575 94.90079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_spi_to_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data_byte_count) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 88.90079 cm -Q -q -1 0 0 1 50.01575 70.90079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (spi_reg_read) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 50.01575 67.10079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -30352,22 +30004,22 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (63) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (62) Tj T* ET Q Q endstream endobj -1268 0 obj +1264 0 obj << -/Length 6598 +/Length 7016 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (spi_reg_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_spi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data_byte_count) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -30376,7 +30028,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_spi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_spi_to_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data_byte_count) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -30385,41 +30037,34 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_spi_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (spi_reg_read) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 709.7008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 40.01575 691.7008 cm +1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (SpiAccessError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (spi_reg_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 679.7008 cm +1 0 0 1 50.01575 685.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_spi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 673.7008 cm -Q -q -1 0 0 1 40.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (SpiRuntimeError) Tj T* ET -Q +1 0 0 1 50.01575 661.7008 cm Q q 1 0 0 1 50.01575 643.7008 cm q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_spi_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (spi_fla) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -30669,13 +30314,13 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (64) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (63) Tj T* ET Q Q endstream endobj -1269 0 obj +1265 0 obj << /Length 11915 >> @@ -30928,15 +30573,15 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (65) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (64) Tj T* ET Q Q endstream endobj -1270 0 obj +1266 0 obj << -/Length 7508 +/Length 7608 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -31105,24 +30750,7 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.t Q Q q -1 0 0 1 40.01575 385.7008 cm -Q -q -1 0 0 1 40.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (TpmRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 355.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 306.1008 cm +1 0 0 1 40.01575 342.1008 cm q 1 1 1 RG .3 w @@ -31134,70 +30762,85 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (tpm12_commands module) Tj T* ET Q Q q -1 0 0 1 40.01575 288.1008 cm +1 0 0 1 40.01575 324.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Definition for TPMv1.2 commands to use with TPM HAL) Tj T* ET Q Q q -1 0 0 1 40.01575 270.1008 cm +1 0 0 1 40.01575 306.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (TCG PC Client TPM Specification TCG TPM v1.2 Specification) Tj T* ET Q Q q -1 0 0 1 40.01575 264.1008 cm +1 0 0 1 40.01575 300.1008 cm Q q -1 0 0 1 40.01575 246.1008 cm +1 0 0 1 40.01575 282.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (continueselftest) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 210.1008 cm +1 0 0 1 50.01575 246.1008 cm q BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (TPM_ContinueSelfTest informs the TPM that it should complete self-test of all TPM functions. The TPM may) Tj T* (return success immediately and then perform the self-test, or it may perform the self-test and then return success) Tj T* (or failure.) Tj T* ET Q Q q -1 0 0 1 40.01575 204.1008 cm +1 0 0 1 40.01575 240.1008 cm Q q -1 0 0 1 40.01575 186.1008 cm +1 0 0 1 40.01575 222.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (forceclear) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 180.1008 cm +1 0 0 1 40.01575 216.1008 cm Q q -1 0 0 1 40.01575 162.1008 cm +1 0 0 1 40.01575 198.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcap) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 138.1008 cm +1 0 0 1 50.01575 174.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns current information regarding the TPM CapArea - Capabilities Area SubCapSize - Size of SubCapabilities) Tj T* (SubCap - Subcapabilities) Tj T* ET Q Q q +1 0 0 1 40.01575 168.1008 cm +Q +q +1 0 0 1 40.01575 150.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvread) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 138.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read a value from the NV store Index, Offset, Size) Tj T* ET +Q +Q +q 1 0 0 1 40.01575 132.1008 cm Q q 1 0 0 1 40.01575 114.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (nvread) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pcrread) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 102.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read a value from the NV store Index, Offset, Size) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (The TPM_PCRRead operation provides non-cryptographic reporting of the contents of a named PCR) Tj T* ET Q Q q @@ -31206,7 +30849,308 @@ Q q 1 0 0 1 40.01575 78.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pcrread) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (startup) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (65) Tj T* ET +Q +Q + +endstream +endobj +1267 0 obj +<< +/Length 6922 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (Execute a tpm_startup command. TPM_Startup is always preceded by TPM_Init, which is the physical indication) Tj T* (\(a system wide reset\) that TPM initialization is necessary Type of Startup to be used: 1: TPM_ST_CLEAR 2:) Tj T* (TPM_ST_STATE 3: TPM_ST_DEACTIVATED) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 690.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (tpm_eventlog module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 672.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Trusted Platform Module Event Log) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 654.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Based on the following specifications:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 624.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG EFI Platform Specification For TPM Family 1.1 or 1.2) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/) Tj 1 0 0 rg (TCG_EFI_Platform_1_22_Final_) Tj 0 0 0 rg (-v15.pdf) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 594.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG PC Client Specific Implementation Specification for Conventional BIOS\224, version 1.21) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 564.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG EFI Protocol Specification, Family \2232.0\224) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/EFI-Protocol-Specification-rev13-160330final.pdf) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 534.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG PC Client Platform Firmware Profile Specification ) Tj 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/PC-Cli) Tj T* (entSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 528.1008 cm +Q +q +1 0 0 1 40.01575 510.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFIFirmwareBlob) Tj /F1 10 Tf ( \() Tj .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (args) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 498.1008 cm +q +.933333 1 .8 rg +n 33.35 0 216 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.tpm_eventlog.TcgPcrEvent) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 492.1008 cm +Q +q +1 0 0 1 40.01575 474.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PcrLogParser) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (log) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 462.1008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 450.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Iterator over the events of a log.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 444.1008 cm +Q +q +1 0 0 1 50.01575 426.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (next) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 420.1008 cm +Q +q +1 0 0 1 40.01575 402.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SCRTMVersion) Tj /F1 10 Tf ( \() Tj .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (args) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 390.1008 cm +q +.933333 1 .8 rg +n 33.35 0 216 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.tpm_eventlog.TcgPcrEvent) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 384.1008 cm +Q +q +1 0 0 1 40.01575 366.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (TcgPcrEvent) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (pcr_index) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event_type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (digest) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 354.1008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 342.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (An Event \(TPM 1.2 format\) as recorded in the SML.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 336.1008 cm +Q +q +1 0 0 1 50.01575 318.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 0 0 0 rg (classmethod ) Tj /F6 10 Tf (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (log) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 306.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Try to read an event from the log.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 290.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Args:) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 275.1008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (log \(file-like\): Log where the event is stored.) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 60.01575 259.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Returns:) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 232.1008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 14 Tm T* ET +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL -0.087679 Tw (An instance of the created event. If a subclass exists for such event_type, an object of this class is returned.) Tj T* 0 Tw (Otherwise, a TcgPcrEvent is returned.) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 226.1008 cm +Q +q +1 0 0 1 40.01575 208.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (log) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 196.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple wrapper around PcrLogParser.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 146.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ucode module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 128.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Microcode update specific functionality \(for each CPU thread\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 112.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 66.18898 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 33.31181 Tm T* ET +q +1 0 0 1 20 17.31181 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 488.4441 25.2 re B* +Q +q +BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( ucode_update_id\( 0 \)) Tj T* (>) Tj (>) Tj (>) Tj ( load_ucode_update\( 0, ucode_buf \)) Tj T* ET +Q +Q +Q +Q +Q +q +Q Q Q q @@ -31225,110 +31169,53 @@ Q endstream endobj -1271 0 obj +1268 0 obj << -/Length 6936 +/Length 7771 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (The TPM_PCRRead operation provides non-cryptographic reporting of the contents of a named PCR) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (startup) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (command_argv) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (Execute a tpm_startup command. TPM_Startup is always preceded by TPM_Init, which is the physical indication) Tj T* (\(a system wide reset\) that TPM initialization is necessary Type of Startup to be used: 1: TPM_ST_CLEAR 2:) Tj T* (TPM_ST_STATE 3: TPM_ST_DEACTIVATED) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 654.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (tpm_eventlog module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 636.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Trusted Platform Module Event Log) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 618.1008 cm +1 0 0 1 40.01575 746.7008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Based on the following specifications:) Tj T* ET -Q -Q +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 16 Tm T* ET q -1 0 0 1 40.01575 588.1008 cm +1 0 0 1 20 0 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG EFI Platform Specification For TPM Family 1.1 or 1.2) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/) Tj 1 0 0 rg (TCG_EFI_Platform_1_22_Final_) Tj 0 0 0 rg (-v15.pdf) Tj T* ET -Q -Q q -1 0 0 1 40.01575 558.1008 cm +1 0 0 1 0 0 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG PC Client Specific Implementation Specification for Conventional BIOS\224, version 1.21) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/TCG_PCClientImplementation_1-21_1_00.pdf) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 528.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG EFI Protocol Specification, Family \2232.0\224) Tj T* 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/EFI-Protocol-Specification-rev13-160330final.pdf) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 498.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (TCG PC Client Platform Firmware Profile Specification ) Tj 0 0 .501961 rg (https://trustedcomputinggroup.org/wp-content/uploads/PC-Cli) Tj T* (entSpecific_Platform_Profile_for_TPM_2p0_Systems_v51.pdf) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 492.1008 cm -Q -q -1 0 0 1 40.01575 474.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFIFirmwareBlob) Tj /F1 10 Tf ( \() Tj .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (args) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 462.1008 cm +1 0 0 1 4.4 .4 cm q +.666667 .8 .6 RG +.3 w .933333 1 .8 rg -n 33.35 0 216 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.tpm_eventlog.TcgPcrEvent) Tj T* ET +n -4 0 488.4441 25.2 re B* +Q +q +BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( update_ucode_all_cpus\( 'ucode.pdb' \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_ucode_update_header\( 'ucode.pdb' \)) Tj T* ET +Q +Q +Q Q Q q -1 0 0 1 40.01575 456.1008 cm Q -q -1 0 0 1 40.01575 438.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PcrLogParser) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (log) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 426.1008 cm +1 0 0 1 40.01575 740.7008 cm +Q +q +1 0 0 1 40.01575 722.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Ucode) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 710.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -31336,142 +31223,87 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 414.1008 cm +1 0 0 1 50.01575 704.7008 cm +Q q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Iterator over the events of a log.) Tj T* ET +1 0 0 1 50.01575 686.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_thread_count) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 408.1008 cm +1 0 0 1 50.01575 680.7008 cm Q q -1 0 0 1 50.01575 390.1008 cm +1 0 0 1 50.01575 662.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (next) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 384.1008 cm +1 0 0 1 50.01575 656.7008 cm Q q -1 0 0 1 40.01575 366.1008 cm +1 0 0 1 50.01575 638.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (SCRTMVersion) Tj /F1 10 Tf ( \() Tj .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (args) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ucode_update_id) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 354.1008 cm +1 0 0 1 50.01575 632.7008 cm +Q +q +1 0 0 1 50.01575 614.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (update_ucode) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_file) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 608.7008 cm +Q +q +1 0 0 1 50.01575 590.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (update_ucode_all_cpus) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_file) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 584.7008 cm +Q +q +1 0 0 1 40.01575 554.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UcodeUpdateHeader) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (header_version) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (update_revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (date) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (processor_signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (checksum) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (loader_revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (processor_flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (data_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (total_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved3) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 542.7008 cm q .933333 1 .8 rg -n 33.35 0 216 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.tpm_eventlog.TcgPcrEvent) Tj T* ET +n 33.35 0 210 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.ucode.UcodeUpdateHeader) Tj T* ET Q Q q -1 0 0 1 40.01575 348.1008 cm +1 0 0 1 40.01575 536.7008 cm Q q -1 0 0 1 40.01575 330.1008 cm +1 0 0 1 40.01575 518.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (TcgPcrEvent) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (pcr_index) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event_type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (digest) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (event) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_ucode_update_header) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (pdb_ucode_buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 318.1008 cm +1 0 0 1 40.01575 512.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +1 0 0 1 40.01575 494.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_ucode_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (ucode_filename) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 306.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (An Event \(TPM 1.2 format\) as recorded in the SML.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 300.1008 cm -Q -q -1 0 0 1 50.01575 282.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 0 0 0 rg (classmethod ) Tj /F6 10 Tf (parse) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (log) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 270.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Try to read an event from the log.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 254.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Args:) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 239.1008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q -1 0 0 1 20 0 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (log \(file-like\): Log where the event is stored.) Tj T* ET -Q -Q -q -Q -Q -Q -q -1 0 0 1 60.01575 223.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Returns:) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 196.1008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 14 Tm T* ET -q -1 0 0 1 20 0 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL -0.087679 Tw (An instance of the created event. If a subclass exists for such event_type, an object of this class is returned.) Tj T* 0 Tw (Otherwise, a TcgPcrEvent is returned.) Tj T* ET -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 190.1008 cm -Q -q -1 0 0 1 40.01575 172.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (log) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 160.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple wrapper around PcrLogParser.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 110.5008 cm +1 0 0 1 40.01575 445.1008 cm q 1 1 1 RG .3 w @@ -31479,21 +31311,151 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ucode module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi module) Tj T* ET Q Q q -1 0 0 1 40.01575 92.50079 cm +1 0 0 1 40.01575 427.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Microcode update specific functionality \(for each CPU thread\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Main UEFI component using platform specific and common UEFI functionality) Tj T* ET Q Q q -1 0 0 1 40.01575 76.50079 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET +1 0 0 1 40.01575 421.1008 cm Q +q +1 0 0 1 40.01575 403.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UEFI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 391.1008 cm +q +.933333 1 .8 rg +n 33.35 0 168 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.1008 cm +Q +q +1 0 0 1 50.01575 367.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_EFI_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (uncompressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compression_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 361.1008 cm +Q +q +1 0 0 1 50.01575 343.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_EFI_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (compressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (uncompressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compression_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.1008 cm +Q +q +1 0 0 1 50.01575 319.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.1008 cm +Q +q +1 0 0 1 50.01575 295.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EFI_tables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.1008 cm +Q +q +1 0 0 1 50.01575 271.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EFI_variables_from_SPI) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.1008 cm +Q +q +1 0 0 1 50.01575 247.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_BootServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 241.1008 cm +Q +q +1 0 0 1 50.01575 223.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_Configuration_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 217.1008 cm +Q +q +1 0 0 1 50.01575 199.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_DXEServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 193.1008 cm +Q +q +1 0 0 1 50.01575 175.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_RuntimeServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 169.1008 cm +Q +q +1 0 0 1 50.01575 151.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_System_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 145.1008 cm +Q +q +1 0 0 1 50.01575 127.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_Table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_sig) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 121.1008 cm +Q +q +1 0 0 1 50.01575 103.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_variable_store) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rom_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 97.10079 cm +Q +q +1 0 0 1 50.01575 79.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_s3_bootscript) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.10079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -31511,141 +31473,164 @@ Q endstream endobj -1272 0 obj +1269 0 obj << -/Length 7728 +/Length 11890 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 727.5008 cm +1 0 0 1 50.01575 763.7008 cm q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 35.2 Tm T* ET -q -1 0 0 1 20 0 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 488.4441 44.4 re B* -Q -q -BT 1 0 0 1 0 30.4 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( ucode_update_id\( 0 \)) Tj T* (>) Tj (>) Tj (>) Tj ( load_ucode_update\( 0, ucode_buf \)) Tj T* (>) Tj (>) Tj (>) Tj ( update_ucode_all_cpus\( 'ucode.pdb' \)) Tj T* (>) Tj (>) Tj (>) Tj ( dump_ucode_update_header\( 'ucode.pdb' \)) Tj T* ET -Q -Q -Q -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 721.5008 cm -Q -q -1 0 0 1 40.01575 703.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Ucode) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 691.5008 cm +1 0 0 1 50.01575 757.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_s3_bootscript) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.5008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 667.5008 cm +1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_cpu_thread_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.5008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 643.5008 cm +1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_EFI_variables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (fname) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rom) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (authvars) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_fw_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.5008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 619.5008 cm +1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ucode_update_id) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_var_store) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (authvars) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.5008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 595.5008 cm +1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (update_ucode) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_file) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables_from_SPI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (BIOS_region_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (BIOS_region_size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 589.5008 cm +1 0 0 1 50.01575 637.7008 cm Q q -1 0 0 1 50.01575 571.5008 cm +1 0 0 1 50.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (update_ucode_all_cpus) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_file) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 565.5008 cm +1 0 0 1 50.01575 613.7008 cm Q q -1 0 0 1 40.01575 535.5008 cm +1 0 0 1 50.01575 595.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UcodeUpdateHeader) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (header_version) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (update_revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (date) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (processor_signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (checksum) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (loader_revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (processor_flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (data_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (total_size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (reserved3) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (var) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 523.5008 cm +1 0 0 1 50.01575 589.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 210 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.ucode.UcodeUpdateHeader) Tj T* ET +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 517.5008 cm +1 0 0 1 50.01575 565.7008 cm Q q -1 0 0 1 40.01575 499.5008 cm +1 0 0 1 50.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_ucode_update_header) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (pdb_ucode_buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_FWType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_nvram_format) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 493.5008 cm +1 0 0 1 40.01575 541.7008 cm Q q -1 0 0 1 40.01575 475.5008 cm +1 0 0 1 40.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_ucode_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (ucode_filename) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_EFI_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (efi_vars) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (nvram_pth) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 425.9008 cm +1 0 0 1 40.01575 517.7008 cm +Q +q +1 0 0 1 40.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr_string) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 493.7008 cm +Q +q +1 0 0 1 40.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_auth_attr_string) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 469.7008 cm +Q +q +1 0 0 1 40.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (identify_EFI_NVRAM) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 445.7008 cm +Q +q +1 0 0 1 40.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_script) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 421.7008 cm +Q +q +1 0 0 1 40.01575 391.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_efi_variable) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (offset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_buf) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (EFI_var_header) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_name) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_data) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_guid) Tj .839216 .701961 0 rg (,) Tj T* .396078 .588235 .639216 rg (efi_var_attributes) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 385.7008 cm +Q +q +1 0 0 1 40.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_sorted_EFI_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (variables) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 318.1008 cm q 1 1 1 RG .3 w @@ -31653,144 +31638,59 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_common module) Tj T* ET Q Q q -1 0 0 1 40.01575 407.9008 cm +1 0 0 1 40.01575 288.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Main UEFI component using platform specific and common UEFI functionality) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Common UEFI/EFI functionality including UEFI variables, Firmware Volumes, Secure Boot variables, S3 boot-script,) Tj T* (UEFI tables, etc.) Tj T* ET Q Q q -1 0 0 1 40.01575 401.9008 cm +1 0 0 1 40.01575 282.1008 cm Q q -1 0 0 1 40.01575 383.9008 cm +1 0 0 1 40.01575 180.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UEFI) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 86 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_BOOT_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (RaiseTPL) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RestoreTPL) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocatePages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreePages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemoryMap) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (AllocatePool) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreePool) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CreateEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetTimer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (WaitForEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SignalEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CloseEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CheckEvent) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (InstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ReinstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UninstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HandleProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (RegisterProtocolNotify) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateDevicePath) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InstallConfigurationTable) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LoadImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StartImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Exit) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (UnloadImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ExitBootServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetNextMonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Stall) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetWatchdogTimer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConnectController) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DisconnectController) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OpenProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CloseProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OpenProtocolInformation) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProtocolsPerHandle) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (LocateHandleBuffer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InstallMultipleProtocolInterfaces) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UninstallMultipleProtocolInterfaces) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (CalculateCrc32) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CopyMem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetMem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CreateEventEx) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 371.9008 cm +1 0 0 1 50.01575 168.1008 cm q .933333 1 .8 rg -n 33.35 0 168 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET +n 33.35 0 282 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_BOOT_SERVICES_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 365.9008 cm +1 0 0 1 40.01575 162.1008 cm Q q -1 0 0 1 50.01575 347.9008 cm +1 0 0 1 40.01575 144.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_EFI_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (uncompressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compression_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_CONFIGURATION_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 341.9008 cm -Q +1 0 0 1 50.01575 132.1008 cm q -1 0 0 1 50.01575 323.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_EFI_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (compressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (uncompressed_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (compression_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 317.9008 cm +1 0 0 1 40.01575 126.1008 cm Q q -1 0 0 1 50.01575 299.9008 cm +1 0 0 1 40.01575 72.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 38 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_DXE_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (AddMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocateMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreeMemorySpace) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (RemoveMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemorySpaceDescriptor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetMemorySpaceAttributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemorySpaceMap) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (AddIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocateIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreeIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RemoveIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetIoSpaceDescriptor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetIoSpaceMap) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Dispatch) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (Schedule) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Trust) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProcessFirmwareVolume) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 293.9008 cm -Q -q -1 0 0 1 50.01575 275.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EFI_tables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 269.9008 cm -Q -q -1 0 0 1 50.01575 251.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EFI_variables_from_SPI) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 245.9008 cm -Q -q -1 0 0 1 50.01575 227.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_BootServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 221.9008 cm -Q -q -1 0 0 1 50.01575 203.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_Configuration_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 197.9008 cm -Q -q -1 0 0 1 50.01575 179.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_DXEServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 173.9008 cm -Q -q -1 0 0 1 50.01575 155.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_RuntimeServices_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 149.9008 cm -Q -q -1 0 0 1 50.01575 131.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_System_Table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 125.9008 cm -Q -q -1 0 0 1 50.01575 107.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_Table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_sig) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 101.9008 cm -Q -q -1 0 0 1 50.01575 83.90079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_EFI_variable_store) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rom_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 77.90079 cm -Q -q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -31806,124 +31706,128 @@ Q endstream endobj -1273 0 obj +1270 0 obj << -/Length 11425 +/Length 8945 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_s3_bootscript) Tj /F2 10 Tf ( \(\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 276 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_DXE_SERVICES_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ERROR_STR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (error) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm -Q +1 0 0 1 50.01575 727.7008 cm q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_s3_bootscript) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Translates an EFI_STATUS value into its corresponding textual representation.) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 40.01575 721.7008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 40.01575 703.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_GUID_STR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 40.01575 697.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 40.01575 655.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_EFI_variables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (fname) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rom) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (authvars) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_fw_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_RUNTIME_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (GetTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetWakeupTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetWakeupTime) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (SetVirtualAddressMap) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConvertPointer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetVariable) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetNextVariableName) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetVariable) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (GetNextHighMonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ResetSystem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UpdateCapsule) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (QueryCapsuleCapabilities) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (QueryVariableInfo) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm -Q -q 1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_var_store) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (authvars) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 300 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_RUNTIME_SERVICES_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 40.01575 637.7008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 40.01575 607.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables_from_SPI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (BIOS_region_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (BIOS_region_size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_SYSTEM_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (FirmwareVendor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FirmwareRevision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConsoleInHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConIn) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConsoleOutHandle) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ConOut) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StandardErrorHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StdErr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RuntimeServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BootServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NumberOfTableEntries) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConfigurationTable) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm -Q -q 1 0 0 1 50.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_EFI_variables_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 240 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_SYSTEM_TABLE) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 40.01575 589.7008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 40.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (var) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SYSTEM_TABLE_REVISION) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (revision) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 40.01575 565.7008 cm Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 40.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable_from_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_TABLE_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CRC32) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 541.7008 cm -Q +1 0 0 1 50.01575 535.7008 cm q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_FWType) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_nvram_format) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 240 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_TABLE_HEADER) Tj T* ET Q Q q -1 0 0 1 40.01575 517.7008 cm +1 0 0 1 40.01575 529.7008 cm Q q -1 0 0 1 40.01575 499.7008 cm +1 0 0 1 40.01575 511.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_EFI_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (efi_vars) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (nvram_pth) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_VENDOR_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (VendorGuidData) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorTable) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 493.7008 cm +1 0 0 1 50.01575 499.7008 cm +q +.933333 1 .8 rg +n 33.35 0 240 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_VENDOR_TABLE) Tj T* ET +Q Q q -1 0 0 1 40.01575 475.7008 cm +1 0 0 1 50.01575 493.7008 cm +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_attr_string) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET +1 0 0 1 50.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VendorGuid) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -31932,7 +31836,7 @@ Q q 1 0 0 1 40.01575 451.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_auth_attr_string) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_EFI_VARIABLE_AUTHENTICATED) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -31941,7 +31845,7 @@ Q q 1 0 0 1 40.01575 427.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (identify_EFI_NVRAM) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_VARIABLE_ATTRIBUTE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_c) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_Mask) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -31950,73 +31854,11 @@ Q q 1 0 0 1 40.01575 403.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_script) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BOOTSCRIPT_ENTRY) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (script_type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (index) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (offset_in_script) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 397.7008 cm -Q -q -1 0 0 1 40.01575 367.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_efi_variable) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (offset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_buf) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (EFI_var_header) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_name) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_data) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (efi_var_guid) Tj .839216 .701961 0 rg (,) Tj T* .396078 .588235 .639216 rg (efi_var_attributes) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 361.7008 cm -Q -q -1 0 0 1 40.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_sorted_EFI_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (variables) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 294.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_common module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 264.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Common UEFI/EFI functionality including UEFI variables, Firmware Volumes, Secure Boot variables, S3 boot-script,) Tj T* (UEFI tables, etc.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 258.1008 cm -Q -q -1 0 0 1 40.01575 156.1008 cm -q -BT 1 0 0 1 0 86 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_BOOT_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (RaiseTPL) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RestoreTPL) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocatePages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreePages) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemoryMap) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (AllocatePool) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreePool) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CreateEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetTimer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (WaitForEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SignalEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CloseEvent) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CheckEvent) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (InstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ReinstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UninstallProtocolInterface) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HandleProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (RegisterProtocolNotify) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateDevicePath) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InstallConfigurationTable) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LoadImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StartImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Exit) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (UnloadImage) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ExitBootServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetNextMonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Stall) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetWatchdogTimer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConnectController) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (DisconnectController) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OpenProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CloseProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (OpenProtocolInformation) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProtocolsPerHandle) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (LocateHandleBuffer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (LocateProtocol) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (InstallMultipleProtocolInterfaces) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UninstallMultipleProtocolInterfaces) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (CalculateCrc32) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CopyMem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetMem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CreateEventEx) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 144.1008 cm -q -.933333 1 .8 rg -n 33.35 0 282 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_BOOT_SERVICES_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 138.1008 cm -Q -q -1 0 0 1 40.01575 120.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_CONFIGURATION_TABLE) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 108.1008 cm +1 0 0 1 50.01575 391.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -32024,15 +31866,133 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 40.01575 102.1008 cm +1 0 0 1 40.01575 385.7008 cm Q q -1 0 0 1 40.01575 72.10079 cm +1 0 0 1 40.01575 367.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_DXE_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (AddMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocateMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreeMemorySpace) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (RemoveMemorySpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemorySpaceDescriptor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetMemorySpaceAttributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetMemorySpaceMap) Tj 0 0 0 rg (,) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode) Tj T* ET Q Q q +1 0 0 1 50.01575 355.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 349.7008 cm +Q +q +1 0 0 1 50.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_DISPATCH_OPCODE) Tj /F4 10 Tf ( = 8) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 325.7008 cm +Q +q +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 1) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 301.7008 cm +Q +q +1 0 0 1 50.01575 283.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_WRITE_OPCODE) Tj /F4 10 Tf ( = 0) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 277.7008 cm +Q +q +1 0 0 1 50.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 3) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 253.7008 cm +Q +q +1 0 0 1 50.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE) Tj /F4 10 Tf ( = 2) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 5) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 205.7008 cm +Q +q +1 0 0 1 50.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE) Tj /F4 10 Tf ( = 4) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 181.7008 cm +Q +q +1 0 0 1 50.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE) Tj /F4 10 Tf ( = 6) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 157.7008 cm +Q +q +1 0 0 1 50.01575 139.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_STALL_OPCODE) Tj /F4 10 Tf ( = 7) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 133.7008 cm +Q +q +1 0 0 1 50.01575 115.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TERMINATE_OPCODE) Tj /F4 10 Tf ( = 255) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 109.7008 cm +Q +q +1 0 0 1 40.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode_EdkCompat) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 79.70079 cm +q +.933333 1 .8 rg +n 33.35 0 252 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.S3BootScriptOpcode) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -32048,165 +32008,154 @@ Q endstream endobj -1274 0 obj +1271 0 obj << -/Length 9420 +/Length 5512 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 751.7008 cm +1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf .396078 .588235 .639216 rg (AddIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (AllocateIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FreeIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RemoveIoSpace) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetIoSpaceDescriptor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetIoSpaceMap) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Dispatch) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (Schedule) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Trust) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ProcessFirmwareVolume) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_INFORMATION_OPCODE) Tj /F4 10 Tf ( = 10) Tj T* ET Q Q q +1 0 0 1 50.01575 757.7008 cm +Q +q 1 0 0 1 50.01575 739.7008 cm q -.933333 1 .8 rg -n 33.35 0 276 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_DXE_SERVICES_TABLE) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_POLL_OPCODE) Tj /F4 10 Tf ( = 9) Tj T* ET Q Q q -1 0 0 1 40.01575 733.7008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 40.01575 715.7008 cm +1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ERROR_STR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (error) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 12) Tj T* ET Q Q q -1 0 0 1 50.01575 703.7008 cm +1 0 0 1 50.01575 709.7008 cm +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Translates an EFI_STATUS value into its corresponding textual representation.) Tj T* ET +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE) Tj /F4 10 Tf ( = 11) Tj T* ET Q Q q -1 0 0 1 40.01575 697.7008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 40.01575 679.7008 cm +1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_GUID_STR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TABLE_OPCODE) Tj /F4 10 Tf ( = 170) Tj T* ET Q Q q -1 0 0 1 40.01575 673.7008 cm +1 0 0 1 40.01575 661.7008 cm Q q -1 0 0 1 40.01575 631.7008 cm +1 0 0 1 40.01575 643.7008 cm q -BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_RUNTIME_SERVICES_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (GetTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetWakeupTime) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetWakeupTime) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (SetVirtualAddressMap) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConvertPointer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetVariable) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (GetNextVariableName) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (SetVariable) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (GetNextHighMonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ResetSystem) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UpdateCapsule) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (QueryCapsuleCapabilities) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (QueryVariableInfo) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode_MDE) Tj T* ET Q Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 50.01575 631.7008 cm q .933333 1 .8 rg -n 33.35 0 300 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_RUNTIME_SERVICES_TABLE) Tj T* ET +n 33.35 0 252 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.S3BootScriptOpcode) Tj T* ET Q Q q -1 0 0 1 40.01575 613.7008 cm +1 0 0 1 50.01575 625.7008 cm Q q -1 0 0 1 40.01575 583.7008 cm +1 0 0 1 50.01575 607.7008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_SYSTEM_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (FirmwareVendor) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (FirmwareRevision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConsoleInHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConIn) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConsoleOutHandle) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (ConOut) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StandardErrorHandle) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (StdErr) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (RuntimeServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (BootServices) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NumberOfTableEntries) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ConfigurationTable) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE) Tj /F4 10 Tf ( = 9) Tj T* ET Q Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 50.01575 601.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 240 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_SYSTEM_TABLE) Tj T* ET +1 0 0 1 50.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_INFORMATION_OPCODE) Tj /F4 10 Tf ( = 10) Tj T* ET Q Q q -1 0 0 1 40.01575 565.7008 cm +1 0 0 1 50.01575 577.7008 cm Q q -1 0 0 1 40.01575 547.7008 cm +1 0 0 1 50.01575 559.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SYSTEM_TABLE_REVISION) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (revision) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_POLL_OPCODE) Tj /F4 10 Tf ( = 13) Tj T* ET Q Q q -1 0 0 1 40.01575 541.7008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 40.01575 523.7008 cm +1 0 0 1 50.01575 535.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_TABLE_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Revision) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CRC32) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_POLL_OPCODE) Tj /F4 10 Tf ( = 14) Tj T* ET Q Q q +1 0 0 1 50.01575 529.7008 cm +Q +q 1 0 0 1 50.01575 511.7008 cm q -.933333 1 .8 rg -n 33.35 0 240 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_TABLE_HEADER) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE) Tj /F4 10 Tf ( = 16) Tj T* ET Q Q q -1 0 0 1 40.01575 505.7008 cm +1 0 0 1 50.01575 505.7008 cm Q q -1 0 0 1 40.01575 487.7008 cm +1 0 0 1 50.01575 487.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_VENDOR_TABLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (VendorGuidData) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorTable) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 12) Tj T* ET Q Q q -1 0 0 1 50.01575 475.7008 cm +1 0 0 1 50.01575 481.7008 cm +Q q -.933333 1 .8 rg -n 33.35 0 240 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.EFI_VENDOR_TABLE) Tj T* ET +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE) Tj /F4 10 Tf ( = 11) Tj T* ET Q Q q -1 0 0 1 50.01575 469.7008 cm +1 0 0 1 50.01575 457.7008 cm Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 50.01575 439.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VendorGuid) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE) Tj /F4 10 Tf ( = 15) Tj T* ET Q Q q -1 0 0 1 40.01575 445.7008 cm +1 0 0 1 40.01575 433.7008 cm Q q -1 0 0 1 40.01575 427.7008 cm +1 0 0 1 40.01575 415.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_EFI_VARIABLE_AUTHENTICATED) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (attr) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptSmbusOperation) Tj T* ET Q Q q -1 0 0 1 40.01575 421.7008 cm -Q -q -1 0 0 1 40.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_VARIABLE_ATTRIBUTE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_c) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_Mask) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 397.7008 cm -Q -q -1 0 0 1 40.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BOOTSCRIPT_ENTRY) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (script_type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (index) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (offset_in_script) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 367.7008 cm +1 0 0 1 50.01575 403.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -32214,20 +32163,30 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 40.01575 361.7008 cm +1 0 0 1 50.01575 397.7008 cm Q q -1 0 0 1 40.01575 343.7008 cm +1 0 0 1 50.01575 379.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (BWBR_PROCESS_CALL) Tj /F4 10 Tf ( = 11) Tj T* ET Q Q q +1 0 0 1 50.01575 373.7008 cm +Q +q +1 0 0 1 50.01575 355.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (PROCESS_CALL) Tj /F4 10 Tf ( = 10) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 349.7008 cm +Q +q 1 0 0 1 50.01575 331.7008 cm q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (QUICK_READ) Tj /F4 10 Tf ( = 0) Tj T* ET Q Q q @@ -32236,7 +32195,7 @@ Q q 1 0 0 1 50.01575 307.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_DISPATCH_OPCODE) Tj /F4 10 Tf ( = 8) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (QUICK_WRITE) Tj /F4 10 Tf ( = 1) Tj T* ET Q Q q @@ -32245,7 +32204,7 @@ Q q 1 0 0 1 50.01575 283.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 1) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_BLOCK) Tj /F4 10 Tf ( = 8) Tj T* ET Q Q q @@ -32254,7 +32213,7 @@ Q q 1 0 0 1 50.01575 259.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_WRITE_OPCODE) Tj /F4 10 Tf ( = 0) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_BYTE) Tj /F4 10 Tf ( = 4) Tj T* ET Q Q q @@ -32263,7 +32222,7 @@ Q q 1 0 0 1 50.01575 235.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 3) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_WORD) Tj /F4 10 Tf ( = 6) Tj T* ET Q Q q @@ -32272,7 +32231,7 @@ Q q 1 0 0 1 50.01575 211.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_WRITE_OPCODE) Tj /F4 10 Tf ( = 2) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (RECEIVE_BYTE) Tj /F4 10 Tf ( = 2) Tj T* ET Q Q q @@ -32281,7 +32240,7 @@ Q q 1 0 0 1 50.01575 187.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 5) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SEND_BYTE) Tj /F4 10 Tf ( = 3) Tj T* ET Q Q q @@ -32290,7 +32249,7 @@ Q q 1 0 0 1 50.01575 163.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_WRITE_OPCODE) Tj /F4 10 Tf ( = 4) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_BLOCK) Tj /F4 10 Tf ( = 9) Tj T* ET Q Q q @@ -32299,7 +32258,7 @@ Q q 1 0 0 1 50.01575 139.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_SMBUS_EXECUTE_OPCODE) Tj /F4 10 Tf ( = 6) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_BYTE) Tj /F4 10 Tf ( = 5) Tj T* ET Q Q q @@ -32308,26 +32267,28 @@ Q q 1 0 0 1 50.01575 115.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_STALL_OPCODE) Tj /F4 10 Tf ( = 7) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_WORD) Tj /F4 10 Tf ( = 7) Tj T* ET Q Q q -1 0 0 1 50.01575 109.7008 cm +1 0 0 1 40.01575 109.7008 cm Q q -1 0 0 1 50.01575 91.70079 cm +1 0 0 1 40.01575 91.70079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TERMINATE_OPCODE) Tj /F4 10 Tf ( = 255) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptWidth) Tj T* ET Q Q q -1 0 0 1 40.01575 85.70079 cm +1 0 0 1 50.01575 79.70079 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q Q q -1 0 0 1 40.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode_EdkCompat) Tj T* ET -Q +1 0 0 1 50.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -32345,18 +32306,16 @@ Q endstream endobj -1275 0 obj +1272 0 obj << -/Length 5549 +/Length 5247 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -.933333 1 .8 rg -n 33.35 0 252 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.S3BootScriptOpcode) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT16) Tj /F4 10 Tf ( = 1) Tj T* ET Q Q q @@ -32365,7 +32324,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_INFORMATION_OPCODE) Tj /F4 10 Tf ( = 10) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT32) Tj /F4 10 Tf ( = 2) Tj T* ET Q Q q @@ -32374,7 +32333,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_POLL_OPCODE) Tj /F4 10 Tf ( = 9) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT64) Tj /F4 10 Tf ( = 3) Tj T* ET Q Q q @@ -32383,42 +32342,42 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 12) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT8) Tj /F4 10 Tf ( = 0) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 40.01575 685.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 40.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE) Tj /F4 10 Tf ( = 11) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (StatusCode) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm -Q +1 0 0 1 50.01575 655.7008 cm q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TABLE_OPCODE) Tj /F4 10 Tf ( = 170) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 40.01575 637.7008 cm +1 0 0 1 50.01575 649.7008 cm Q q -1 0 0 1 40.01575 619.7008 cm +1 0 0 1 50.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptOpcode_MDE) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ABORTED) Tj /F4 10 Tf ( = 21) Tj T* ET Q Q q +1 0 0 1 50.01575 625.7008 cm +Q +q 1 0 0 1 50.01575 607.7008 cm q -.933333 1 .8 rg -n 33.35 0 252 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_common.S3BootScriptOpcode) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ACCESS_DENIED) Tj /F4 10 Tf ( = 15) Tj T* ET Q Q q @@ -32427,7 +32386,7 @@ Q q 1 0 0 1 50.01575 583.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_DISPATCH_2_OPCODE) Tj /F4 10 Tf ( = 9) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ALREADY_STARTED) Tj /F4 10 Tf ( = 20) Tj T* ET Q Q q @@ -32436,7 +32395,7 @@ Q q 1 0 0 1 50.01575 559.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_INFORMATION_OPCODE) Tj /F4 10 Tf ( = 10) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BAD_BUFFER_SIZE) Tj /F4 10 Tf ( = 4) Tj T* ET Q Q q @@ -32445,7 +32404,7 @@ Q q 1 0 0 1 50.01575 535.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_IO_POLL_OPCODE) Tj /F4 10 Tf ( = 13) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BUFFER_TOO_SMALL) Tj /F4 10 Tf ( = 5) Tj T* ET Q Q q @@ -32454,7 +32413,7 @@ Q q 1 0 0 1 50.01575 511.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_MEM_POLL_OPCODE) Tj /F4 10 Tf ( = 14) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_COMPROMISED_DATA) Tj /F4 10 Tf ( = 33) Tj T* ET Q Q q @@ -32463,7 +32422,7 @@ Q q 1 0 0 1 50.01575 487.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_POLL_OPCODE) Tj /F4 10 Tf ( = 16) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_CRC_ERROR) Tj /F4 10 Tf ( = 27) Tj T* ET Q Q q @@ -32472,7 +32431,7 @@ Q q 1 0 0 1 50.01575 463.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_READ_WRITE_OPCODE) Tj /F4 10 Tf ( = 12) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_DEVICE_ERROR) Tj /F4 10 Tf ( = 7) Tj T* ET Q Q q @@ -32481,7 +32440,7 @@ Q q 1 0 0 1 50.01575 439.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG2_WRITE_OPCODE) Tj /F4 10 Tf ( = 11) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_END_OF_FILE) Tj /F4 10 Tf ( = 31) Tj T* ET Q Q q @@ -32490,142 +32449,134 @@ Q q 1 0 0 1 50.01575 415.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_PCI_CONFIG_POLL_OPCODE) Tj /F4 10 Tf ( = 15) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_END_OF_MEDIA) Tj /F4 10 Tf ( = 28) Tj T* ET Q Q q -1 0 0 1 40.01575 409.7008 cm +1 0 0 1 50.01575 409.7008 cm Q q -1 0 0 1 40.01575 391.7008 cm +1 0 0 1 50.01575 391.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptSmbusOperation) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_HTTP_ERROR) Tj /F4 10 Tf ( = 35) Tj T* ET Q Q q -1 0 0 1 50.01575 379.7008 cm +1 0 0 1 60.01575 367.7008 cm q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_WARN_UNKNOWN_GLYPH = 1 EFI_WARN_DELETE_FAILURE = 2 EFI_WARN_WRITE_FAILURE = 3) Tj T* (EFI_WARN_BUFFER_TOO_SMALL = 4 EFI_WARN_STALE_DATA = 5 EFI_WARN_FILE_SYSTEM = 6) Tj T* ET Q Q q -1 0 0 1 50.01575 373.7008 cm +1 0 0 1 50.01575 361.7008 cm Q q -1 0 0 1 50.01575 355.7008 cm +1 0 0 1 50.01575 343.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (BWBR_PROCESS_CALL) Tj /F4 10 Tf ( = 11) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ICMP_ERROR) Tj /F4 10 Tf ( = 22) Tj T* ET Q Q q -1 0 0 1 50.01575 349.7008 cm +1 0 0 1 50.01575 337.7008 cm Q q -1 0 0 1 50.01575 331.7008 cm +1 0 0 1 50.01575 319.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (PROCESS_CALL) Tj /F4 10 Tf ( = 10) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INCOMPATIBLE_VERSION) Tj /F4 10 Tf ( = 25) Tj T* ET Q Q q -1 0 0 1 50.01575 325.7008 cm +1 0 0 1 50.01575 313.7008 cm Q q -1 0 0 1 50.01575 307.7008 cm +1 0 0 1 50.01575 295.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (QUICK_READ) Tj /F4 10 Tf ( = 0) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INVALID_LANGUAGE) Tj /F4 10 Tf ( = 32) Tj T* ET Q Q q -1 0 0 1 50.01575 301.7008 cm +1 0 0 1 50.01575 289.7008 cm Q q -1 0 0 1 50.01575 283.7008 cm +1 0 0 1 50.01575 271.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (QUICK_WRITE) Tj /F4 10 Tf ( = 1) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INVALID_PARAMETER) Tj /F4 10 Tf ( = 2) Tj T* ET Q Q q -1 0 0 1 50.01575 277.7008 cm +1 0 0 1 50.01575 265.7008 cm Q q -1 0 0 1 50.01575 259.7008 cm +1 0 0 1 50.01575 247.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_BLOCK) Tj /F4 10 Tf ( = 8) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_LOAD_ERROR) Tj /F4 10 Tf ( = 1) Tj T* ET Q Q q -1 0 0 1 50.01575 253.7008 cm +1 0 0 1 50.01575 241.7008 cm Q q -1 0 0 1 50.01575 235.7008 cm +1 0 0 1 50.01575 223.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_BYTE) Tj /F4 10 Tf ( = 4) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_MEDIA_CHANGED) Tj /F4 10 Tf ( = 13) Tj T* ET Q Q q -1 0 0 1 50.01575 229.7008 cm +1 0 0 1 50.01575 217.7008 cm Q q -1 0 0 1 50.01575 211.7008 cm +1 0 0 1 50.01575 199.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (READ_WORD) Tj /F4 10 Tf ( = 6) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_FOUND) Tj /F4 10 Tf ( = 14) Tj T* ET Q Q q -1 0 0 1 50.01575 205.7008 cm +1 0 0 1 50.01575 193.7008 cm Q q -1 0 0 1 50.01575 187.7008 cm +1 0 0 1 50.01575 175.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (RECEIVE_BYTE) Tj /F4 10 Tf ( = 2) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_READY) Tj /F4 10 Tf ( = 6) Tj T* ET Q Q q -1 0 0 1 50.01575 181.7008 cm +1 0 0 1 50.01575 169.7008 cm Q q -1 0 0 1 50.01575 163.7008 cm +1 0 0 1 50.01575 151.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SEND_BYTE) Tj /F4 10 Tf ( = 3) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_STARTED) Tj /F4 10 Tf ( = 19) Tj T* ET Q Q q -1 0 0 1 50.01575 157.7008 cm +1 0 0 1 50.01575 145.7008 cm Q q -1 0 0 1 50.01575 139.7008 cm +1 0 0 1 50.01575 127.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_BLOCK) Tj /F4 10 Tf ( = 9) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_MAPPING) Tj /F4 10 Tf ( = 17) Tj T* ET Q Q q -1 0 0 1 50.01575 133.7008 cm +1 0 0 1 50.01575 121.7008 cm Q q -1 0 0 1 50.01575 115.7008 cm +1 0 0 1 50.01575 103.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_BYTE) Tj /F4 10 Tf ( = 5) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_MEDIA) Tj /F4 10 Tf ( = 12) Tj T* ET Q Q q -1 0 0 1 50.01575 109.7008 cm +1 0 0 1 50.01575 97.70079 cm Q q -1 0 0 1 50.01575 91.70079 cm +1 0 0 1 50.01575 79.70079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (WRITE_WORD) Tj /F4 10 Tf ( = 7) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_RESPONSE) Tj /F4 10 Tf ( = 16) Tj T* ET Q Q q -1 0 0 1 40.01575 85.70079 cm -Q -q -1 0 0 1 40.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptWidth) Tj T* ET -Q +1 0 0 1 50.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -32643,18 +32594,16 @@ Q endstream endobj -1276 0 obj +1273 0 obj << -/Length 5278 +/Length 9216 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_OUT_OF_RESOURCES) Tj /F4 10 Tf ( = 9) Tj T* ET Q Q q @@ -32663,7 +32612,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT16) Tj /F4 10 Tf ( = 1) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_PROTOCOL_ERROR) Tj /F4 10 Tf ( = 24) Tj T* ET Q Q q @@ -32672,7 +32621,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT32) Tj /F4 10 Tf ( = 2) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SECURITY_VIOLATION) Tj /F4 10 Tf ( = 26) Tj T* ET Q Q q @@ -32681,7 +32630,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT64) Tj /F4 10 Tf ( = 3) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SUCCESS) Tj /F4 10 Tf ( = 0) Tj T* ET Q Q q @@ -32690,20 +32639,101 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_WIDTH_UINT8) Tj /F4 10 Tf ( = 0) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_TFTP_ERROR) Tj /F4 10 Tf ( = 23) Tj T* ET Q Q q -1 0 0 1 40.01575 661.7008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 40.01575 643.7008 cm +1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (StatusCode) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_TIMEOUT) Tj /F4 10 Tf ( = 18) Tj T* ET Q Q q -1 0 0 1 50.01575 631.7008 cm +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_UNSUPPORTED) Tj /F4 10 Tf ( = 3) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_VOLUME_CORRUPTED) Tj /F4 10 Tf ( = 10) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_VOLUME_FULL) Tj /F4 10 Tf ( = 11) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_WRITE_PROTECTED) Tj /F4 10 Tf ( = 8) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 541.7008 cm +Q +q +1 0 0 1 40.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (align) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (of) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 517.7008 cm +Q +q +1 0 0 1 40.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (bit_set) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (value) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (mask) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 493.7008 cm +Q +q +1 0 0 1 40.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_3b_size) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 469.7008 cm +Q +q +1 0 0 1 40.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_nvar_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (name_offset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (isAscii) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 445.7008 cm +Q +q +1 0 0 1 40.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_dispatch) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (entrypoint) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (context) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 415.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -32711,211 +32741,154 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 625.7008 cm +1 0 0 1 40.01575 409.7008 cm Q q -1 0 0 1 50.01575 607.7008 cm +1 0 0 1 40.01575 391.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ABORTED) Tj /F4 10 Tf ( = 21) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_io_pci_mem) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (unknown) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (count) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (buffer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (value) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (mask) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 601.7008 cm -Q +1 0 0 1 50.01575 379.7008 cm q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ACCESS_DENIED) Tj /F4 10 Tf ( = 15) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 577.7008 cm +1 0 0 1 40.01575 373.7008 cm Q q -1 0 0 1 50.01575 559.7008 cm +1 0 0 1 40.01575 355.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ALREADY_STARTED) Tj /F4 10 Tf ( = 20) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_mem_poll) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (duration) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (looptimes) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 553.7008 cm -Q +1 0 0 1 50.01575 343.7008 cm q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BAD_BUFFER_SIZE) Tj /F4 10 Tf ( = 4) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 529.7008 cm +1 0 0 1 40.01575 337.7008 cm Q q -1 0 0 1 50.01575 511.7008 cm +1 0 0 1 40.01575 319.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BUFFER_TOO_SMALL) Tj /F4 10 Tf ( = 5) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_smbus_execute) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (command) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (operation) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (peccheck) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 505.7008 cm -Q +1 0 0 1 50.01575 307.7008 cm q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_COMPROMISED_DATA) Tj /F4 10 Tf ( = 33) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 481.7008 cm +1 0 0 1 40.01575 301.7008 cm Q q -1 0 0 1 50.01575 463.7008 cm +1 0 0 1 40.01575 283.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_CRC_ERROR) Tj /F4 10 Tf ( = 27) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_stall) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (duration) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_DEVICE_ERROR) Tj /F4 10 Tf ( = 7) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_END_OF_FILE) Tj /F4 10 Tf ( = 31) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_END_OF_MEDIA) Tj /F4 10 Tf ( = 28) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_HTTP_ERROR) Tj /F4 10 Tf ( = 35) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 343.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_WARN_UNKNOWN_GLYPH = 1 EFI_WARN_DELETE_FAILURE = 2 EFI_WARN_WRITE_FAILURE = 3) Tj T* (EFI_WARN_BUFFER_TOO_SMALL = 4 EFI_WARN_STALE_DATA = 5 EFI_WARN_FILE_SYSTEM = 6) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_ICMP_ERROR) Tj /F4 10 Tf ( = 22) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 313.7008 cm -Q -q -1 0 0 1 50.01575 295.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INCOMPATIBLE_VERSION) Tj /F4 10 Tf ( = 25) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q 1 0 0 1 50.01575 271.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INVALID_LANGUAGE) Tj /F4 10 Tf ( = 32) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 265.7008 cm +1 0 0 1 40.01575 265.7008 cm Q q -1 0 0 1 50.01575 247.7008 cm +1 0 0 1 40.01575 247.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_INVALID_PARAMETER) Tj /F4 10 Tf ( = 2) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_terminate) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 241.7008 cm -Q +1 0 0 1 50.01575 235.7008 cm q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_LOAD_ERROR) Tj /F4 10 Tf ( = 1) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 217.7008 cm +1 0 0 1 40.01575 229.7008 cm +Q +q +1 0 0 1 40.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_unknown) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 50.01575 199.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_MEDIA_CHANGED) Tj /F4 10 Tf ( = 13) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 193.7008 cm +1 0 0 1 40.01575 193.7008 cm Q q -1 0 0 1 50.01575 175.7008 cm +1 0 0 1 40.01575 175.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_FOUND) Tj /F4 10 Tf ( = 14) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_auth_var) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 169.7008 cm +1 0 0 1 40.01575 169.7008 cm Q q -1 0 0 1 50.01575 151.7008 cm +1 0 0 1 40.01575 151.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_READY) Tj /F4 10 Tf ( = 6) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_efivar_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (fname) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (var) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (var_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 145.7008 cm +1 0 0 1 40.01575 145.7008 cm Q q -1 0 0 1 50.01575 127.7008 cm +1 0 0 1 40.01575 127.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NOT_STARTED) Tj /F4 10 Tf ( = 19) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_esal_var) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 121.7008 cm +1 0 0 1 40.01575 121.7008 cm Q q -1 0 0 1 50.01575 103.7008 cm +1 0 0 1 40.01575 103.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_MAPPING) Tj /F4 10 Tf ( = 17) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_external) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 97.70079 cm +1 0 0 1 40.01575 97.70079 cm Q q -1 0 0 1 50.01575 79.70079 cm +1 0 0 1 40.01575 79.70079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_MEDIA) Tj /F4 10 Tf ( = 12) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_pkcs7) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 73.70079 cm +1 0 0 1 40.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -32933,106 +32906,106 @@ Q endstream endobj -1277 0 obj +1274 0 obj << -/Length 9135 +/Length 8801 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_NO_RESPONSE) Tj /F4 10 Tf ( = 16) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_OUT_OF_RESOURCES) Tj /F4 10 Tf ( = 9) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048_sha1) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 40.01575 733.7008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_PROTOCOL_ERROR) Tj /F4 10 Tf ( = 24) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 40.01575 709.7008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SECURITY_VIOLATION) Tj /F4 10 Tf ( = 26) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sb_db) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 40.01575 685.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 40.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_SUCCESS) Tj /F4 10 Tf ( = 0) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha1) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 40.01575 661.7008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 40.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_TFTP_ERROR) Tj /F4 10 Tf ( = 23) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha224) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 40.01575 637.7008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 40.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_TIMEOUT) Tj /F4 10 Tf ( = 18) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm +1 0 0 1 40.01575 613.7008 cm Q q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 40.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_UNSUPPORTED) Tj /F4 10 Tf ( = 3) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha384) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 40.01575 589.7008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 40.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_VOLUME_CORRUPTED) Tj /F4 10 Tf ( = 10) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha512) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 40.01575 565.7008 cm Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 40.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_VOLUME_FULL) Tj /F4 10 Tf ( = 11) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 541.7008 cm +1 0 0 1 40.01575 541.7008 cm Q q -1 0 0 1 50.01575 523.7008 cm +1 0 0 1 40.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_WRITE_PROTECTED) Tj /F4 10 Tf ( = 8) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33041,7 +33014,7 @@ Q q 1 0 0 1 40.01575 499.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (align) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (of) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha384) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33050,38 +33023,75 @@ Q q 1 0 0 1 40.01575 475.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (bit_set) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (value) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (mask) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha512) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 469.7008 cm +1 0 0 1 40.01575 426.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* Q q -1 0 0 1 40.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_3b_size) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_fv module) Tj T* ET Q Q q -1 0 0 1 40.01575 445.7008 cm +1 0 0 1 40.01575 414.1008 cm Q q -1 0 0 1 40.01575 427.7008 cm +1 0 0 1 40.01575 396.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_nvar_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (name_offset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (isAscii) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DecodeSection) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (SecType) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (SecBody) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (SecHeaderSize) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 421.7008 cm +1 0 0 1 40.01575 390.1008 cm Q q -1 0 0 1 40.01575 403.7008 cm +1 0 0 1 40.01575 372.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_dispatch) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (entrypoint) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (context) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_FILE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Checksum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CalcSum) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 391.7008 cm +1 0 0 1 50.01575 360.1008 cm +q +.933333 1 .8 rg +n 33.35 0 180 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 354.1008 cm +Q +q +1 0 0 1 40.01575 336.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_FV) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Checksum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ExtHeaderOffset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CalcSum) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 324.1008 cm +q +.933333 1 .8 rg +n 33.35 0 180 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 318.1008 cm +Q +q +1 0 0 1 40.01575 300.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_MODULE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 288.1008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -33089,145 +33099,87 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 40.01575 385.7008 cm +1 0 0 1 50.01575 282.1008 cm Q q -1 0 0 1 40.01575 367.7008 cm +1 0 0 1 50.01575 264.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_io_pci_mem) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (unknown) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (count) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (buffer) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (value) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (mask) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (calc_hashes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 355.7008 cm +1 0 0 1 50.01575 258.1008 cm +Q +q +1 0 0 1 50.01575 240.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (name) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 234.1008 cm +Q +q +1 0 0 1 40.01575 216.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_SECTION) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Name) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 204.1008 cm q .933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +n 33.35 0 180 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET Q Q q -1 0 0 1 40.01575 349.7008 cm +1 0 0 1 50.01575 198.1008 cm Q q -1 0 0 1 40.01575 331.7008 cm +1 0 0 1 50.01575 180.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_mem_poll) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (duration) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (looptimes) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (name) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 319.7008 cm +1 0 0 1 40.01575 174.1008 cm +Q q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +1 0 0 1 40.01575 156.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvChecksum16) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 313.7008 cm +1 0 0 1 40.01575 150.1008 cm Q q -1 0 0 1 40.01575 295.7008 cm +1 0 0 1 40.01575 132.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_smbus_execute) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (address) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (command) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (operation) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (peccheck) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvChecksum8) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 283.7008 cm +1 0 0 1 40.01575 126.1008 cm +Q q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +1 0 0 1 40.01575 108.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvSum16) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 277.7008 cm +1 0 0 1 40.01575 102.1008 cm Q q -1 0 0 1 40.01575 259.7008 cm +1 0 0 1 40.01575 84.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_stall) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (duration) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvSum8) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 247.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 241.7008 cm -Q -q -1 0 0 1 40.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_terminate) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 211.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 205.7008 cm -Q -q -1 0 0 1 40.01575 187.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (op_unknown) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (opcode) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 175.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 169.7008 cm -Q -q -1 0 0 1 40.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_auth_var) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 145.7008 cm -Q -q -1 0 0 1 40.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_efivar_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (fname) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (var) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (var_type) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 121.7008 cm -Q -q -1 0 0 1 40.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_esal_var) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 97.70079 cm -Q -q -1 0 0 1 40.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_external) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 73.70079 cm +1 0 0 1 40.01575 78.10079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -33245,16 +33197,16 @@ Q endstream endobj -1278 0 obj +1275 0 obj << -/Length 8804 +/Length 10004 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 40.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_pkcs7) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (GetFvHeader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33263,7 +33215,7 @@ Q q 1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwFile) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (FvImage) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FvLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fof) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33272,7 +33224,7 @@ Q q 1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048_sha1) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwFileSection) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (sections) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (ssize) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (sof) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33281,7 +33233,7 @@ Q q 1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_rsa2048_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwVolume) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33290,7 +33242,7 @@ Q q 1 0 0 1 40.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sb_db) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (db) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (decode_dir) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ValidateFwVolumeHeader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (ZeroVector) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FsGuid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FvLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (ExtHeaderOffset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33299,7 +33251,7 @@ Q q 1 0 0 1 40.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha1) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (align_image) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (8) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fill) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33308,7 +33260,7 @@ Q q 1 0 0 1 40.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha224) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33317,7 +33269,7 @@ Q q 1 0 0 1 40.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_raw) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33326,7 +33278,7 @@ Q q 1 0 0 1 40.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha384) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_section) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (uncomressed_size) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (compression_type) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33335,47 +33287,11 @@ Q q 1 0 0 1 40.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_sha512) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_guid_bin) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 541.7008 cm -Q -q -1 0 0 1 40.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 517.7008 cm -Q -q -1 0 0 1 40.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha256) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 493.7008 cm -Q -q -1 0 0 1 40.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha384) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 469.7008 cm -Q -q -1 0 0 1 40.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_x509_sha512) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 402.1008 cm +1 0 0 1 40.01575 498.1008 cm q 1 1 1 RG .3 w @@ -33383,50 +33299,90 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_fv module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_platform module) Tj T* ET Q Q q -1 0 0 1 40.01575 390.1008 cm +1 0 0 1 40.01575 480.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Platform specific UEFI functionality \(parsing platform specific EFI NVRAM, capsules, etc.\)) Tj T* ET +Q Q q -1 0 0 1 40.01575 372.1008 cm +1 0 0 1 40.01575 474.1008 cm +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DecodeSection) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (SecType) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (SecBody) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (SecHeaderSize) Tj .839216 .701961 0 rg (\)) Tj T* ET +1 0 0 1 40.01575 456.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_NVAR1) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved3) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 444.1008 cm +q +.933333 1 .8 rg +n 33.35 0 234 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_NVAR1) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 438.1008 cm +Q +q +1 0 0 1 40.01575 420.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 408.1008 cm +q +.933333 1 .8 rg +n 33.35 0 222 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 402.1008 cm +Q +q +1 0 0 1 40.01575 384.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS_APPLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (unknown) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 372.1008 cm +q +.933333 1 .8 rg +n 33.35 0 258 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE) Tj T* ET Q Q q 1 0 0 1 40.01575 366.1008 cm Q q -1 0 0 1 40.01575 348.1008 cm +1 0 0 1 40.01575 336.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_FILE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Checksum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (UD) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CalcSum) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS_AUTH) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TimeStamp1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TimeStamp2) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (PubKeyIndex) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 336.1008 cm +1 0 0 1 50.01575 324.1008 cm q .933333 1 .8 rg -n 33.35 0 180 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET +n 33.35 0 252 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH) Tj T* ET Q Q q -1 0 0 1 40.01575 330.1008 cm +1 0 0 1 40.01575 318.1008 cm Q q -1 0 0 1 40.01575 312.1008 cm +1 0 0 1 40.01575 300.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_FV) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Checksum) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (ExtHeaderOffset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (CalcSum) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 300.1008 cm -q -.933333 1 .8 rg -n 33.35 0 180 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIvar_EVSA) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33435,7 +33391,7 @@ Q q 1 0 0 1 40.01575 276.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_MODULE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FWType) Tj T* ET Q Q q @@ -33452,7 +33408,7 @@ Q q 1 0 0 1 50.01575 240.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (calc_hashes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_EVSA) Tj /F4 10 Tf ( = 'evsa') Tj T* ET Q Q q @@ -33461,64 +33417,65 @@ Q q 1 0 0 1 50.01575 216.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (name) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_NVAR) Tj /F4 10 Tf ( = 'nvar') Tj T* ET Q Q q -1 0 0 1 40.01575 210.1008 cm +1 0 0 1 50.01575 210.1008 cm Q q -1 0 0 1 40.01575 192.1008 cm +1 0 0 1 50.01575 192.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_SECTION) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Offset) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Name) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Type) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Image) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_UEFI) Tj /F4 10 Tf ( = 'uefi') Tj T* ET Q Q q -1 0 0 1 50.01575 180.1008 cm +1 0 0 1 50.01575 186.1008 cm +Q q -.933333 1 .8 rg -n 33.35 0 180 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_fv.EFI_MODULE) Tj T* ET +1 0 0 1 50.01575 168.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_UEFI_AUTH) Tj /F4 10 Tf ( = 'uefi_auth') Tj T* ET Q Q q -1 0 0 1 50.01575 174.1008 cm +1 0 0 1 50.01575 162.1008 cm Q q -1 0 0 1 50.01575 156.1008 cm +1 0 0 1 50.01575 144.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (name) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS) Tj /F4 10 Tf ( = 'vss') Tj T* ET Q Q q -1 0 0 1 40.01575 150.1008 cm +1 0 0 1 50.01575 138.1008 cm Q q -1 0 0 1 40.01575 132.1008 cm +1 0 0 1 50.01575 120.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvChecksum16) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS2) Tj /F4 10 Tf ( = 'vss2') Tj T* ET Q Q q -1 0 0 1 40.01575 126.1008 cm +1 0 0 1 50.01575 114.1008 cm Q q -1 0 0 1 40.01575 108.1008 cm +1 0 0 1 50.01575 96.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvChecksum8) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS2_AUTH) Tj /F4 10 Tf ( = 'vss2_auth') Tj T* ET Q Q q -1 0 0 1 40.01575 102.1008 cm +1 0 0 1 50.01575 90.10079 cm Q q -1 0 0 1 40.01575 84.10079 cm +1 0 0 1 50.01575 72.10079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvSum16) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS_APPLE) Tj /F4 10 Tf ( = 'vss_apple') Tj T* ET Q Q q -1 0 0 1 40.01575 78.10079 cm +1 0 0 1 50.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -33536,16 +33493,16 @@ Q endstream endobj -1279 0 obj +1276 0 obj << -/Length 10067 +/Length 8871 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 763.7008 cm +1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FvSum8) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS_AUTH) Tj /F4 10 Tf ( = 'vss_auth') Tj T* ET Q Q q @@ -33554,7 +33511,7 @@ Q q 1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (GetFvHeader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_VARIABLE_STATE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_c) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_Mask) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33563,7 +33520,7 @@ Q q 1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwFile) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (FvImage) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FvLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fof) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ParsePFS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -33572,43 +33529,50 @@ Q q 1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwFileSection) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (sections) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (ssize) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (sof) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (polarity) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PfsFile) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (data) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (concat) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 685.7008 cm -Q +1 0 0 1 50.01575 679.7008 cm q -1 0 0 1 40.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (NextFwVolume) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (off) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 40.01575 661.7008 cm +1 0 0 1 50.01575 673.7008 cm Q q -1 0 0 1 40.01575 643.7008 cm +1 0 0 1 50.01575 655.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ValidateFwVolumeHeader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (ZeroVector) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FsGuid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (FvLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (HeaderLength) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (ExtHeaderOffset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 637.7008 cm +1 0 0 1 40.01575 649.7008 cm Q q -1 0 0 1 40.01575 619.7008 cm +1 0 0 1 40.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (align_image) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (8) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fill) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PfsFileSection) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (data) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 613.7008 cm +1 0 0 1 50.01575 619.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q Q q -1 0 0 1 40.01575 595.7008 cm +1 0 0 1 50.01575 613.7008 cm +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_file) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (\)) Tj T* ET +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -33617,133 +33581,11 @@ Q q 1 0 0 1 40.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_raw) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptType) Tj T* ET Q Q q -1 0 0 1 40.01575 565.7008 cm -Q -q -1 0 0 1 40.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (assemble_uefi_section) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (image) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (uncomressed_size) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (compression_type) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 541.7008 cm -Q -q -1 0 0 1 40.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_guid_bin) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (guid) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 474.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_platform module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 456.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Platform specific UEFI functionality \(parsing platform specific EFI NVRAM, capsules, etc.\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 450.1008 cm -Q -q -1 0 0 1 40.01575 432.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_NVAR1) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TotalSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved3) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 420.1008 cm -q -.933333 1 .8 rg -n 33.35 0 234 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_NVAR1) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 414.1008 cm -Q -q -1 0 0 1 40.01575 396.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 384.1008 cm -q -.933333 1 .8 rg -n 33.35 0 222 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 378.1008 cm -Q -q -1 0 0 1 40.01575 360.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS_APPLE) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (unknown) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 348.1008 cm -q -.933333 1 .8 rg -n 33.35 0 258 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS_APPLE) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 342.1008 cm -Q -q -1 0 0 1 40.01575 312.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EFI_HDR_VSS_AUTH) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (MonotonicCount) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TimeStamp1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (TimeStamp2) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (PubKeyIndex) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (guid) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 300.1008 cm -q -.933333 1 .8 rg -n 33.35 0 252 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.EFI_HDR_VSS_AUTH) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 294.1008 cm -Q -q -1 0 0 1 40.01575 276.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIvar_EVSA) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 270.1008 cm -Q -q -1 0 0 1 40.01575 252.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FWType) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 240.1008 cm +1 0 0 1 50.01575 559.7008 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -33751,70 +33593,187 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 50.01575 234.1008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 50.01575 216.1008 cm +1 0 0 1 50.01575 535.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_EVSA) Tj /F4 10 Tf ( = 'evsa') Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TYPE_DEFAULT) Tj /F4 10 Tf ( = 0) Tj T* ET Q Q q -1 0 0 1 50.01575 210.1008 cm +1 0 0 1 50.01575 529.7008 cm Q q -1 0 0 1 50.01575 192.1008 cm +1 0 0 1 50.01575 511.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_NVAR) Tj /F4 10 Tf ( = 'nvar') Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TYPE_EDKCOMPAT) Tj /F4 10 Tf ( = 170) Tj T* ET Q Q q -1 0 0 1 50.01575 186.1008 cm +1 0 0 1 40.01575 505.7008 cm Q q -1 0 0 1 50.01575 168.1008 cm +1 0 0 1 40.01575 475.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_UEFI) Tj /F4 10 Tf ( = 'uefi') Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UEFI_VARIABLE_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid0) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (VendorGuid1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid3) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 162.1008 cm -Q +1 0 0 1 50.01575 463.7008 cm q -1 0 0 1 50.01575 144.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_UEFI_AUTH) Tj /F4 10 Tf ( = 'uefi_auth') Tj T* ET +.933333 1 .8 rg +n 33.35 0 276 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.UEFI_VARIABLE_HEADER) Tj T* ET Q Q q -1 0 0 1 50.01575 138.1008 cm +1 0 0 1 40.01575 457.7008 cm Q q -1 0 0 1 50.01575 120.1008 cm +1 0 0 1 40.01575 439.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS) Tj /F4 10 Tf ( = 'vss') Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UEFI_VARIABLE_STORE_HEADER_SIZE) Tj /F4 10 Tf ( = 28) Tj T* ET Q Q q -1 0 0 1 50.01575 114.1008 cm -Q +1 0 0 1 50.01575 415.7008 cm q -1 0 0 1 50.01575 96.10079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS2) Tj /F4 10 Tf ( = 'vss2') Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_VARIABLE_HEADER_AUTH = \223) Tj (<) Tj (HBBI28sIIIHH8s\224 EFI_VARIABLE_HEADER_AUTH_SIZE =) Tj T* (struct.calcsize\(EFI_VARIABLE_HEADER_AUTH\)) Tj T* ET Q Q q -1 0 0 1 50.01575 90.10079 cm -Q +1 0 0 1 50.01575 391.7008 cm q -1 0 0 1 50.01575 72.10079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS2_AUTH) Tj /F4 10 Tf ( = 'vss2_auth') Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_VARIABLE_HEADER = \223) Tj (<) Tj (HBBIIIIHH8s\224 EFI_VARIABLE_HEADER_SIZE =) Tj T* (struct.calcsize\(EFI_VARIABLE_HEADER\)) Tj T* ET Q Q q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 40.01575 385.7008 cm +Q +q +1 0 0 1 40.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VARIABLE_STORE_HEADER_VSS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Format) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 355.7008 cm +q +.933333 1 .8 rg +n 33.35 0 306 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 349.7008 cm +Q +q +1 0 0 1 40.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VARIABLE_STORE_HEADER_VSS2) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Format) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 319.7008 cm +q +.933333 1 .8 rg +n 33.35 0 312 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS2) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 313.7008 cm +Q +q +1 0 0 1 40.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create_s3bootscript_entry_buffer) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 289.7008 cm +Q +q +1 0 0 1 40.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s3bootscript_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (script_data) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 265.7008 cm +Q +q +1 0 0 1 40.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode_def) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 241.7008 cm +Q +q +1 0 0 1 40.01575 223.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode_edkcompat) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 217.7008 cm +Q +q +1 0 0 1 40.01575 199.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bootscript_entry) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (entry) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 193.7008 cm +Q +q +1 0 0 1 40.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s3bootscript_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 169.7008 cm +Q +q +1 0 0 1 40.01575 151.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode_def) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 145.7008 cm +Q +q +1 0 0 1 40.01575 127.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode_edkcompat) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 121.7008 cm +Q +q +1 0 0 1 40.01575 103.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_NVAR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 97.70079 cm +Q +q +1 0 0 1 40.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_NVAR_simple) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -33832,314 +33791,16 @@ Q endstream endobj -1280 0 obj +1277 0 obj << -/Length 8784 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS_APPLE) Tj /F4 10 Tf ( = 'vss_apple') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_FW_TYPE_VSS_AUTH) Tj /F4 10 Tf ( = 'vss_auth') Tj T* ET -Q -Q -q -1 0 0 1 40.01575 733.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IS_VARIABLE_STATE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_c) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_Mask) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 709.7008 cm -Q -q -1 0 0 1 40.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ParsePFS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 685.7008 cm -Q -q -1 0 0 1 40.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PfsFile) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (data) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (concat) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 655.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 625.7008 cm -Q -q -1 0 0 1 40.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PfsFileSection) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (data) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 595.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 565.7008 cm -Q -q -1 0 0 1 40.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (S3BootScriptType) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 535.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TYPE_DEFAULT) Tj /F4 10 Tf ( = 0) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_BOOT_SCRIPT_TYPE_EDKCOMPAT) Tj /F4 10 Tf ( = 170) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 481.7008 cm -Q -q -1 0 0 1 40.01575 451.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (UEFI_VARIABLE_HEADER) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (StartId) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Attributes) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (NameSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (DataSize) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid0) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (VendorGuid1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid2) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (VendorGuid3) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 439.7008 cm -q -.933333 1 .8 rg -n 33.35 0 276 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.UEFI_VARIABLE_HEADER) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 433.7008 cm -Q -q -1 0 0 1 40.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (UEFI_VARIABLE_STORE_HEADER_SIZE) Tj /F4 10 Tf ( = 28) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_VARIABLE_HEADER_AUTH = \223) Tj (<) Tj (HBBI28sIIIHH8s\224 EFI_VARIABLE_HEADER_AUTH_SIZE =) Tj T* (struct.calcsize\(EFI_VARIABLE_HEADER_AUTH\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (EFI_VARIABLE_HEADER = \223) Tj (<) Tj (HBBIIIIHH8s\224 EFI_VARIABLE_HEADER_SIZE =) Tj T* (struct.calcsize\(EFI_VARIABLE_HEADER\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 361.7008 cm -Q -q -1 0 0 1 40.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VARIABLE_STORE_HEADER_VSS) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Format) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 331.7008 cm -q -.933333 1 .8 rg -n 33.35 0 306 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 325.7008 cm -Q -q -1 0 0 1 40.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VARIABLE_STORE_HEADER_VSS2) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (Signature) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Size) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Format) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (State) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (Reserved1) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 295.7008 cm -q -.933333 1 .8 rg -n 33.35 0 312 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.uefi_platform.VARIABLE_STORE_HEADER_VSS2) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 289.7008 cm -Q -q -1 0 0 1 40.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create_s3bootscript_entry_buffer) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (index) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 265.7008 cm -Q -q -1 0 0 1 40.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s3bootscript_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (script_data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 241.7008 cm -Q -q -1 0 0 1 40.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode_def) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 217.7008 cm -Q -q -1 0 0 1 40.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decode_s3bs_opcode_edkcompat) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 193.7008 cm -Q -q -1 0 0 1 40.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bootscript_entry) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (entry) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 169.7008 cm -Q -q -1 0 0 1 40.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s3bootscript_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 145.7008 cm -Q -q -1 0 0 1 40.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode_def) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 121.7008 cm -Q -q -1 0 0 1 40.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (encode_s3bs_opcode_edkcompat) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (op) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 97.70079 cm -Q -q -1 0 0 1 40.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_NVAR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (76) Tj T* ET -Q -Q - -endstream -endobj -1281 0 obj -<< -/Length 7863 +/Length 7995 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 40.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_NVAR_simple) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_UEFI) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34148,7 +33809,7 @@ Q q 1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_UEFI) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_UEFI_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34157,7 +33818,7 @@ Q q 1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_UEFI_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34166,7 +33827,7 @@ Q q 1 0 0 1 40.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS2) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34175,7 +33836,7 @@ Q q 1 0 0 1 40.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS2) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS2_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34184,7 +33845,7 @@ Q q 1 0 0 1 40.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS2_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS_APPLE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34193,7 +33854,7 @@ Q q 1 0 0 1 40.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS_APPLE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34202,7 +33863,7 @@ Q q 1 0 0 1 40.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getEFIvariables_VSS_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EFI) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34211,7 +33872,7 @@ Q q 1 0 0 1 40.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EFI) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EFI_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34220,7 +33881,7 @@ Q q 1 0 0 1 40.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EFI_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EVSA) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34229,7 +33890,7 @@ Q q 1 0 0 1 40.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_EVSA) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_NVAR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34238,7 +33899,7 @@ Q q 1 0 0 1 40.01575 499.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_NVAR) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_NVAR_simple) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34247,7 +33908,7 @@ Q q 1 0 0 1 40.01575 475.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_NVAR_simple) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34256,7 +33917,7 @@ Q q 1 0 0 1 40.01575 451.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS2) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34265,7 +33926,7 @@ Q q 1 0 0 1 40.01575 427.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS2) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS2_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34274,7 +33935,7 @@ Q q 1 0 0 1 40.01575 403.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS2_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS_APPLE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34283,7 +33944,7 @@ Q q 1 0 0 1 40.01575 379.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS_APPLE) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34292,7 +33953,7 @@ Q q 1 0 0 1 40.01575 355.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getNVstore_VSS_AUTH) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (id_s3bootscript_type) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34301,7 +33962,7 @@ Q q 1 0 0 1 40.01575 331.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (id_s3bootscript_type) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (script) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isCorrectVSStype) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (vss_type) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -34310,20 +33971,11 @@ Q q 1 0 0 1 40.01575 307.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isCorrectVSStype) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (nvram_buf) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (vss_type) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 301.7008 cm -Q -q -1 0 0 1 40.01575 283.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (parse_s3bootscript_entry) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s3bootscript_type) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (script) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (off) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (log_script) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 234.1008 cm +1 0 0 1 40.01575 258.1008 cm q 1 1 1 RG .3 w @@ -34335,20 +33987,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi_search module) Tj T* ET Q Q q -1 0 0 1 40.01575 216.1008 cm +1 0 0 1 40.01575 240.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (UEFI image search auxilliary functionality) Tj T* ET Q Q q -1 0 0 1 40.01575 200.1008 cm +1 0 0 1 40.01575 224.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 180.7008 cm +1 0 0 1 40.01575 204.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -34378,24 +34030,344 @@ Q Q Q q -1 0 0 1 40.01575 174.7008 cm +1 0 0 1 40.01575 198.7008 cm Q q -1 0 0 1 40.01575 156.7008 cm +1 0 0 1 40.01575 180.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_match_criteria) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (efi) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (criteria) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_log) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 150.7008 cm +1 0 0 1 40.01575 174.7008 cm Q q -1 0 0 1 40.01575 132.7008 cm +1 0 0 1 40.01575 156.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_rules) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (efi) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rules) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (entry_name) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_log) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (bLog) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 40.01575 107.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (virtmem module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 89.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to virtual memory) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 73.10079 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (76) Tj T* ET +Q +Q + +endstream +endobj +1278 0 obj +<< +/Length 10144 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 727.5008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 35.2 Tm T* ET +q +1 0 0 1 20 0 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 488.4441 44.4 re B* +Q +q +BT 1 0 0 1 0 30.4 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_virtual_mem\( 0xf0000, 0x100 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_virtual_mem\( 0xf0000, 0x100, buffer \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_virtual_mem_dowrd\( 0xf0000, 0xdeadbeef \)) Tj T* (>) Tj (>) Tj (>) Tj ( read_virtual_mem_dowrd\( 0xfed40000 \)) Tj T* ET +Q +Q +Q +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 721.5008 cm +Q +q +1 0 0 1 40.01575 703.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VirtMemory) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 691.5008 cm +q +.933333 1 .8 rg +n 33.35 0 168 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.5008 cm +Q +q +1 0 0 1 50.01575 667.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (18446744073709551615) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.5008 cm +Q +q +1 0 0 1 50.01575 643.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.5008 cm +Q +q +1 0 0 1 50.01575 619.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.5008 cm +Q +q +1 0 0 1 50.01575 595.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.5008 cm +Q +q +1 0 0 1 50.01575 571.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.5008 cm +Q +q +1 0 0 1 50.01575 547.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.5008 cm +Q +q +1 0 0 1 50.01575 523.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.5008 cm +Q +q +1 0 0 1 50.01575 499.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.5008 cm +Q +q +1 0 0 1 50.01575 475.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 469.5008 cm +Q +q +1 0 0 1 50.01575 451.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.5008 cm +Q +q +1 0 0 1 50.01575 427.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 377.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmm module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 347.9008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (VMM specific functionality 1. Hypervisor hypercall interfaces 2. Second-level Address Translation \(SLAT\) 3. VirtIO) Tj T* (devices 4. \205) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 341.9008 cm +Q +q +1 0 0 1 40.01575 323.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMM) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 311.9008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 305.9008 cm +Q +q +1 0 0 1 50.01575 287.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EPT_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eptp) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_fname) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 281.9008 cm +Q +q +1 0 0 1 50.01575 263.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 257.9008 cm +Q +q +1 0 0 1 50.01575 239.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_extended_fast) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (parameter_block) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 233.9008 cm +Q +q +1 0 0 1 50.01575 215.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_fast) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (param0) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (param1) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 209.9008 cm +Q +q +1 0 0 1 50.01575 191.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_five_args) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg1) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg2) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg3) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg4) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg5) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 185.9008 cm +Q +q +1 0 0 1 50.01575 167.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_memory_based) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (parameters) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 161.9008 cm +Q +q +1 0 0 1 50.01575 143.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 137.9008 cm +Q +q +1 0 0 1 40.01575 119.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VirtIO_Device) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (b) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (d) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (f) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 107.9008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 101.9008 cm +Q +q +1 0 0 1 50.01575 83.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_device) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 77.90079 cm +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -34411,391 +34383,20 @@ Q endstream endobj -1282 0 obj +1279 0 obj << -/Length 9880 +/Length 4260 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 766.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (virtmem module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 748.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Access to virtual memory) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 732.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 683.9008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 35.2 Tm T* ET -q -1 0 0 1 20 0 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 494.4441 44.4 re B* -Q -q -BT 1 0 0 1 0 30.4 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( read_virtual_mem\( 0xf0000, 0x100 \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_virtual_mem\( 0xf0000, 0x100, buffer \)) Tj T* (>) Tj (>) Tj (>) Tj ( write_virtual_mem_dowrd\( 0xf0000, 0xdeadbeef \)) Tj T* (>) Tj (>) Tj (>) Tj ( read_virtual_mem_dowrd\( 0xfed40000 \)) Tj T* ET -Q -Q -Q -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 677.9008 cm -Q -q -1 0 0 1 40.01575 659.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MemoryAccessError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 647.9008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 641.9008 cm -Q -q -1 0 0 1 40.01575 623.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (MemoryRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 611.9008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 605.9008 cm -Q -q -1 0 0 1 40.01575 587.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VirtMemory) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 575.9008 cm -q -.933333 1 .8 rg -n 33.35 0 168 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.hal_base.HALBase) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 569.9008 cm -Q -q -1 0 0 1 50.01575 551.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (18446744073709551615) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 545.9008 cm -Q -q -1 0 0 1 50.01575 527.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 521.9008 cm -Q -q -1 0 0 1 50.01575 503.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 497.9008 cm -Q -q -1 0 0 1 50.01575 479.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 473.9008 cm -Q -q -1 0 0 1 50.01575 455.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 449.9008 cm -Q -q -1 0 0 1 50.01575 431.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_virtual_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 425.9008 cm -Q -q -1 0 0 1 50.01575 407.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 401.9008 cm -Q -q -1 0 0 1 50.01575 383.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 377.9008 cm -Q -q -1 0 0 1 50.01575 359.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_byte) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (byte_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 353.9008 cm -Q -q -1 0 0 1 50.01575 335.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 329.9008 cm -Q -q -1 0 0 1 50.01575 311.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_virtual_mem_word) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (virt_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (word_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 262.3008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmm module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 232.3008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (VMM specific functionality 1. Hypervisor hypercall interfaces 2. Second-level Address Translation \(SLAT\) 3. VirtIO) Tj T* (devices 4. \205) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 226.3008 cm -Q -q -1 0 0 1 40.01575 208.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMM) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 196.3008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 190.3008 cm -Q -q -1 0 0 1 50.01575 172.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_EPT_page_tables) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eptp) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_fname) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 166.3008 cm -Q -q -1 0 0 1 50.01575 148.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 142.3008 cm -Q -q -1 0 0 1 50.01575 124.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_extended_fast) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (parameter_block) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 118.3008 cm -Q -q -1 0 0 1 50.01575 100.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_fast) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (param0) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (param1) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 94.30079 cm -Q -q -1 0 0 1 50.01575 76.30079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_five_args) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg1) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg2) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg3) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg4) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (arg5) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 70.30079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (78) Tj T* ET -Q -Q - -endstream -endobj -1283 0 obj -<< -/Length 5273 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall64_memory_based) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (hypervisor_input_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (parameters) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 733.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (VMMRuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 697.7008 cm -Q -q -1 0 0 1 40.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VirtIO_Device) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (b) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (d) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (f) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 667.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_device) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 637.7008 cm -Q -q -1 0 0 1 40.01575 619.7008 cm +1 0 0 1 40.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_virtio_devices) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (devices) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 567.7008 cm +1 0 0 1 40.01575 711.7008 cm q 1 1 1 RG .3 w @@ -34807,14 +34408,14 @@ BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 1 1 1 rg (OS Helpers & Drivers) Tj T* ET Q Q q -1 0 0 1 40.01575 549.7008 cm +1 0 0 1 40.01575 693.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Provides a translation layer to convert a common interface to OS specific driver calls) Tj T* ET Q Q q -1 0 0 1 40.01575 500.1008 cm +1 0 0 1 40.01575 644.1008 cm q 1 1 1 RG .3 w @@ -34826,14 +34427,14 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (OS Helpers and Drivers) Tj T* ET Q Q q -1 0 0 1 40.01575 482.1008 cm +1 0 0 1 40.01575 626.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Provide common interfaces to interact with system drivers/commands) Tj T* ET Q Q q -1 0 0 1 40.01575 432.5008 cm +1 0 0 1 40.01575 576.5008 cm q 1 1 1 RG .3 w @@ -34845,14 +34446,14 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (Mostly invoked by HAL modules) Tj Q Q q -1 0 0 1 40.01575 414.5008 cm +1 0 0 1 40.01575 558.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Directly invoking helpers from modules should be minimized) Tj T* ET Q Q q -1 0 0 1 40.01575 364.9008 cm +1 0 0 1 40.01575 508.9008 cm q 1 1 1 RG .3 w @@ -34864,21 +34465,21 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (Helpers import from BaseHelper) Tj Q Q q -1 0 0 1 40.01575 346.9008 cm +1 0 0 1 40.01575 490.9008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Override applicable functions \226 default is to generate exception) Tj T* ET Q Q q -1 0 0 1 40.01575 328.9008 cm +1 0 0 1 40.01575 472.9008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (I/O, PCI, MSR, UEFI Variables, etc.) Tj T* ET Q Q q -1 0 0 1 40.01575 279.3008 cm +1 0 0 1 40.01575 423.3008 cm q 1 1 1 RG .3 w @@ -34890,14 +34491,14 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (Create a New Helper) Tj T* ET Q Q q -1 0 0 1 40.01575 261.3008 cm +1 0 0 1 40.01575 405.3008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Helper needs to be added to the import list either within helpers.py or custom_helpers.py) Tj T* ET Q Q q -1 0 0 1 40.01575 211.7008 cm +1 0 0 1 40.01575 355.7008 cm q 1 1 1 RG .3 w @@ -34909,25 +34510,25 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (Example) Tj T* ET Q Q q -1 0 0 1 40.01575 181.7008 cm +1 0 0 1 40.01575 325.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The new helper should be added to either ) Tj /F3 10 Tf (chipsec/helper/helpers.py) Tj /F1 10 Tf ( or) Tj T* /F3 10 Tf (chipsec/helper/custom_helpers.py) Tj T* ET Q Q q -1 0 0 1 40.01575 163.7008 cm +1 0 0 1 40.01575 307.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (A new helper folder should be created under ) Tj /F3 10 Tf (chipsec/helper/new_helper) Tj T* ET Q Q q -1 0 0 1 40.01575 145.7008 cm +1 0 0 1 40.01575 289.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec/helper/new_helper/__init__.py) Tj /F1 10 Tf ( within the new folder needs to add the helper to avail_helpers list) Tj T* ET Q Q q -1 0 0 1 40.01575 81.30079 cm +1 0 0 1 40.01575 206.1008 cm q q 1 0 0 1 0 0 cm @@ -34937,67 +34538,24 @@ q .666667 .8 .6 RG .3 w .933333 1 .8 rg -n -4 0 514.4441 63.6 re B* +n -4 0 514.4441 82.8 re B* Q q 0 0 0 rg -BT 1 0 0 1 0 49.6 Tm /F3 8 Tf 9.6 TL (import platform) Tj T* (from chipsec.helper.oshelper import avail_helpers) Tj T* T* (if "linux" == platform.system\(\).lower\(\):) Tj T* ( __all__ = [ "linuxhelper" ]) Tj T* ( avail_helpers.append\("linuxhelper"\)) Tj T* ET +BT 1 0 0 1 0 68.8 Tm /F3 8 Tf 9.6 TL (import platform) Tj T* (from chipsec.helper.oshelper import avail_helpers) Tj T* T* (if "linux" == platform.system\(\).lower\(\):) Tj T* ( __all__ = [ "linuxhelper" ]) Tj T* ( avail_helpers.append\("linuxhelper"\)) Tj T* (else:) Tj T* ( __all__ = [ ]) Tj T* ET Q Q Q Q Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (79) Tj T* ET -Q -Q - -endstream -endobj -1284 0 obj -<< -/Length 5765 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 749.7008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 25.2 re B* -Q -q -0 0 0 rg -BT 1 0 0 1 0 11.2 Tm /F3 8 Tf 9.6 TL (else:) Tj T* ( __all__ = [ ]) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 729.7008 cm +1 0 0 1 40.01575 186.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec/helper/new_helper/new_helper.py) Tj /F1 10 Tf ( should import from Helper Base Class) Tj T* ET Q Q q -1 0 0 1 40.01575 665.3008 cm +1 0 0 1 40.01575 121.7008 cm q q 1 0 0 1 0 0 cm @@ -35018,7 +34576,29 @@ Q Q Q q -1 0 0 1 40.01575 615.7008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (78) Tj T* ET +Q +Q + +endstream +endobj +1280 0 obj +<< +/Length 7358 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -35030,7 +34610,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (helper package) Tj T* ET Q Q q -1 0 0 1 40.01575 566.1008 cm +1 0 0 1 40.01575 716.5008 cm q 1 1 1 RG .3 w @@ -35042,7 +34622,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (dal package) Tj T* ET Q Q q -1 0 0 1 40.01575 516.5008 cm +1 0 0 1 40.01575 666.9008 cm q 1 1 1 RG .3 w @@ -35054,29 +34634,29 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (dalhelper module) Tj T* ET Q Q q -1 0 0 1 40.01575 498.5008 cm +1 0 0 1 40.01575 648.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Intel DFx Abstraction Layer \(DAL\) helper) Tj T* ET Q Q q -1 0 0 1 40.01575 480.5008 cm +1 0 0 1 40.01575 630.9008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (From the Intel\(R\) DFx Abstraction Layer Python* Command Line Interface User Guide) Tj T* ET Q Q q -1 0 0 1 40.01575 474.5008 cm +1 0 0 1 40.01575 624.9008 cm Q q -1 0 0 1 40.01575 456.5008 cm +1 0 0 1 40.01575 606.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (DALHelper) Tj T* ET Q Q q -1 0 0 1 50.01575 444.5008 cm +1 0 0 1 50.01575 594.9008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -35084,142 +34664,461 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helpe Q Q q -1 0 0 1 50.01575 438.5008 cm +1 0 0 1 50.01575 588.9008 cm Q q -1 0 0 1 50.01575 420.5008 cm +1 0 0 1 50.01575 570.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 414.5008 cm +1 0 0 1 50.01575 564.9008 cm Q q -1 0 0 1 50.01575 396.5008 cm +1 0 0 1 50.01575 546.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 390.5008 cm +1 0 0 1 50.01575 540.9008 cm Q q -1 0 0 1 50.01575 372.5008 cm +1 0 0 1 50.01575 522.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 366.5008 cm +1 0 0 1 50.01575 516.9008 cm Q q -1 0 0 1 50.01575 348.5008 cm +1 0 0 1 50.01575 498.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dal_version) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 342.5008 cm +1 0 0 1 50.01575 492.9008 cm Q q -1 0 0 1 50.01575 324.5008 cm +1 0 0 1 50.01575 474.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 318.5008 cm +1 0 0 1 50.01575 468.9008 cm Q q -1 0 0 1 50.01575 300.5008 cm +1 0 0 1 50.01575 450.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 294.5008 cm +1 0 0 1 50.01575 444.9008 cm Q q -1 0 0 1 50.01575 276.5008 cm +1 0 0 1 50.01575 426.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_thread) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 270.5008 cm +1 0 0 1 50.01575 420.9008 cm Q q -1 0 0 1 50.01575 252.5008 cm +1 0 0 1 50.01575 402.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 246.5008 cm +1 0 0 1 50.01575 396.9008 cm Q q -1 0 0 1 50.01575 228.5008 cm +1 0 0 1 50.01575 378.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 222.5008 cm +1 0 0 1 50.01575 372.9008 cm Q q -1 0 0 1 50.01575 204.5008 cm +1 0 0 1 50.01575 354.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 198.5008 cm +1 0 0 1 50.01575 348.9008 cm Q q -1 0 0 1 50.01575 180.5008 cm +1 0 0 1 50.01575 330.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 174.5008 cm +1 0 0 1 50.01575 324.9008 cm Q q -1 0 0 1 50.01575 156.5008 cm +1 0 0 1 50.01575 306.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 150.5008 cm +1 0 0 1 50.01575 300.9008 cm Q q -1 0 0 1 50.01575 132.5008 cm +1 0 0 1 50.01575 282.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 126.5008 cm +1 0 0 1 50.01575 276.9008 cm Q q -1 0 0 1 50.01575 108.5008 cm +1 0 0 1 50.01575 258.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 102.5008 cm +1 0 0 1 50.01575 252.9008 cm Q q -1 0 0 1 50.01575 84.50079 cm +1 0 0 1 50.01575 234.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 78.50079 cm +1 0 0 1 50.01575 228.9008 cm +Q +q +1 0 0 1 50.01575 210.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (core_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 204.9008 cm +Q +q +1 0 0 1 50.01575 186.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 180.9008 cm +Q +q +1 0 0 1 50.01575 162.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 156.9008 cm +Q +q +1 0 0 1 50.01575 138.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 132.9008 cm +Q +q +1 0 0 1 50.01575 114.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 108.9008 cm +Q +q +1 0 0 1 50.01575 90.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 84.90079 cm +Q +q +1 0 0 1 50.01575 66.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (79) Tj T* ET +Q +Q + +endstream +endobj +1281 0 obj +<< +/Length 10636 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pci_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 553.7008 cm +Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 529.7008 cm +Q +q +1 0 0 1 50.01575 511.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bytewise) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 457.7008 cm +Q +q +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 433.7008 cm +Q +q +1 0 0 1 50.01575 415.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exhists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 409.7008 cm +Q +q +1 0 0 1 50.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.7008 cm +Q +q +1 0 0 1 50.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (target_machine) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 361.7008 cm +Q +q +1 0 0 1 50.01575 343.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.7008 cm +Q +q +1 0 0 1 50.01575 319.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.7008 cm +Q +q +1 0 0 1 50.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.7008 cm +Q +q +1 0 0 1 50.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 205.7008 cm +Q +q +1 0 0 1 50.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bytewise) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 181.7008 cm +Q +q +1 0 0 1 40.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -35237,16 +35136,591 @@ Q endstream endobj -1285 0 obj +1282 0 obj << -/Length 11915 +/Length 7838 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (efi package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 716.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (efihelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 698.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (On UEFI use the efi package functions) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 692.5008 cm +Q +q +1 0 0 1 40.01575 674.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EfiHelper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 662.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 656.5008 cm +Q +q +1 0 0 1 50.01575 638.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 632.5008 cm +Q +q +1 0 0 1 50.01575 614.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 608.5008 cm +Q +q +1 0 0 1 50.01575 590.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 584.5008 cm +Q +q +1 0 0 1 50.01575 566.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 560.5008 cm +Q +q +1 0 0 1 50.01575 542.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 536.5008 cm +Q +q +1 0 0 1 50.01575 518.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 512.5008 cm +Q +q +1 0 0 1 50.01575 494.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 488.5008 cm +Q +q +1 0 0 1 50.01575 470.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 464.5008 cm +Q +q +1 0 0 1 50.01575 446.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable_full) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 440.5008 cm +Q +q +1 0 0 1 50.01575 422.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 416.5008 cm +Q +q +1 0 0 1 50.01575 398.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 392.5008 cm +Q +q +1 0 0 1 50.01575 374.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 368.5008 cm +Q +q +1 0 0 1 50.01575 350.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 344.5008 cm +Q +q +1 0 0 1 50.01575 326.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 320.5008 cm +Q +q +1 0 0 1 50.01575 302.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 296.5008 cm +Q +q +1 0 0 1 50.01575 278.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 272.5008 cm +Q +q +1 0 0 1 50.01575 254.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 248.5008 cm +Q +q +1 0 0 1 50.01575 230.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 224.5008 cm +Q +q +1 0 0 1 50.01575 206.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 200.5008 cm +Q +q +1 0 0 1 50.01575 182.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pa2va) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 176.5008 cm +Q +q +1 0 0 1 50.01575 158.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 152.5008 cm +Q +q +1 0 0 1 50.01575 134.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 128.5008 cm +Q +q +1 0 0 1 50.01575 110.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 104.5008 cm +Q +q +1 0 0 1 50.01575 86.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 80.50079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (81) Tj T* ET +Q +Q + +endstream +endobj +1283 0 obj +<< +/Length 9539 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (core_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 751.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 745.7008 cm +Q +q +1 0 0 1 50.01575 727.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 721.7008 cm +Q +q +1 0 0 1 50.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 697.7008 cm +Q +q +1 0 0 1 50.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (7) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 673.7008 cm +Q +q +1 0 0 1 50.01575 655.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 649.7008 cm +Q +q +1 0 0 1 50.01575 631.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 625.7008 cm +Q +q +1 0 0 1 50.01575 607.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 601.7008 cm +Q +q +1 0 0 1 50.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 577.7008 cm +Q +q +1 0 0 1 50.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 553.7008 cm +Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 529.7008 cm +Q +q +1 0 0 1 50.01575 511.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 421.7008 cm +Q +q +1 0 0 1 40.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 354.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (file package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 304.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (filehelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 286.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Use results from a json file) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 280.5008 cm +Q +q +1 0 0 1 40.01575 262.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FileCmds) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (filename) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 250.5008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 244.5008 cm +Q +q +1 0 0 1 50.01575 226.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (AddElement) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cmd) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ret) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 220.5008 cm +Q +q +1 0 0 1 50.01575 202.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (Load) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 196.5008 cm +Q +q +1 0 0 1 50.01575 178.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (Save) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 172.5008 cm +Q +q +1 0 0 1 50.01575 154.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getElement) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cmd) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 148.5008 cm +Q +q +1 0 0 1 40.01575 130.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FileHelper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 118.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 112.5008 cm +Q +q +1 0 0 1 50.01575 94.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 88.50079 cm +Q +q +1 0 0 1 50.01575 70.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (82) Tj T* ET +Q +Q + +endstream +endobj +1284 0 obj +<< +/Length 11281 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35255,7 +35729,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35264,7 +35738,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35273,7 +35747,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35282,7 +35756,7 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35291,7 +35765,7 @@ Q q 1 0 0 1 50.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35300,7 +35774,7 @@ Q q 1 0 0 1 50.01575 619.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35309,7 +35783,7 @@ Q q 1 0 0 1 50.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -35318,7 +35792,7 @@ Q q 1 0 0 1 50.01575 571.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35327,7 +35801,7 @@ Q q 1 0 0 1 50.01575 547.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35336,7 +35810,2014 @@ Q q 1 0 0 1 50.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pci_addr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.7008 cm +Q +q +1 0 0 1 50.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 469.7008 cm +Q +q +1 0 0 1 50.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 421.7008 cm +Q +q +1 0 0 1 50.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 397.7008 cm +Q +q +1 0 0 1 50.01575 379.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 373.7008 cm +Q +q +1 0 0 1 50.01575 355.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 349.7008 cm +Q +q +1 0 0 1 50.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 325.7008 cm +Q +q +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 301.7008 cm +Q +q +1 0 0 1 50.01575 283.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 277.7008 cm +Q +q +1 0 0 1 50.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 253.7008 cm +Q +q +1 0 0 1 50.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 205.7008 cm +Q +q +1 0 0 1 50.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 181.7008 cm +Q +q +1 0 0 1 50.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 151.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 145.7008 cm +Q +q +1 0 0 1 50.01575 127.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 121.7008 cm +Q +q +1 0 0 1 50.01575 103.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 97.70079 cm +Q +q +1 0 0 1 50.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (83) Tj T* ET +Q +Q + +endstream +endobj +1285 0 obj +<< +/Length 7270 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 553.7008 cm +Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 529.7008 cm +Q +q +1 0 0 1 40.01575 511.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 462.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (linux package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 412.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpuid module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 400.5008 cm +Q +q +1 0 0 1 40.01575 382.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CPUID) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 370.5008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 364.5008 cm +Q +q +1 0 0 1 40.01575 346.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CPUID_struct) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 334.5008 cm +q +.933333 1 .8 rg +n 33.35 0 102 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (_ctypes.Structure) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 328.5008 cm +Q +q +1 0 0 1 50.01575 310.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (eax) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 298.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 292.5008 cm +Q +q +1 0 0 1 50.01575 274.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ebx) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 262.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 256.5008 cm +Q +q +1 0 0 1 50.01575 238.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ecx) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 226.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 220.5008 cm +Q +q +1 0 0 1 50.01575 202.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (edx) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 190.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 140.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (legacy_pci module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 128.9008 cm +Q +q +1 0 0 1 40.01575 110.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (LEGACY_PCI) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 98.90079 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 92.90079 cm +Q +q +1 0 0 1 50.01575 74.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (func) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 68.90079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (84) Tj T* ET +Q +Q + +endstream +endobj +1286 0 obj +<< +/Length 7452 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (func) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 757.7008 cm +Q +q +1 0 0 1 40.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PORTS) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 727.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 721.7008 cm +Q +q +1 0 0 1 50.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (inl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 697.7008 cm +Q +q +1 0 0 1 50.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (outl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 630.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (linuxhelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 612.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Linux helper) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 606.1008 cm +Q +q +1 0 0 1 40.01575 588.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (LinuxHelper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 576.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 570.1008 cm +Q +q +1 0 0 1 50.01575 552.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEVICE_NAME) Tj /F4 10 Tf ( = '/dev/chipsec') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 546.1008 cm +Q +q +1 0 0 1 50.01575 528.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEV_MEM) Tj /F4 10 Tf ( = '/dev/mem') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 522.1008 cm +Q +q +1 0 0 1 50.01575 504.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEV_PORT) Tj /F4 10 Tf ( = '/dev/port') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 498.1008 cm +Q +q +1 0 0 1 50.01575 480.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DKMS_DIR) Tj /F4 10 Tf ( = '/var/lib/dkms/') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 474.1008 cm +Q +q +1 0 0 1 50.01575 456.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 450.1008 cm +Q +q +1 0 0 1 50.01575 432.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_get_efivar_from_sys) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 426.1008 cm +Q +q +1 0 0 1 50.01575 408.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 402.1008 cm +Q +q +1 0 0 1 50.01575 384.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 378.1008 cm +Q +q +1 0 0 1 50.01575 360.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 354.1008 cm +Q +q +1 0 0 1 50.01575 336.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MODULE_NAME) Tj /F4 10 Tf ( = 'chipsec') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 330.1008 cm +Q +q +1 0 0 1 50.01575 312.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SUPPORT_KERNEL26_GET_PAGE_IS_RAM) Tj /F4 10 Tf ( = False) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 306.1008 cm +Q +q +1 0 0 1 50.01575 288.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SUPPORT_KERNEL26_GET_PHYS_MEM_ACCESS_PROT) Tj /F4 10 Tf ( = False) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 282.1008 cm +Q +q +1 0 0 1 50.01575 264.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 258.1008 cm +Q +q +1 0 0 1 50.01575 240.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_get_efivar_from_sys) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 234.1008 cm +Q +q +1 0 0 1 50.01575 216.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 210.1008 cm +Q +q +1 0 0 1 50.01575 192.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 186.1008 cm +Q +q +1 0 0 1 50.01575 168.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_bytes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 162.1008 cm +Q +q +1 0 0 1 50.01575 144.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (close) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 138.1008 cm +Q +q +1 0 0 1 50.01575 120.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 114.1008 cm +Q +q +1 0 0 1 50.01575 96.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compute_ioctlbase) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (itype) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('C') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 90.10079 cm +Q +q +1 0 0 1 50.01575 72.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (85) Tj T* ET +Q +Q + +endstream +endobj +1287 0 obj +<< +/Length 8001 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type1) Tj /F4 10 Tf ( = [1, 2]) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type2) Tj /F4 10 Tf ( = [1, 2, 3, 4]) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devmem_available) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 607.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/mem is usable.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 583.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via /dev/mem. Returns) Tj T* (True if /dev/mem is accessible.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 577.7008 cm +Q +q +1 0 0 1 50.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devmsr_available) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/cpu/CPUNUM/msr is usable.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 511.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via) Tj T* (/dev/cpu/CPUNUM/msr. This requires loading the \(more standard\) msr driver. Returns True if) Tj T* (/dev/cpu/CPUNUM/msr is accessible.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devport_available) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/port is usable.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 451.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via /dev/port. Returns True) Tj T* (if /dev/port is accessible.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physmem) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 421.7008 cm +Q +q +1 0 0 1 50.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 397.7008 cm +Q +q +1 0 0 1 50.01575 379.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 373.7008 cm +Q +q +1 0 0 1 50.01575 355.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 349.7008 cm +Q +q +1 0 0 1 50.01575 331.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 325.7008 cm +Q +q +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 301.7008 cm +Q +q +1 0 0 1 50.01575 283.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_dkms_module_location) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 277.7008 cm +Q +q +1 0 0 1 50.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_page_is_ram) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 253.7008 cm +Q +q +1 0 0 1 50.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_phys_mem_access_prot) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 205.7008 cm +Q +q +1 0 0 1 50.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 181.7008 cm +Q +q +1 0 0 1 50.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 157.7008 cm +Q +q +1 0 0 1 50.01575 139.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 133.7008 cm +Q +q +1 0 0 1 50.01575 115.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 109.7008 cm +Q +q +1 0 0 1 50.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ioctl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (nr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (mutate_flag) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 85.70079 cm +Q +q +1 0 0 1 50.01575 67.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 66.18898 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (86) Tj T* ET +Q +Q + +endstream +endobj +1288 0 obj +<< +/Length 11468 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_get_EFI_variable_full) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (7) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_chipsec_module) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (memory_mapping) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns the mmap region that fully encompasses this area.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 571.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Returns None if no region matches.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.7008 cm +Q +q +1 0 0 1 50.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 469.7008 cm +Q +q +1 0 0 1 50.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_ACPI_table) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 421.7008 cm +Q +q +1 0 0 1 50.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 397.7008 cm +Q +q +1 0 0 1 50.01575 379.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 373.7008 cm +Q +q +1 0 0 1 50.01575 355.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 343.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Map to memory a specific region.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.7008 cm +Q +q +1 0 0 1 50.01575 319.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.7008 cm +Q +q +1 0 0 1 50.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.7008 cm +Q +q +1 0 0 1 50.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (domain) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 241.7008 cm +Q +q +1 0 0 1 50.01575 223.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 217.7008 cm +Q +q +1 0 0 1 50.01575 199.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 193.7008 cm +Q +q +1 0 0 1 50.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 169.7008 cm +Q +q +1 0 0 1 50.01575 151.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 145.7008 cm +Q +q +1 0 0 1 50.01575 127.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 121.7008 cm +Q +q +1 0 0 1 50.01575 103.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (domain) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 97.70079 cm +Q +q +1 0 0 1 50.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (87) Tj T* ET +Q +Q + +endstream +endobj +1289 0 obj +<< +/Length 10335 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 655.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 649.7008 cm +Q +q +1 0 0 1 50.01575 631.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 625.7008 cm +Q +q +1 0 0 1 50.01575 607.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 601.7008 cm +Q +q +1 0 0 1 50.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rotate_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (n) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 577.7008 cm +Q +q +1 0 0 1 50.01575 559.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 553.7008 cm +Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 529.7008 cm +Q +q +1 0 0 1 50.01575 511.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 457.7008 cm +Q +q +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 433.7008 cm +Q +q +1 0 0 1 50.01575 415.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_efi_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 409.7008 cm +Q +q +1 0 0 1 50.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_efivars) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.7008 cm +Q +q +1 0 0 1 50.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 361.7008 cm +Q +q +1 0 0 1 50.01575 343.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.7008 cm +Q +q +1 0 0 1 50.01575 319.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.7008 cm +Q +q +1 0 0 1 50.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.7008 cm +Q +q +1 0 0 1 50.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 205.7008 cm +Q +q +1 0 0 1 40.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MemoryMapping) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (fileno) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (prot) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (offset) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 175.7008 cm +q +.933333 1 .8 rg +n 33.35 0 54 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (mmap.mmap) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 163.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Memory mapping based on Python\222s mmap.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 151.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This subclass keeps tracks of the start and end of the mapping.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 145.7008 cm +Q +q +1 0 0 1 40.01575 127.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (88) Tj T* ET +Q +Q + +endstream +endobj +1290 0 obj +<< +/Length 7604 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (osx package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 716.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (osxhelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 698.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (OSX helper) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 692.5008 cm +Q +q +1 0 0 1 40.01575 674.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (OSXHelper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 662.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 656.5008 cm +Q +q +1 0 0 1 50.01575 638.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEVICE_NAME) Tj /F4 10 Tf ( = '/dev/chipsec') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 632.5008 cm +Q +q +1 0 0 1 50.01575 614.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DRIVER_NAME) Tj /F4 10 Tf ( = 'chipsec.kext') Tj T* ET +Q +Q +q +1 0 0 1 50.01575 608.5008 cm +Q +q +1 0 0 1 50.01575 590.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 584.5008 cm +Q +q +1 0 0 1 50.01575 566.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_bytes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 560.5008 cm +Q +q +1 0 0 1 50.01575 542.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (close) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 536.5008 cm +Q +q +1 0 0 1 50.01575 518.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 512.5008 cm +Q +q +1 0 0 1 50.01575 494.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 488.5008 cm +Q +q +1 0 0 1 50.01575 470.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 464.5008 cm +Q +q +1 0 0 1 50.01575 446.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 440.5008 cm +Q +q +1 0 0 1 50.01575 422.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type1) Tj /F4 10 Tf ( = [1, 2]) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 416.5008 cm +Q +q +1 0 0 1 50.01575 398.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type2) Tj /F4 10 Tf ( = [1, 2, 3, 4]) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 392.5008 cm +Q +q +1 0 0 1 50.01575 374.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 368.5008 cm +Q +q +1 0 0 1 50.01575 350.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 344.5008 cm +Q +q +1 0 0 1 50.01575 326.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 320.5008 cm +Q +q +1 0 0 1 50.01575 302.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 296.5008 cm +Q +q +1 0 0 1 50.01575 278.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 272.5008 cm +Q +q +1 0 0 1 50.01575 254.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 248.5008 cm +Q +q +1 0 0 1 50.01575 230.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 224.5008 cm +Q +q +1 0 0 1 50.01575 206.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 200.5008 cm +Q +q +1 0 0 1 50.01575 182.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 176.5008 cm +Q +q +1 0 0 1 50.01575 158.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 152.5008 cm +Q +q +1 0 0 1 50.01575 134.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ioctl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ioctl_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 128.5008 cm +Q +q +1 0 0 1 50.01575 110.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 104.5008 cm +Q +q +1 0 0 1 50.01575 86.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_driver) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 80.50079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (89) Tj T* ET +Q +Q + +endstream +endobj +1291 0 obj +<< +/Length 11234 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mem_read_block) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (sz) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mem_write_block) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (sz) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35372,7 +37853,554 @@ Q q 1 0 0 1 50.01575 427.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 421.7008 cm +Q +q +1 0 0 1 50.01575 403.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.7008 cm +Q +q +1 0 0 1 50.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 361.7008 cm +Q +q +1 0 0 1 50.01575 343.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.7008 cm +Q +q +1 0 0 1 50.01575 319.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rotate_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (n) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.7008 cm +Q +q +1 0 0 1 50.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.7008 cm +Q +q +1 0 0 1 50.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 241.7008 cm +Q +q +1 0 0 1 50.01575 223.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 217.7008 cm +Q +q +1 0 0 1 50.01575 199.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 193.7008 cm +Q +q +1 0 0 1 50.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 169.7008 cm +Q +q +1 0 0 1 50.01575 151.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_efi_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 145.7008 cm +Q +q +1 0 0 1 50.01575 127.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 121.7008 cm +Q +q +1 0 0 1 50.01575 103.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 97.70079 cm +Q +q +1 0 0 1 50.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (90) Tj T* ET +Q +Q + +endstream +endobj +1292 0 obj +<< +/Length 6864 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 727.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 721.7008 cm +Q +q +1 0 0 1 50.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 697.7008 cm +Q +q +1 0 0 1 40.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 630.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rwe package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 580.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rwehelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 530.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (win package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 481.3008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (win32helper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 431.7008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (basehelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 419.7008 cm +Q +q +1 0 0 1 40.01575 401.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Helper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 389.7008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 383.7008 cm +Q +q +1 0 0 1 50.01575 365.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 359.7008 cm +Q +q +1 0 0 1 50.01575 341.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 335.7008 cm +Q +q +1 0 0 1 50.01575 317.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 311.7008 cm +Q +q +1 0 0 1 50.01575 293.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 287.7008 cm +Q +q +1 0 0 1 50.01575 269.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 263.7008 cm +Q +q +1 0 0 1 50.01575 245.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 239.7008 cm +Q +q +1 0 0 1 50.01575 221.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 215.7008 cm +Q +q +1 0 0 1 50.01575 197.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 191.7008 cm +Q +q +1 0 0 1 50.01575 173.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 167.7008 cm +Q +q +1 0 0 1 50.01575 149.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 143.7008 cm +Q +q +1 0 0 1 50.01575 125.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 119.7008 cm +Q +q +1 0 0 1 50.01575 101.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 95.70079 cm +Q +q +1 0 0 1 50.01575 77.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 71.70079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (91) Tj T* ET +Q +Q + +endstream +endobj +1293 0 obj +<< +/Length 11441 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_info) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 709.7008 cm +Q +q +1 0 0 1 50.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.7008 cm +Q +q +1 0 0 1 50.01575 475.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 469.7008 cm +Q +q +1 0 0 1 50.01575 451.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 445.7008 cm +Q +q +1 0 0 1 50.01575 427.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -35405,7 +38433,7 @@ Q q 1 0 0 1 50.01575 343.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bytewise) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -35423,2322 +38451,16 @@ Q q 1 0 0 1 50.01575 295.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exhists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 241.7008 cm -Q -q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (target_machine) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dword_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (81) Tj T* ET -Q -Q - -endstream -endobj -1286 0 obj -<< -/Length 7859 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bytewise) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 733.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (DALHelperError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 697.7008 cm -Q -q -1 0 0 1 40.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 630.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (efi package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 580.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (efihelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 562.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (On UEFI use the efi package functions) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 556.5008 cm -Q -q -1 0 0 1 40.01575 538.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (EfiHelper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 526.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 520.5008 cm -Q -q -1 0 0 1 50.01575 502.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 496.5008 cm -Q -q -1 0 0 1 50.01575 478.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 472.5008 cm -Q -q -1 0 0 1 50.01575 454.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 448.5008 cm -Q -q -1 0 0 1 50.01575 430.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 424.5008 cm -Q -q -1 0 0 1 50.01575 406.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 400.5008 cm -Q -q -1 0 0 1 50.01575 382.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 376.5008 cm -Q -q -1 0 0 1 50.01575 358.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 352.5008 cm -Q -q -1 0 0 1 50.01575 334.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 328.5008 cm -Q -q -1 0 0 1 50.01575 310.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable_full) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 304.5008 cm -Q -q -1 0 0 1 50.01575 286.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 280.5008 cm -Q -q -1 0 0 1 50.01575 262.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 256.5008 cm -Q -q -1 0 0 1 50.01575 238.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 232.5008 cm -Q -q -1 0 0 1 50.01575 214.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 208.5008 cm -Q -q -1 0 0 1 50.01575 190.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 184.5008 cm -Q -q -1 0 0 1 50.01575 166.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 160.5008 cm -Q -q -1 0 0 1 50.01575 142.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 136.5008 cm -Q -q -1 0 0 1 50.01575 118.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 112.5008 cm -Q -q -1 0 0 1 50.01575 94.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 88.50079 cm -Q -q -1 0 0 1 50.01575 70.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (82) Tj T* ET -Q -Q - -endstream -endobj -1287 0 obj -<< -/Length 9913 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (pa2va) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guidstr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (7) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 553.7008 cm -Q -q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 361.7008 cm -Q -q -1 0 0 1 50.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 301.7008 cm -Q -q -1 0 0 1 40.01575 283.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (EfiHelperError) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 271.7008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 265.7008 cm -Q -q -1 0 0 1 40.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 198.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (file package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 148.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (filehelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 130.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Use results from a json file) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 124.5008 cm -Q -q -1 0 0 1 40.01575 106.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FileCmds) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (filename) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 94.50079 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 88.50079 cm -Q -q -1 0 0 1 50.01575 70.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (AddElement) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cmd) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ret) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (83) Tj T* ET -Q -Q - -endstream -endobj -1288 0 obj -<< -/Length 9562 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (Load) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (Save) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getElement) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cmd) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 709.7008 cm -Q -q -1 0 0 1 40.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (FileHelper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 679.7008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 673.7008 cm -Q -q -1 0 0 1 50.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 553.7008 cm -Q -q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 361.7008 cm -Q -q -1 0 0 1 50.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 313.7008 cm -Q -q -1 0 0 1 50.01575 295.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 241.7008 cm -Q -q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (84) Tj T* ET -Q -Q - -endstream -endobj -1289 0 obj -<< -/Length 9215 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 703.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 697.7008 cm -Q -q -1 0 0 1 50.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 673.7008 cm -Q -q -1 0 0 1 50.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 553.7008 cm -Q -q -1 0 0 1 50.01575 535.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 373.7008 cm -Q -q -1 0 0 1 40.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 306.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (linux package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 256.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpuid module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 244.5008 cm -Q -q -1 0 0 1 40.01575 226.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CPUID) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 214.5008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 208.5008 cm -Q -q -1 0 0 1 40.01575 190.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (CPUID_struct) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 178.5008 cm -q -.933333 1 .8 rg -n 33.35 0 102 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (_ctypes.Structure) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 172.5008 cm -Q -q -1 0 0 1 50.01575 154.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (eax) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 142.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 136.5008 cm -Q -q -1 0 0 1 50.01575 118.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ebx) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 106.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -Q -q -1 0 0 1 50.01575 82.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ecx) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 70.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (85) Tj T* ET -Q -Q - -endstream -endobj -1290 0 obj -<< -/Length 6627 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (edx) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 751.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Structure/Union member) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 702.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (legacy_pci module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 690.1008 cm -Q -q -1 0 0 1 40.01575 672.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (LEGACY_PCI) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 660.1008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 654.1008 cm -Q -q -1 0 0 1 50.01575 636.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (func) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 630.1008 cm -Q -q -1 0 0 1 50.01575 612.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (func) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 606.1008 cm -Q -q -1 0 0 1 40.01575 588.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (PORTS) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 576.1008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 570.1008 cm -Q -q -1 0 0 1 50.01575 552.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (inl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 546.1008 cm -Q -q -1 0 0 1 50.01575 528.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (outl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (port) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 478.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (linuxhelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 460.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Linux helper) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 454.5008 cm -Q -q -1 0 0 1 40.01575 436.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (LinuxHelper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 424.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 418.5008 cm -Q -q -1 0 0 1 50.01575 400.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEVICE_NAME) Tj /F4 10 Tf ( = '/dev/chipsec') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 394.5008 cm -Q -q -1 0 0 1 50.01575 376.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEV_MEM) Tj /F4 10 Tf ( = '/dev/mem') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 370.5008 cm -Q -q -1 0 0 1 50.01575 352.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEV_PORT) Tj /F4 10 Tf ( = '/dev/port') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 346.5008 cm -Q -q -1 0 0 1 50.01575 328.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DKMS_DIR) Tj /F4 10 Tf ( = '/var/lib/dkms/') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 322.5008 cm -Q -q -1 0 0 1 50.01575 304.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 298.5008 cm -Q -q -1 0 0 1 50.01575 280.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_get_efivar_from_sys) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 274.5008 cm -Q -q -1 0 0 1 50.01575 256.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 250.5008 cm -Q -q -1 0 0 1 50.01575 232.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFIVARS_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 226.5008 cm -Q -q -1 0 0 1 50.01575 208.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 202.5008 cm -Q -q -1 0 0 1 50.01575 184.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (MODULE_NAME) Tj /F4 10 Tf ( = 'chipsec') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 178.5008 cm -Q -q -1 0 0 1 50.01575 160.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SUPPORT_KERNEL26_GET_PAGE_IS_RAM) Tj /F4 10 Tf ( = False) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 154.5008 cm -Q -q -1 0 0 1 50.01575 136.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (SUPPORT_KERNEL26_GET_PHYS_MEM_ACCESS_PROT) Tj /F4 10 Tf ( = False) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 130.5008 cm -Q -q -1 0 0 1 50.01575 112.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 106.5008 cm -Q -q -1 0 0 1 50.01575 88.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_get_efivar_from_sys) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 82.50079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (86) Tj T* ET -Q -Q - -endstream -endobj -1291 0 obj -<< -/Length 7558 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (VARS_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_bytes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (close) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compute_ioctlbase) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (itype) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('C') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type1) Tj /F4 10 Tf ( = [1, 2]) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type2) Tj /F4 10 Tf ( = [1, 2, 3, 4]) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devmem_available) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/mem is usable.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 415.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via /dev/mem. Returns) Tj T* (True if /dev/mem is accessible.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devmsr_available) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/cpu/CPUNUM/msr is usable.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 343.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via) Tj T* (/dev/cpu/CPUNUM/msr. This requires loading the \(more standard\) msr driver. Returns True if) Tj T* (/dev/cpu/CPUNUM/msr is accessible.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (devport_available) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check if /dev/port is usable.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 283.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (In case the driver is not loaded, we might be able to perform the requested operation via /dev/port. Returns True) Tj T* (if /dev/port is accessible.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 277.7008 cm -Q -q -1 0 0 1 50.01575 259.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physmem) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 253.7008 cm -Q -q -1 0 0 1 50.01575 235.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 229.7008 cm -Q -q -1 0 0 1 50.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 205.7008 cm -Q -q -1 0 0 1 50.01575 187.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 181.7008 cm -Q -q -1 0 0 1 50.01575 163.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 157.7008 cm -Q -q -1 0 0 1 50.01575 139.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 133.7008 cm -Q -q -1 0 0 1 50.01575 115.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_dkms_module_location) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 109.7008 cm -Q -q -1 0 0 1 50.01575 91.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_page_is_ram) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 85.70079 cm -Q -q -1 0 0 1 50.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_phys_mem_access_prot) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (87) Tj T* ET -Q -Q - -endstream -endobj -1292 0 obj -<< -/Length 10213 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ioctl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (nr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .619608 .415686 .533333 rg (*) Tj .396078 .588235 .639216 rg (mutate_flag) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_get_EFI_variable_full) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (kern_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (7) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_chipsec_module) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 445.7008 cm -Q -q -1 0 0 1 50.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (memory_mapping) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns the mmap region that fully encompasses this area.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 403.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Returns None if no region matches.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 373.7008 cm -Q -q -1 0 0 1 50.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 349.7008 cm -Q -q -1 0 0 1 50.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 301.7008 cm -Q -q -1 0 0 1 50.01575 283.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 277.7008 cm -Q -q -1 0 0 1 50.01575 259.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_ACPI_table) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 253.7008 cm -Q -q -1 0 0 1 50.01575 235.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 229.7008 cm -Q -q -1 0 0 1 50.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 205.7008 cm -Q -q -1 0 0 1 50.01575 187.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Map to memory a specific region.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (domain) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 73.70079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (88) Tj T* ET -Q -Q - -endstream -endobj -1293 0 obj -<< -/Length 12525 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (domain) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rotate_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (n) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 361.7008 cm -Q -q -1 0 0 1 50.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 313.7008 cm -Q -q -1 0 0 1 50.01575 295.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q 1 0 0 1 50.01575 289.7008 cm Q q 1 0 0 1 50.01575 271.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -37747,7 +38469,7 @@ Q q 1 0 0 1 50.01575 247.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_efi_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -37756,907 +38478,65 @@ Q q 1 0 0 1 50.01575 223.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_efivars) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (89) Tj T* ET -Q -Q - -endstream -endobj -1294 0 obj -<< -/Length 7319 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (MemoryMapping) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (fileno) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (flags) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (prot) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (offset) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 727.7008 cm -q -.933333 1 .8 rg -n 33.35 0 54 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (mmap.mmap) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 715.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Memory mapping based on Python\222s mmap.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This subclass keeps tracks of the start and end of the mapping.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 697.7008 cm -Q -q -1 0 0 1 40.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 630.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (osx package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 580.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (osxhelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 562.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (OSX helper) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 556.5008 cm -Q -q -1 0 0 1 40.01575 538.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (OSXHelper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 526.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.basehelper.Helper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 520.5008 cm -Q -q -1 0 0 1 50.01575 502.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DEVICE_NAME) Tj /F4 10 Tf ( = '/dev/chipsec') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 496.5008 cm -Q -q -1 0 0 1 50.01575 478.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DRIVER_NAME) Tj /F4 10 Tf ( = 'chipsec.kext') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 472.5008 cm -Q -q -1 0 0 1 50.01575 454.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 448.5008 cm -Q -q -1 0 0 1 50.01575 430.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (num_bytes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 424.5008 cm -Q -q -1 0 0 1 50.01575 406.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (close) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 400.5008 cm -Q -q -1 0 0 1 50.01575 382.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 376.5008 cm -Q -q -1 0 0 1 50.01575 358.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 352.5008 cm -Q -q -1 0 0 1 50.01575 334.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 328.5008 cm -Q -q -1 0 0 1 50.01575 310.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 304.5008 cm -Q -q -1 0 0 1 50.01575 286.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type1) Tj /F4 10 Tf ( = [1, 2]) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 280.5008 cm -Q -q -1 0 0 1 50.01575 262.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompression_oder_type2) Tj /F4 10 Tf ( = [1, 2, 3, 4]) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 256.5008 cm -Q -q -1 0 0 1 50.01575 238.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 232.5008 cm -Q -q -1 0 0 1 50.01575 214.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 208.5008 cm -Q -q -1 0 0 1 50.01575 190.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 184.5008 cm -Q -q -1 0 0 1 50.01575 166.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 160.5008 cm -Q -q -1 0 0 1 50.01575 142.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 136.5008 cm -Q -q -1 0 0 1 50.01575 118.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 112.5008 cm -Q -q -1 0 0 1 50.01575 94.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tool_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (tool_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 88.50079 cm -Q -q -1 0 0 1 50.01575 70.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (90) Tj T* ET -Q -Q - -endstream -endobj -1295 0 obj -<< -/Length 11216 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (init) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ioctl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ioctl_name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_driver) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 661.7008 cm -Q -q -1 0 0 1 50.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mem_read_block) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (sz) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mem_write_block) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (sz) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (newval) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 445.7008 cm -Q -q -1 0 0 1 50.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 421.7008 cm -Q -q -1 0 0 1 50.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (native_set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 373.7008 cm -Q -q -1 0 0 1 50.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 349.7008 cm -Q -q -1 0 0 1 50.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 301.7008 cm -Q -q -1 0 0 1 50.01575 283.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 241.7008 cm -Q -q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rotate_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (n) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 73.70079 cm +1 0 0 1 50.01575 217.7008 cm Q q -1 0 0 1 34.01575 795.874 cm +1 0 0 1 50.01575 199.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_native_api) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (91) Tj T* ET +1 0 0 1 50.01575 193.7008 cm Q -Q - -endstream -endobj -1296 0 obj -<< -/Length 7592 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 50.01575 175.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 50.01575 169.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (unknown_efi_decompress) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 50.01575 151.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 50.01575 145.7008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 127.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 121.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 103.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 50.01575 97.70079 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 50.01575 79.70079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 577.7008 cm -Q -q -1 0 0 1 40.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 510.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rwe package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 460.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rwehelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 410.9008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (win package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 361.3008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (win32helper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 311.7008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (basehelper module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 299.7008 cm -Q -q -1 0 0 1 40.01575 281.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (Helper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 269.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 263.7008 cm -Q -q -1 0 0 1 50.01575 245.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 239.7008 cm -Q -q -1 0 0 1 50.01575 221.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 215.7008 cm -Q -q -1 0 0 1 50.01575 197.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 191.7008 cm -Q -q -1 0 0 1 50.01575 173.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 167.7008 cm -Q -q -1 0 0 1 50.01575 149.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (create) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 143.7008 cm -Q -q -1 0 0 1 50.01575 125.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 119.7008 cm -Q -q -1 0 0 1 50.01575 101.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 95.70079 cm -Q -q -1 0 0 1 50.01575 77.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 71.70079 cm +1 0 0 1 50.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -38674,278 +38554,271 @@ Q endstream endobj -1297 0 obj +1294 0 obj << -/Length 10704 +/Length 8612 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 60.01575 751.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 50.01575 745.7008 cm +Q +q +1 0 0 1 50.01575 727.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 678.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (helpers module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 628.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (oshelper module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 610.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Abstracts support for various OS/environments, wrapper around platform specific code that invokes kernel driver) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 604.5008 cm +Q +q +1 0 0 1 40.01575 586.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (OsHelper) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 574.5008 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 568.5008 cm +Q +q +1 0 0 1 50.01575 550.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 544.5008 cm +Q +q +1 0 0 1 50.01575 526.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 520.5008 cm +Q +q +1 0 0 1 50.01575 502.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 496.5008 cm +Q +q +1 0 0 1 50.01575 478.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 472.5008 cm +Q +q +1 0 0 1 50.01575 454.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 448.5008 cm +Q +q +1 0 0 1 50.01575 430.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 424.5008 cm +Q +q +1 0 0 1 50.01575 406.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 400.5008 cm +Q +q +1 0 0 1 50.01575 382.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 50.01575 376.5008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 50.01575 358.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 50.01575 352.5008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 334.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 328.5008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 310.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 50.01575 304.5008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 50.01575 286.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 50.01575 280.5008 cm Q q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_info) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 50.01575 262.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 50.01575 256.5008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 50.01575 238.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 50.01575 232.5008 cm Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 50.01575 214.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 541.7008 cm +1 0 0 1 50.01575 208.5008 cm Q q -1 0 0 1 50.01575 523.7008 cm +1 0 0 1 50.01575 190.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_dal) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 517.7008 cm +1 0 0 1 50.01575 184.5008 cm Q q -1 0 0 1 50.01575 499.7008 cm +1 0 0 1 50.01575 166.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_efi) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 493.7008 cm +1 0 0 1 50.01575 160.5008 cm Q q -1 0 0 1 50.01575 475.7008 cm +1 0 0 1 50.01575 142.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_linux) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 469.7008 cm +1 0 0 1 50.01575 136.5008 cm Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 50.01575 118.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_macos) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 445.7008 cm +1 0 0 1 50.01575 112.5008 cm Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 50.01575 94.50079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_win8_or_greater) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 421.7008 cm +1 0 0 1 50.01575 88.50079 cm Q q -1 0 0 1 50.01575 403.7008 cm +1 0 0 1 50.01575 70.50079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_windows) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 373.7008 cm -Q -q -1 0 0 1 50.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 349.7008 cm -Q -q -1 0 0 1 50.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 325.7008 cm -Q -q -1 0 0 1 50.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 301.7008 cm -Q -q -1 0 0 1 50.01575 283.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 241.7008 cm -Q -q -1 0 0 1 50.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 193.7008 cm -Q -q -1 0 0 1 50.01575 175.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 121.7008 cm -Q -q -1 0 0 1 50.01575 103.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_native_api) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 73.70079 cm +1 0 0 1 50.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -38963,16 +38836,16 @@ Q endstream endobj -1298 0 obj +1295 0 obj << -/Length 8374 +/Length 11486 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -38981,7 +38854,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (loadHelpers) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -38990,7 +38863,7 @@ Q q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -38999,7 +38872,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -39008,7 +38881,7 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -39017,216 +38890,230 @@ Q q 1 0 0 1 50.01575 643.7008 cm q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 637.7008 cm +Q +q +1 0 0 1 50.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 457.7008 cm +Q +q +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 433.7008 cm +Q +q +1 0 0 1 50.01575 415.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 409.7008 cm +Q +q +1 0 0 1 50.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.7008 cm +Q +q +1 0 0 1 50.01575 367.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 361.7008 cm +Q +q +1 0 0 1 50.01575 343.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (to_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 337.7008 cm +Q +q +1 0 0 1 50.01575 319.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 313.7008 cm +Q +q +1 0 0 1 50.01575 295.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_native_api) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 265.7008 cm +Q +q +1 0 0 1 50.01575 247.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 241.7008 cm +Q +q +1 0 0 1 50.01575 223.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 217.7008 cm +Q +q +1 0 0 1 50.01575 199.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 193.7008 cm +Q +q +1 0 0 1 50.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 169.7008 cm +Q +q +1 0 0 1 50.01575 151.7008 cm +q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 60.01575 631.7008 cm +1 0 0 1 60.01575 139.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET Q Q q -1 0 0 1 50.01575 625.7008 cm +1 0 0 1 50.01575 133.7008 cm Q q -1 0 0 1 50.01575 607.7008 cm +1 0 0 1 50.01575 115.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_phys_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_hi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address_lo) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 558.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* +1 0 0 1 40.01575 109.7008 cm Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (helpers module) Tj T* ET +1 0 0 1 40.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (f_mod_zip) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (x) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 508.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* +1 0 0 1 40.01575 85.70079 cm Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (oshelper module) Tj T* ET +1 0 0 1 40.01575 67.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tools_path) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 490.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Abstracts support for various OS/environments, wrapper around platform specific code that invokes kernel driver) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 484.5008 cm -Q -q -1 0 0 1 40.01575 466.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (HWAccessViolationError) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (msg) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (errorcode) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 454.5008 cm -q -.933333 1 .8 rg -n 33.35 0 222 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.oshelper.OsHelperError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 448.5008 cm -Q -q -1 0 0 1 40.01575 430.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (OsHelper) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 418.5008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 412.5008 cm -Q -q -1 0 0 1 50.01575 394.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (EFI_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 388.5008 cm -Q -q -1 0 0 1 50.01575 370.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (alloc_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (max_phys_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 364.5008 cm -Q -q -1 0 0 1 50.01575 346.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (compress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (FileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 340.5008 cm -Q -q -1 0 0 1 50.01575 322.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 316.5008 cm -Q -q -1 0 0 1 50.01575 298.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (decompress_file) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressedFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (OutputFileName) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (CompressionType) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 292.5008 cm -Q -q -1 0 0 1 50.01575 274.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (delete_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 268.5008 cm -Q -q -1 0 0 1 50.01575 250.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (free_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 244.5008 cm -Q -q -1 0 0 1 50.01575 226.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_SDT) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 220.5008 cm -Q -q -1 0 0 1 50.01575 202.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_ACPI_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (table_name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 196.5008 cm -Q -q -1 0 0 1 50.01575 178.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 172.5008 cm -Q -q -1 0 0 1 50.01575 154.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_affinity) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 148.5008 cm -Q -q -1 0 0 1 50.01575 130.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_descriptor_table) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc_table_code) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 124.5008 cm -Q -q -1 0 0 1 50.01575 106.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_threads_count) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -Q -q -1 0 0 1 50.01575 82.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getcwd) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 76.50079 cm +1 0 0 1 40.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -39244,278 +39131,287 @@ Q endstream endobj -1299 0 obj +1296 0 obj << -/Length 10981 +/Length 7363 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r8) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r9) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r10) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (r11) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (xmm_buffer) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_dal) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_modname_zip) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (x) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm -Q +1 0 0 1 40.01575 687.7008 cm q -1 0 0 1 50.01575 715.7008 cm +1 1 1 RG +.3 w +.396078 .721569 .352941 rg +n -10 0 525.2441 18 re B* +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_efi) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 1 1 1 rg (Fuzzing) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm -Q +1 0 0 1 40.01575 638.1008 cm q -1 0 0 1 50.01575 691.7008 cm +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_linux) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (fuzzing package) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm -Q +1 0 0 1 40.01575 588.5008 cm q -1 0 0 1 50.01575 667.7008 cm +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_macos) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (primitives module) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 40.01575 576.5008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 40.01575 558.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_win8_or_greater) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (base_primitive) Tj T* ET Q -q -1 0 0 1 50.01575 637.7008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 50.01575 546.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_windows) Tj /F2 10 Tf ( \(\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm -Q +1 0 0 1 50.01575 534.5008 cm q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (list_EFI_variables) Tj /F2 10 Tf ( \(\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The primitive base class implements common functionality shared across most primitives.) Tj T* ET Q Q q -1 0 0 1 50.01575 589.7008 cm +1 0 0 1 50.01575 528.5008 cm Q q -1 0 0 1 50.01575 571.7008 cm +1 0 0 1 50.01575 510.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (loadHelpers) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (exhaust) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 565.7008 cm +1 0 0 1 60.01575 498.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Exhaust the possible mutations for this primitive.) Tj T* ET +Q Q q -1 0 0 1 50.01575 547.7008 cm +1 0 0 1 60.01575 486.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (load_ucode_update) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ucode_update_buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: The number of mutations to reach exhaustion) Tj T* ET Q Q q -1 0 0 1 50.01575 541.7008 cm +1 0 0 1 50.01575 480.5008 cm Q q -1 0 0 1 50.01575 523.7008 cm +1 0 0 1 50.01575 462.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_io_space) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (physical_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cache_type) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 517.7008 cm +1 0 0 1 60.01575 450.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive by stepping through the fuzz library, return False on completion.) Tj T* ET +Q Q q -1 0 0 1 50.01575 499.7008 cm +1 0 0 1 60.01575 438.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Boolean @return: True on success, False otherwise.) Tj T* ET Q Q q -1 0 0 1 50.01575 493.7008 cm +1 0 0 1 50.01575 432.5008 cm Q q -1 0 0 1 50.01575 475.7008 cm +1 0 0 1 50.01575 414.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_read_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 469.7008 cm +1 0 0 1 60.01575 402.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Calculate and return the total number of mutations for this individual primitive.) Tj T* ET +Q Q q -1 0 0 1 50.01575 451.7008 cm +1 0 0 1 60.01575 390.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msgbus_send_write_message) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mcr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mcrx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mdr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of mutated forms this primitive can take) Tj T* ET Q Q q -1 0 0 1 50.01575 445.7008 cm +1 0 0 1 50.01575 384.5008 cm Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 50.01575 366.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET Q -q -1 0 0 1 50.01575 421.7008 cm Q q -1 0 0 1 50.01575 403.7008 cm +1 0 0 1 60.01575 354.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Nothing fancy on render, simply return the value.) Tj T* ET Q Q q -1 0 0 1 50.01575 397.7008 cm +1 0 0 1 50.01575 348.5008 cm Q q -1 0 0 1 50.01575 379.7008 cm +1 0 0 1 50.01575 330.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (reset) Tj /F2 10 Tf ( \(\)) Tj T* ET Q -q -1 0 0 1 50.01575 373.7008 cm Q q -1 0 0 1 50.01575 355.7008 cm +1 0 0 1 60.01575 318.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reset this primitive to the starting mutation state.) Tj T* ET Q Q q -1 0 0 1 50.01575 349.7008 cm +1 0 0 1 40.01575 312.5008 cm Q q -1 0 0 1 50.01575 331.7008 cm +1 0 0 1 40.01575 282.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bit_field) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_num) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 60.01575 319.7008 cm +1 0 0 1 50.01575 270.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Read PCI configuration registers via legacy CF8/CFC ports) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET Q Q q -1 0 0 1 50.01575 313.7008 cm +1 0 0 1 50.01575 264.5008 cm Q q -1 0 0 1 50.01575 295.7008 cm +1 0 0 1 50.01575 246.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_integer_boundaries) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (integer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm +1 0 0 1 60.01575 234.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (retpoline_enabled) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Add the supplied integer and border cases to the integer fuzz heuristics library.) Tj T* ET Q Q q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm +1 0 0 1 60.01575 222.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_sw_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (SMI_code_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type integer: Int @param integer: Integer to append to fuzz heuristics) Tj T* ET Q Q q -1 0 0 1 50.01575 241.7008 cm +1 0 0 1 50.01575 216.5008 cm Q q -1 0 0 1 50.01575 223.7008 cm +1 0 0 1 50.01575 198.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_EFI_variable) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (datasize) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 217.7008 cm -Q -q -1 0 0 1 50.01575 199.7008 cm +1 0 0 1 60.01575 186.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_affinity) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Render the primitive.) Tj T* ET Q Q q -1 0 0 1 50.01575 193.7008 cm +1 0 0 1 50.01575 180.5008 cm Q q -1 0 0 1 50.01575 175.7008 cm +1 0 0 1 50.01575 162.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (start) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (driver_exists) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (to_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (from_file) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (to_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (number) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bit_count) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 169.7008 cm -Q -q -1 0 0 1 50.01575 151.7008 cm +1 0 0 1 60.01575 150.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stop) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (start_driver) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Convert a number to a binary string.) Tj T* ET Q Q q -1 0 0 1 50.01575 145.7008 cm +1 0 0 1 60.01575 126.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (@type number: Integer @param number: \(Optional, def=self.value\) Number to convert @type bit_count: Integer) Tj T* (@param bit_count: \(Optional, def=self.width\) Width of bit string) Tj T* ET +Q Q q -1 0 0 1 50.01575 127.7008 cm +1 0 0 1 60.01575 114.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (use_native_api) Tj /F2 10 Tf ( \(\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: String @return: Bit string) Tj T* ET Q Q q -1 0 0 1 50.01575 121.7008 cm +1 0 0 1 50.01575 108.5008 cm Q q -1 0 0 1 50.01575 103.7008 cm +1 0 0 1 50.01575 90.50079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (va2pa) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (va) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (to_decimal) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (binary) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm +1 0 0 1 60.01575 78.50079 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_cr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cr_number) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Convert a binary string to a decimal number.) Tj T* ET Q Q q -1 0 0 1 50.01575 73.70079 cm +1 0 0 1 60.01575 66.50079 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type binary: String @param binary: Binary string) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -39533,58 +39429,68 @@ Q endstream endobj -1300 0 obj +1297 0 obj << -/Length 7864 +/Length 11368 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 60.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_io_port) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (io_port) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Converted bit string) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 40.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_mmio_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (offset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (byte) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm -Q +1 0 0 1 50.01575 727.7008 cm q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_msr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpu_thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (edx) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 216 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 40.01575 721.7008 cm +Q +q +1 0 0 1 40.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (delim) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_pci_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (device) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (function) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET Q Q q -1 0 0 1 60.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Write PCI configuration registers via legacy CF8/CFC ports) Tj T* ET -Q +1 0 0 1 40.01575 685.7008 cm Q q -1 0 0 1 50.01575 673.7008 cm +1 0 0 1 40.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (dword) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 50.01575 655.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (phys_address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (length) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buf) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 216 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET Q Q q @@ -39593,58 +39499,59 @@ Q q 1 0 0 1 40.01575 631.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (OsHelperError) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (msg) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (errorcode) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (group) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (name) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (values) Tj 0 0 0 rg (\)) Tj T* ET Q Q q 1 0 0 1 50.01575 619.7008 cm q .933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET Q Q q -1 0 0 1 40.01575 613.7008 cm +1 0 0 1 50.01575 613.7008 cm Q q -1 0 0 1 40.01575 595.7008 cm +1 0 0 1 50.01575 595.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (UnimplementedAPIError) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (api_name) Tj 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 583.7008 cm +1 0 0 1 60.01575 583.7008 cm q -.933333 1 .8 rg -n 33.35 0 222 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.oshelper.OsHelperError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Move to the next item in the values list.) Tj T* ET Q Q q -1 0 0 1 40.01575 577.7008 cm +1 0 0 1 60.01575 571.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: False @return: False) Tj T* ET +Q Q q -1 0 0 1 40.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (UnimplementedNativeAPIError) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (api_name) Tj 0 0 0 rg (\)) Tj T* ET -Q +1 0 0 1 50.01575 565.7008 cm Q q 1 0 0 1 50.01575 547.7008 cm q -.933333 1 .8 rg -n 33.35 0 270 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.helper.oshelper.UnimplementedAPIError) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 541.7008 cm +1 0 0 1 60.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Number of values in this primitive.) Tj T* ET +Q Q q -1 0 0 1 40.01575 523.7008 cm +1 0 0 1 60.01575 523.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (f_mod_zip) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (x) Tj .839216 .701961 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of values in this primitive.) Tj T* ET Q Q q @@ -39653,7 +39560,7 @@ Q q 1 0 0 1 40.01575 499.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_tools_path) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isinteger) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (var) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q @@ -39662,161 +39569,189 @@ Q q 1 0 0 1 40.01575 475.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (helper) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (qword) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 469.7008 cm -Q -q -1 0 0 1 40.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (map_modname_zip) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (x) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 399.7008 cm -q -1 1 1 RG -.3 w -.396078 .721569 .352941 rg -n -10 0 525.2441 18 re B* -Q -q -BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 1 1 1 rg (Fuzzing) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 350.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (fuzzing package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 300.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (primitives module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 288.5008 cm -Q -q -1 0 0 1 40.01575 270.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 258.5008 cm +1 0 0 1 50.01575 463.7008 cm q .933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +n 33.35 0 216 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET Q Q q -1 0 0 1 50.01575 246.5008 cm +1 0 0 1 40.01575 457.7008 cm +Q q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The primitive base class implements common functionality shared across most primitives.) Tj T* ET +1 0 0 1 40.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (random_data) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (min_length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_mutations) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (25) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (step) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 240.5008 cm -Q +1 0 0 1 50.01575 427.7008 cm q -1 0 0 1 50.01575 222.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (exhaust) Tj /F2 10 Tf ( \(\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET Q Q q -1 0 0 1 60.01575 210.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Exhaust the possible mutations for this primitive.) Tj T* ET -Q +1 0 0 1 50.01575 421.7008 cm Q q -1 0 0 1 60.01575 198.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: The number of mutations to reach exhaustion) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 192.5008 cm -Q -q -1 0 0 1 50.01575 174.5008 cm +1 0 0 1 50.01575 403.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 162.5008 cm +1 0 0 1 60.01575 391.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive by stepping through the fuzz library, return False on completion.) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive value returning False on completion.) Tj T* ET Q Q q -1 0 0 1 60.01575 150.5008 cm +1 0 0 1 60.01575 379.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Boolean @return: True on success, False otherwise.) Tj T* ET Q Q q -1 0 0 1 50.01575 144.5008 cm +1 0 0 1 50.01575 373.7008 cm Q q -1 0 0 1 50.01575 126.5008 cm +1 0 0 1 50.01575 355.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 114.5008 cm +1 0 0 1 60.01575 343.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Calculate and return the total number of mutations for this individual primitive.) Tj T* ET Q Q q -1 0 0 1 60.01575 102.5008 cm +1 0 0 1 60.01575 331.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of mutated forms this primitive can take) Tj T* ET Q Q q -1 0 0 1 50.01575 96.50079 cm +1 0 0 1 40.01575 325.7008 cm Q q -1 0 0 1 50.01575 78.50079 cm +1 0 0 1 40.01575 307.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (static) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 60.01575 66.50079 cm +1 0 0 1 50.01575 295.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Nothing fancy on render, simply return the value.) Tj T* ET +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET Q Q q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 50.01575 289.7008 cm +Q +q +1 0 0 1 50.01575 271.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Do nothing.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 247.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: False @return: False) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 241.7008 cm +Q +q +1 0 0 1 50.01575 223.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Return 0.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 199.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: 0 @return: 0) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 193.7008 cm +Q +q +1 0 0 1 40.01575 175.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (string) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (- 1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (padding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (encoding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('ascii') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_len) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 163.7008 cm +q +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 157.7008 cm +Q +q +1 0 0 1 50.01575 139.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_long_strings) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sequence) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 115.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Given a sequence, generate a number of selectively chosen strings lengths of the given sequence and add to) Tj T* (the string heuristic library.) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 103.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type sequence: String @param sequence: Sequence to repeat for creation of fuzz strings.) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 97.70079 cm +Q +q +1 0 0 1 50.01575 79.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_library) Tj /F4 10 Tf ( = []) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 73.70079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -39834,394 +39769,51 @@ Q endstream endobj -1301 0 obj +1298 0 obj << -/Length 11851 +/Length 9025 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (reset) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 751.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reset this primitive to the starting mutation state.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 745.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bit_field) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (width) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_num) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (,) Tj T* .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 697.7008 cm -Q -q -1 0 0 1 50.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_integer_boundaries) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (integer) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Add the supplied integer and border cases to the integer fuzz heuristics library.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 655.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type integer: Int @param integer: Integer to append to fuzz heuristics) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Render the primitive.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 613.7008 cm -Q -q -1 0 0 1 50.01575 595.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (to_binary) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (number) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bit_count) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Convert a number to a binary string.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 559.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (@type number: Integer @param number: \(Optional, def=self.value\) Number to convert @type bit_count: Integer) Tj T* (@param bit_count: \(Optional, def=self.width\) Width of bit string) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 547.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: String @return: Bit string) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (to_decimal) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (binary) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Convert a binary string to a decimal number.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 499.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type binary: String @param binary: Binary string) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 487.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Converted bit string) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 481.7008 cm -Q -q -1 0 0 1 40.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (byte) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 451.7008 cm -q -.933333 1 .8 rg -n 33.35 0 216 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 445.7008 cm -Q -q -1 0 0 1 40.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (delim) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 415.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 409.7008 cm -Q -q -1 0 0 1 40.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (dword) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 379.7008 cm -q -.933333 1 .8 rg -n 33.35 0 216 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 373.7008 cm -Q -q -1 0 0 1 40.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (group) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (name) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (values) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 343.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 307.7008 cm +1 0 0 1 60.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Move to the next item in the values list.) Tj T* ET +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive by stepping through the fuzz library extended with the \223this\224 library, return False on) Tj T* (completion.) Tj T* ET Q Q q -1 0 0 1 60.01575 295.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: False @return: False) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 259.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Number of values in this primitive.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 247.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of values in this primitive.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 241.7008 cm -Q -q -1 0 0 1 40.01575 223.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (isinteger) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (var) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 217.7008 cm -Q -q -1 0 0 1 40.01575 199.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (qword) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 187.7008 cm -q -.933333 1 .8 rg -n 33.35 0 216 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.bit_field) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 181.7008 cm -Q -q -1 0 0 1 40.01575 163.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (random_data) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (min_length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_length) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_mutations) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (25) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (step) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 151.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 145.7008 cm -Q -q -1 0 0 1 50.01575 127.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 115.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive value returning False on completion.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 103.7008 cm +1 0 0 1 60.01575 727.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Boolean @return: True on success, False otherwise.) Tj T* ET Q Q q -1 0 0 1 50.01575 97.70079 cm -Q -q -1 0 0 1 50.01575 79.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Calculate and return the total number of mutations for this individual primitive.) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (97) Tj T* ET -Q -Q - -endstream -endobj -1302 0 obj -<< -/Length 9176 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 60.01575 763.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of mutated forms this primitive can take) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (static) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 727.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q 1 0 0 1 50.01575 721.7008 cm Q q 1 0 0 1 50.01575 703.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q 1 0 0 1 60.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Do nothing.) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Calculate and return the total number of mutations for this individual primitive.) Tj T* ET Q Q q 1 0 0 1 60.01575 679.7008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: False @return: False) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of mutated forms this primitive can take) Tj T* ET Q Q q @@ -40230,140 +39822,26 @@ Q q 1 0 0 1 50.01575 655.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q 1 0 0 1 60.01575 643.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Return 0.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 631.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: 0 @return: 0) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 625.7008 cm -Q -q -1 0 0 1 40.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (string) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (- 1) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (padding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (encoding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('ascii') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (max_len) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 595.7008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzing.primitives.base_primitive) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_long_strings) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sequence) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 547.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Given a sequence, generate a number of selectively chosen strings lengths of the given sequence and add to) Tj T* (the string heuristic library.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 535.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@type sequence: String @param sequence: Sequence to repeat for creation of fuzz strings.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_library) Tj /F4 10 Tf ( = []) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 505.7008 cm -Q -q -1 0 0 1 50.01575 487.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (mutate) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 463.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Mutate the primitive by stepping through the fuzz library extended with the \223this\224 library, return False on) Tj T* (completion.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 451.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Boolean @return: True on success, False otherwise.) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 445.7008 cm -Q -q -1 0 0 1 50.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (num_mutations) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Calculate and return the total number of mutations for this individual primitive.) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 403.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (@rtype: Integer @return: Number of mutated forms this primitive can take) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 397.7008 cm -Q -q -1 0 0 1 50.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (render) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 367.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Render the primitive, encode the string according to the specified encoding.) Tj T* ET Q Q q -1 0 0 1 40.01575 361.7008 cm +1 0 0 1 40.01575 637.7008 cm Q q -1 0 0 1 40.01575 343.7008 cm +1 0 0 1 40.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (word) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (value) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (endian) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (') Tj (<) Tj (') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (format) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('binary') Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (signed) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (full_range) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (fuzzable) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (name) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 331.7008 cm +1 0 0 1 50.01575 607.7008 cm q .933333 1 .8 rg n 33.35 0 216 12 re f* @@ -40371,7 +39849,7 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.fuzzi Q Q q -1 0 0 1 40.01575 277.3008 cm +1 0 0 1 40.01575 553.3008 cm q 1 1 1 RG .3 w @@ -40383,13 +39861,13 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (CHIPSEC_MAIN Program Flow) Tj T* Q Q q -1 0 0 1 40.01575 265.3008 cm +1 0 0 1 40.01575 541.3008 cm Q q -1 0 0 1 40.01575 265.3008 cm +1 0 0 1 40.01575 541.3008 cm Q q -1 0 0 1 40.01575 235.3008 cm +1 0 0 1 40.01575 511.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40443,10 +39921,10 @@ Q Q Q q -1 0 0 1 40.01575 229.3008 cm +1 0 0 1 40.01575 505.3008 cm Q q -1 0 0 1 40.01575 217.3008 cm +1 0 0 1 40.01575 493.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40469,10 +39947,10 @@ Q Q Q q -1 0 0 1 40.01575 211.3008 cm +1 0 0 1 40.01575 487.3008 cm Q q -1 0 0 1 40.01575 199.3008 cm +1 0 0 1 40.01575 475.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40494,10 +39972,10 @@ Q Q Q q -1 0 0 1 40.01575 193.3008 cm +1 0 0 1 40.01575 469.3008 cm Q q -1 0 0 1 40.01575 181.3008 cm +1 0 0 1 40.01575 457.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40520,10 +39998,10 @@ Q Q Q q -1 0 0 1 40.01575 175.3008 cm +1 0 0 1 40.01575 451.3008 cm Q q -1 0 0 1 40.01575 163.3008 cm +1 0 0 1 40.01575 439.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40546,10 +40024,10 @@ Q Q Q q -1 0 0 1 40.01575 157.3008 cm +1 0 0 1 40.01575 433.3008 cm Q q -1 0 0 1 40.01575 145.3008 cm +1 0 0 1 40.01575 421.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40572,10 +40050,10 @@ Q Q Q q -1 0 0 1 40.01575 139.3008 cm +1 0 0 1 40.01575 415.3008 cm Q q -1 0 0 1 40.01575 127.3008 cm +1 0 0 1 40.01575 403.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40598,10 +40076,10 @@ Q Q Q q -1 0 0 1 40.01575 127.3008 cm +1 0 0 1 40.01575 403.3008 cm Q q -1 0 0 1 40.01575 72.90079 cm +1 0 0 1 40.01575 348.9008 cm q 1 1 1 RG .3 w @@ -40613,35 +40091,13 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (CHIPSEC_UTIL Program Flow) Tj T* Q Q q -1 0 0 1 40.01575 66.18898 cm +1 0 0 1 40.01575 336.9008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q +1 0 0 1 40.01575 336.9008 cm Q q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (98) Tj T* ET -Q -Q - -endstream -endobj -1303 0 obj -<< -/Length 7420 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 775.7008 cm -Q -q -1 0 0 1 40.01575 745.7008 cm +1 0 0 1 40.01575 306.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40695,10 +40151,10 @@ Q Q Q q -1 0 0 1 40.01575 739.7008 cm +1 0 0 1 40.01575 300.9008 cm Q q -1 0 0 1 40.01575 727.7008 cm +1 0 0 1 40.01575 288.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40721,10 +40177,10 @@ Q Q Q q -1 0 0 1 40.01575 721.7008 cm +1 0 0 1 40.01575 282.9008 cm Q q -1 0 0 1 40.01575 709.7008 cm +1 0 0 1 40.01575 270.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40746,10 +40202,10 @@ Q Q Q q -1 0 0 1 40.01575 703.7008 cm +1 0 0 1 40.01575 264.9008 cm Q q -1 0 0 1 40.01575 691.7008 cm +1 0 0 1 40.01575 252.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40772,10 +40228,10 @@ Q Q Q q -1 0 0 1 40.01575 685.7008 cm +1 0 0 1 40.01575 246.9008 cm Q q -1 0 0 1 40.01575 673.7008 cm +1 0 0 1 40.01575 234.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40798,10 +40254,10 @@ Q Q Q q -1 0 0 1 40.01575 667.7008 cm +1 0 0 1 40.01575 228.9008 cm Q q -1 0 0 1 40.01575 655.7008 cm +1 0 0 1 40.01575 216.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40824,10 +40280,10 @@ Q Q Q q -1 0 0 1 40.01575 655.7008 cm +1 0 0 1 40.01575 216.9008 cm Q q -1 0 0 1 40.01575 601.3008 cm +1 0 0 1 40.01575 162.5008 cm q 1 1 1 RG .3 w @@ -40839,10 +40295,10 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (Auxiliary components) Tj T* ET Q Q q -1 0 0 1 40.01575 589.3008 cm +1 0 0 1 40.01575 150.5008 cm Q q -1 0 0 1 40.01575 565.3008 cm +1 0 0 1 40.01575 126.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40892,10 +40348,10 @@ Q Q Q q -1 0 0 1 40.01575 565.3008 cm +1 0 0 1 40.01575 126.5008 cm Q q -1 0 0 1 40.01575 510.9008 cm +1 0 0 1 40.01575 72.10079 cm q 1 1 1 RG .3 w @@ -40907,10 +40363,32 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (Executable build scripts) Tj T* Q Q q -1 0 0 1 40.01575 498.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q Q q -1 0 0 1 40.01575 486.9008 cm +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (97) Tj T* ET +Q +Q + +endstream +endobj +1299 0 obj +<< +/Length 8153 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 769.7008 cm +Q +q +1 0 0 1 40.01575 757.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -40926,10 +40404,10 @@ Q Q Q q -1 0 0 1 40.01575 486.9008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 40.01575 430.1008 cm +1 0 0 1 40.01575 700.9008 cm q 1 1 1 RG .3 w @@ -40941,7 +40419,7 @@ BT 1 0 0 1 0 2.8 Tm 16.8 TL /F5 14 Tf 1 1 1 rg (CHIPSEC Modules) Tj T* ET Q Q q -1 0 0 1 40.01575 375.7008 cm +1 0 0 1 40.01575 646.5008 cm q 1 1 1 RG .3 w @@ -40953,10 +40431,10 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (Introduction) Tj T* ET Q Q q -1 0 0 1 40.01575 363.7008 cm +1 0 0 1 40.01575 634.5008 cm Q q -1 0 0 1 40.01575 261.7008 cm +1 0 0 1 40.01575 532.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -41055,61 +40533,39 @@ Q Q Q q -1 0 0 1 40.01575 261.7008 cm +1 0 0 1 40.01575 532.5008 cm Q q -1 0 0 1 40.01575 207.7008 cm +1 0 0 1 40.01575 478.5008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (A CHIPSEC module is just a python class that inherits from BaseModule and implements ) Tj /F3 10 Tf (is_supported) Tj /F1 10 Tf ( and ) Tj /F3 10 Tf (run) Tj /F1 10 Tf (.) Tj T* (Modules are stored under the chipsec installation directory in a subdirectory \223modules\224. The \223modules\224 directory) Tj T* (contains one subdirectory for each chipset that chipsec supports. There is also a directory for common modules that) Tj T* (should apply to every platform.) Tj T* ET Q Q q -1 0 0 1 40.01575 165.7008 cm +1 0 0 1 40.01575 436.5008 cm q BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (Internally the chipsec application uses the concept of a module name, which is a string of the form:) Tj T* /F3 10 Tf (common.bios_wp) Tj /F1 10 Tf (. This means module ) Tj /F3 10 Tf (common.bios_wp) Tj /F1 10 Tf ( is a python script called ) Tj /F3 10 Tf (bios_wp.py) Tj /F1 10 Tf ( that is stored at) Tj T* /F3 10 Tf (<) Tj (ROOT_DIR) Tj (>) Tj (\\chipsec\\modules\\common\\) Tj /F1 10 Tf (.) Tj T* ET Q Q q -1 0 0 1 40.01575 135.7008 cm +1 0 0 1 40.01575 406.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Modules can be mapped to one or more security vulnerabilities being checked. More information also found in the) Tj T* (documentation for any individual module.) Tj T* ET Q Q q -1 0 0 1 40.01575 117.7008 cm +1 0 0 1 40.01575 388.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Known vulnerabilities can be mapped to CHIPSEC modules as follows:) Tj T* ET Q Q q -1 0 0 1 40.01575 111.7008 cm +1 0 0 1 40.01575 382.5008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (99) Tj T* ET -Q -Q - -endstream -endobj -1304 0 obj -<< -/Length 9574 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 761.3008 cm +1 0 0 1 40.01575 328.1008 cm q 1 1 1 RG .3 w @@ -41122,7 +40578,7 @@ BT 1 0 0 1 0 2.4 Tm /F5 12 Tf 14.4 TL 107.922 0 Td (Attack Surface/Vector: Firmw Q Q q -1 0 0 1 40.01575 505.3008 cm +1 0 0 1 40.01575 72.10079 cm q 1 1 1 rg n 0 250 515.2441 -16 re f* @@ -41333,13 +40789,35 @@ Q Q Q q -1 0 0 1 40.01575 505.3008 cm +1 0 0 1 40.01575 72.10079 cm Q q -1 0 0 1 40.01575 499.3008 cm +1 0 0 1 40.01575 66.18898 cm Q q -1 0 0 1 40.01575 444.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (98) Tj T* ET +Q +Q + +endstream +endobj +1300 0 obj +<< +/Length 9513 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 761.3008 cm q 1 1 1 RG .3 w @@ -41352,7 +40830,7 @@ BT 1 0 0 1 0 2.4 Tm /F5 12 Tf 14.4 TL 104.94 0 Td (Attack Surface/Vector: Runtim Q Q q -1 0 0 1 40.01575 278.9008 cm +1 0 0 1 40.01575 595.3008 cm q 1 1 1 rg n 0 160 515.2441 -16 re f* @@ -41512,13 +40990,13 @@ Q Q Q q -1 0 0 1 40.01575 278.9008 cm +1 0 0 1 40.01575 595.3008 cm Q q -1 0 0 1 40.01575 272.9008 cm +1 0 0 1 40.01575 589.3008 cm Q q -1 0 0 1 40.01575 218.5008 cm +1 0 0 1 40.01575 534.9008 cm q 1 1 1 RG .3 w @@ -41530,22 +41008,28 @@ BT 1 0 0 1 0 2.4 Tm 11.91005 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vec Q Q q -1 0 0 1 40.01575 82.50079 cm +1 0 0 1 40.01575 332.9008 cm q 1 1 1 rg -n 0 130 515.2441 -16 re f* +n 0 196 515.2441 -16 re f* .878431 .878431 .878431 rg -n 0 114 515.2441 -30 re f* +n 0 180 515.2441 -30 re f* 1 1 1 rg -n 0 84 515.2441 -30 re f* +n 0 150 515.2441 -30 re f* .878431 .878431 .878431 rg -n 0 54 515.2441 -54 re f* +n 0 120 515.2441 -54 re f* +1 1 1 rg +n 0 66 515.2441 -18 re f* +.878431 .878431 .878431 rg +n 0 48 515.2441 -18 re f* +1 1 1 rg +n 0 30 515.2441 -30 re f* .960784 .960784 .862745 rg -n 0 130 515.2441 -16 re f* +n 0 196 515.2441 -16 re f* 0 .443137 .772549 rg BT /F2 10 Tf 10 TL ET q -1 0 0 1 6 117 cm +1 0 0 1 6 183 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41556,7 +41040,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 20.96902 0 Td (Vulnerability Description) Tj T Q Q q -1 0 0 1 177.748 117 cm +1 0 0 1 177.748 183 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41567,7 +41051,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 38.75902 0 Td (CHIPSEC Module) Tj T* -38.75902 Q Q q -1 0 0 1 349.4961 117 cm +1 0 0 1 349.4961 183 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41580,98 +41064,48 @@ Q 0 0 0 rg BT /F1 10 Tf 12 TL ET q -1 0 0 1 6 99 cm +1 0 0 1 6 165 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Root certificate) Tj T* ET Q Q q -1 0 0 1 177.748 87 cm +1 0 0 1 177.748 153 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.bios_wp,) Tj T* (common.secureboot.variables) Tj T* ET Q Q q -1 0 0 1 6 57 cm +1 0 0 1 6 123 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Key exchange keys and) Tj T* (whitelist/blacklist) Tj T* ET Q Q q -1 0 0 1 177.748 69 cm +1 0 0 1 177.748 135 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (common.secureboot.variables) Tj T* ET Q Q q -1 0 0 1 6 3 cm +1 0 0 1 6 69 cm q 0 0 0 rg BT 1 0 0 1 0 38 Tm /F1 10 Tf 12 TL (Controls in setup variable \(CSM) Tj T* (enable/disable, image verification) Tj T* (policies, secure boot) Tj T* (enable/disable, clear/restore keys\)) Tj T* ET Q Q q -1 0 0 1 177.748 39 cm +1 0 0 1 177.748 105 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (chipsec_util uefi var-find Setup) Tj T* ET Q Q q -1 J -1 j -0 0 0 RG -.25 w -n 0 0 m 515.2441 0 l S -n 0 114 m 515.2441 114 l S -n 0 84 m 515.2441 84 l S -n 0 54 m 515.2441 54 l S -n 171.748 0 m 171.748 130 l S -n 343.4961 0 m 343.4961 130 l S -n 0 130 m 515.2441 130 l S -n 0 0 m 0 130 l S -n 515.2441 0 m 515.2441 130 l S -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (100) Tj T* ET -Q -Q - -endstream -endobj -1305 0 obj -<< -/Length 9714 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 709.7008 cm -q -1 1 1 rg -n 0 66 515.2441 -18 re f* -.878431 .878431 .878431 rg -n 0 48 515.2441 -18 re f* -1 1 1 rg -n 0 30 515.2441 -30 re f* -0 0 0 rg -BT /F1 10 Tf 12 TL ET -q 1 0 0 1 6 51 cm q 0 0 0 rg @@ -41718,25 +41152,29 @@ q 1 j 0 0 0 RG .25 w +n 0 180 m 515.2441 180 l S +n 0 150 m 515.2441 150 l S +n 0 120 m 515.2441 120 l S n 0 66 m 515.2441 66 l S n 0 48 m 515.2441 48 l S n 0 30 m 515.2441 30 l S -n 171.748 0 m 171.748 66 l S -n 343.4961 0 m 343.4961 66 l S -n 0 0 m 0 66 l S -n 515.2441 0 m 515.2441 66 l S +n 171.748 0 m 171.748 196 l S +n 343.4961 0 m 343.4961 196 l S +n 0 196 m 515.2441 196 l S n 0 0 m 515.2441 0 l S +n 0 0 m 0 196 l S +n 515.2441 0 m 515.2441 196 l S Q Q Q q -1 0 0 1 40.01575 709.7008 cm +1 0 0 1 40.01575 332.9008 cm Q q -1 0 0 1 40.01575 703.7008 cm +1 0 0 1 40.01575 326.9008 cm Q q -1 0 0 1 40.01575 649.3008 cm +1 0 0 1 40.01575 272.5008 cm q 1 1 1 RG .3 w @@ -41748,34 +41186,26 @@ BT 1 0 0 1 0 2.4 Tm 95.91605 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vec Q Q q -1 0 0 1 40.01575 333.3008 cm +1 0 0 1 40.01575 76.50079 cm q 1 1 1 rg -n 0 310 515.2441 -16 re f* +n 0 190 515.2441 -16 re f* .878431 .878431 .878431 rg -n 0 294 515.2441 -30 re f* +n 0 174 515.2441 -30 re f* 1 1 1 rg -n 0 264 515.2441 -30 re f* +n 0 144 515.2441 -30 re f* .878431 .878431 .878431 rg -n 0 234 515.2441 -30 re f* +n 0 114 515.2441 -30 re f* 1 1 1 rg -n 0 204 515.2441 -42 re f* +n 0 84 515.2441 -42 re f* .878431 .878431 .878431 rg -n 0 162 515.2441 -42 re f* -1 1 1 rg -n 0 120 515.2441 -30 re f* -.878431 .878431 .878431 rg -n 0 90 515.2441 -30 re f* -1 1 1 rg -n 0 60 515.2441 -30 re f* -.878431 .878431 .878431 rg -n 0 30 515.2441 -30 re f* +n 0 42 515.2441 -42 re f* .960784 .960784 .862745 rg -n 0 310 515.2441 -16 re f* +n 0 190 515.2441 -16 re f* 0 .443137 .772549 rg BT /F2 10 Tf 10 TL ET q -1 0 0 1 6 297 cm +1 0 0 1 6 177 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41786,7 +41216,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 20.96902 0 Td (Vulnerability Description) Tj T Q Q q -1 0 0 1 177.748 297 cm +1 0 0 1 177.748 177 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41797,7 +41227,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 38.75902 0 Td (CHIPSEC Module) Tj T* -38.75902 Q Q q -1 0 0 1 349.4961 297 cm +1 0 0 1 349.4961 177 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -41810,76 +41240,130 @@ Q 0 0 0 rg BT /F1 10 Tf 12 TL ET q -1 0 0 1 6 267 cm +1 0 0 1 6 147 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Secure boot configuration is stored) Tj T* (in unprotected variable) Tj T* ET Q Q q -1 0 0 1 177.748 267 cm +1 0 0 1 177.748 147 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.secureboot.variables,) Tj T* (chipsec_util uefi var-list) Tj T* ET Q Q q -1 0 0 1 6 237 cm +1 0 0 1 6 117 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Variable permissions are not set) Tj T* (according to specification) Tj T* ET Q Q q -1 0 0 1 177.748 249 cm +1 0 0 1 177.748 129 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (common.uefi.access_uefispec) Tj T* ET Q Q q -1 0 0 1 6 207 cm +1 0 0 1 6 87 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Sensitive data \(like passwords\) are) Tj T* (stored in uefi variables) Tj T* ET Q Q q -1 0 0 1 177.748 207 cm +1 0 0 1 177.748 87 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (chipsec_util uefi var-list \(manual) Tj T* (analysis\)) Tj T* ET Q Q q -1 0 0 1 6 165 cm +1 0 0 1 6 45 cm q 0 0 0 rg BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (Firmware doesn\222t sanitize) Tj T* (pointers/addresses stored in) Tj T* (variables) Tj T* ET Q Q q -1 0 0 1 177.748 177 cm +1 0 0 1 177.748 57 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (chipsec_util uefi var-list \(manual) Tj T* (analysis\)) Tj T* ET Q Q q -1 0 0 1 6 135 cm +1 0 0 1 6 15 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Firmware hangs on invalid variable) Tj T* (content) Tj T* ET Q Q q -1 0 0 1 177.748 123 cm +1 0 0 1 177.748 3 cm q 0 0 0 rg BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (chipsec_util uefi var-write,) Tj T* (chipsec_util uefi var-delete \(manual) Tj T* (analysis\)) Tj T* ET Q Q q +1 J +1 j +0 0 0 RG +.25 w +n 0 0 m 515.2441 0 l S +n 0 174 m 515.2441 174 l S +n 0 144 m 515.2441 144 l S +n 0 114 m 515.2441 114 l S +n 0 84 m 515.2441 84 l S +n 0 42 m 515.2441 42 l S +n 171.748 0 m 171.748 190 l S +n 343.4961 0 m 343.4961 190 l S +n 0 190 m 515.2441 190 l S +n 0 0 m 0 190 l S +n 515.2441 0 m 515.2441 190 l S +Q +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (99) Tj T* ET +Q +Q + +endstream +endobj +1301 0 obj +<< +/Length 8928 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 655.7008 cm +q +1 1 1 rg +n 0 120 515.2441 -30 re f* +.878431 .878431 .878431 rg +n 0 90 515.2441 -30 re f* +1 1 1 rg +n 0 60 515.2441 -30 re f* +.878431 .878431 .878431 rg +n 0 30 515.2441 -30 re f* +0 0 0 rg +BT /F1 10 Tf 12 TL ET +q 1 0 0 1 6 93 cm q 0 0 0 rg @@ -41940,32 +41424,26 @@ q 1 j 0 0 0 RG .25 w -n 0 294 m 515.2441 294 l S -n 0 264 m 515.2441 264 l S -n 0 234 m 515.2441 234 l S -n 0 204 m 515.2441 204 l S -n 0 162 m 515.2441 162 l S n 0 120 m 515.2441 120 l S n 0 90 m 515.2441 90 l S n 0 60 m 515.2441 60 l S n 0 30 m 515.2441 30 l S -n 171.748 0 m 171.748 310 l S -n 343.4961 0 m 343.4961 310 l S -n 0 310 m 515.2441 310 l S +n 171.748 0 m 171.748 120 l S +n 343.4961 0 m 343.4961 120 l S +n 0 0 m 0 120 l S +n 515.2441 0 m 515.2441 120 l S n 0 0 m 515.2441 0 l S -n 0 0 m 0 310 l S -n 515.2441 0 m 515.2441 310 l S Q Q Q q -1 0 0 1 40.01575 333.3008 cm +1 0 0 1 40.01575 655.7008 cm Q q -1 0 0 1 40.01575 327.3008 cm +1 0 0 1 40.01575 649.7008 cm Q q -1 0 0 1 40.01575 272.9008 cm +1 0 0 1 40.01575 595.3008 cm q 1 1 1 RG .3 w @@ -41977,7 +41455,7 @@ BT 1 0 0 1 0 2.4 Tm 98.92205 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vec Q Q q -1 0 0 1 40.01575 148.9008 cm +1 0 0 1 40.01575 471.3008 cm q 1 1 1 rg n 0 118 515.2441 -16 re f* @@ -42120,13 +41598,13 @@ Q Q Q q -1 0 0 1 40.01575 148.9008 cm +1 0 0 1 40.01575 471.3008 cm Q q -1 0 0 1 40.01575 142.9008 cm +1 0 0 1 40.01575 465.3008 cm Q q -1 0 0 1 40.01575 88.50079 cm +1 0 0 1 40.01575 410.9008 cm q 1 1 1 RG .3 w @@ -42138,16 +41616,32 @@ BT 1 0 0 1 0 2.4 Tm 87.58205 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vec Q Q q -1 0 0 1 40.01575 66.50079 cm +1 0 0 1 40.01575 172.9008 cm q 1 1 1 rg -n 0 16 515.2441 -16 re f* +n 0 232 515.2441 -16 re f* +.878431 .878431 .878431 rg +n 0 216 515.2441 -42 re f* +1 1 1 rg +n 0 174 515.2441 -30 re f* +.878431 .878431 .878431 rg +n 0 144 515.2441 -18 re f* +1 1 1 rg +n 0 126 515.2441 -30 re f* +.878431 .878431 .878431 rg +n 0 96 515.2441 -30 re f* +1 1 1 rg +n 0 66 515.2441 -18 re f* +.878431 .878431 .878431 rg +n 0 48 515.2441 -30 re f* +1 1 1 rg +n 0 18 515.2441 -18 re f* .960784 .960784 .862745 rg -n 0 16 515.2441 -16 re f* +n 0 232 515.2441 -16 re f* 0 .443137 .772549 rg BT /F2 10 Tf 10 TL ET q -1 0 0 1 6 3 cm +1 0 0 1 6 219 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42158,7 +41652,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 20.96902 0 Td (Vulnerability Description) Tj T Q Q q -1 0 0 1 177.748 3 cm +1 0 0 1 177.748 219 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42169,7 +41663,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 38.75902 0 Td (CHIPSEC Module) Tj T* -38.75902 Q Q q -1 0 0 1 349.4961 3 cm +1 0 0 1 349.4961 219 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42179,61 +41673,6 @@ q BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 59.30902 0 Td (Example) Tj T* -59.30902 0 Td ET Q Q -q -1 J -1 j -0 0 0 RG -.25 w -n 0 0 m 515.2441 0 l S -n 171.748 0 m 171.748 16 l S -n 343.4961 0 m 343.4961 16 l S -n 0 16 m 515.2441 16 l S -n 0 0 m 0 16 l S -n 515.2441 0 m 515.2441 16 l S -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (101) Tj T* ET -Q -Q - -endstream -endobj -1306 0 obj -<< -/Length 7964 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 559.7008 cm -q -1 1 1 rg -n 0 216 515.2441 -42 re f* -.878431 .878431 .878431 rg -n 0 174 515.2441 -30 re f* -1 1 1 rg -n 0 144 515.2441 -18 re f* -.878431 .878431 .878431 rg -n 0 126 515.2441 -30 re f* -1 1 1 rg -n 0 96 515.2441 -30 re f* -.878431 .878431 .878431 rg -n 0 66 515.2441 -18 re f* -1 1 1 rg -n 0 48 515.2441 -30 re f* -.878431 .878431 .878431 rg -n 0 18 515.2441 -18 re f* 0 0 0 rg BT /F1 10 Tf 12 TL ET q @@ -42326,22 +41765,23 @@ n 0 96 m 515.2441 96 l S n 0 66 m 515.2441 66 l S n 0 48 m 515.2441 48 l S n 0 18 m 515.2441 18 l S -n 171.748 0 m 171.748 216 l S -n 343.4961 0 m 343.4961 216 l S -n 0 0 m 0 216 l S -n 515.2441 0 m 515.2441 216 l S +n 171.748 0 m 171.748 232 l S +n 343.4961 0 m 343.4961 232 l S +n 0 232 m 515.2441 232 l S n 0 0 m 515.2441 0 l S +n 0 0 m 0 232 l S +n 515.2441 0 m 515.2441 232 l S Q Q Q q -1 0 0 1 40.01575 559.7008 cm +1 0 0 1 40.01575 172.9008 cm Q q -1 0 0 1 40.01575 553.7008 cm +1 0 0 1 40.01575 166.9008 cm Q q -1 0 0 1 40.01575 499.3008 cm +1 0 0 1 40.01575 112.5008 cm q 1 1 1 RG .3 w @@ -42353,26 +41793,16 @@ BT 1 0 0 1 0 2.4 Tm 137.262 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vect Q Q q -1 0 0 1 40.01575 315.3008 cm +1 0 0 1 40.01575 90.50079 cm q 1 1 1 rg -n 0 178 515.2441 -16 re f* -.878431 .878431 .878431 rg -n 0 162 515.2441 -42 re f* -1 1 1 rg -n 0 120 515.2441 -42 re f* -.878431 .878431 .878431 rg -n 0 78 515.2441 -30 re f* -1 1 1 rg -n 0 48 515.2441 -18 re f* -.878431 .878431 .878431 rg -n 0 30 515.2441 -30 re f* +n 0 16 515.2441 -16 re f* .960784 .960784 .862745 rg -n 0 178 515.2441 -16 re f* +n 0 16 515.2441 -16 re f* 0 .443137 .772549 rg BT /F2 10 Tf 10 TL ET q -1 0 0 1 6 165 cm +1 0 0 1 6 3 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42383,7 +41813,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 20.96902 0 Td (Vulnerability Description) Tj T Q Q q -1 0 0 1 177.748 165 cm +1 0 0 1 177.748 3 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42394,7 +41824,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 38.75902 0 Td (CHIPSEC Module) Tj T* -38.75902 Q Q q -1 0 0 1 349.4961 165 cm +1 0 0 1 349.4961 3 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42404,6 +41834,55 @@ q BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 59.30902 0 Td (Example) Tj T* -59.30902 0 Td ET Q Q +q +1 J +1 j +0 0 0 RG +.25 w +n 0 0 m 515.2441 0 l S +n 171.748 0 m 171.748 16 l S +n 343.4961 0 m 343.4961 16 l S +n 0 16 m 515.2441 16 l S +n 0 0 m 0 16 l S +n 515.2441 0 m 515.2441 16 l S +Q +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (100) Tj T* ET +Q +Q + +endstream +endobj +1302 0 obj +<< +/Length 7583 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 613.7008 cm +q +1 1 1 rg +n 0 162 515.2441 -42 re f* +.878431 .878431 .878431 rg +n 0 120 515.2441 -42 re f* +1 1 1 rg +n 0 78 515.2441 -30 re f* +.878431 .878431 .878431 rg +n 0 48 515.2441 -18 re f* +1 1 1 rg +n 0 30 515.2441 -30 re f* 0 0 0 rg BT /F1 10 Tf 12 TL ET q @@ -42465,23 +41944,22 @@ n 0 120 m 515.2441 120 l S n 0 78 m 515.2441 78 l S n 0 48 m 515.2441 48 l S n 0 30 m 515.2441 30 l S -n 171.748 0 m 171.748 178 l S -n 343.4961 0 m 343.4961 178 l S -n 0 178 m 515.2441 178 l S +n 171.748 0 m 171.748 162 l S +n 343.4961 0 m 343.4961 162 l S +n 0 0 m 0 162 l S +n 515.2441 0 m 515.2441 162 l S n 0 0 m 515.2441 0 l S -n 0 0 m 0 178 l S -n 515.2441 0 m 515.2441 178 l S Q Q Q q -1 0 0 1 40.01575 315.3008 cm +1 0 0 1 40.01575 613.7008 cm Q q -1 0 0 1 40.01575 309.3008 cm +1 0 0 1 40.01575 607.7008 cm Q q -1 0 0 1 40.01575 254.9008 cm +1 0 0 1 40.01575 553.3008 cm q 1 1 1 RG .3 w @@ -42493,14 +41971,18 @@ BT 1 0 0 1 0 2.4 Tm 56.23205 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vec Q Q q -1 0 0 1 40.01575 70.90079 cm +1 0 0 1 40.01575 309.3008 cm q 1 1 1 rg -n 0 178 515.2441 -16 re f* +n 0 238 515.2441 -16 re f* .878431 .878431 .878431 rg -n 0 162 515.2441 -30 re f* +n 0 222 515.2441 -30 re f* 1 1 1 rg -n 0 132 515.2441 -42 re f* +n 0 192 515.2441 -42 re f* +.878431 .878431 .878431 rg +n 0 150 515.2441 -30 re f* +1 1 1 rg +n 0 120 515.2441 -30 re f* .878431 .878431 .878431 rg n 0 90 515.2441 -30 re f* 1 1 1 rg @@ -42508,11 +41990,11 @@ n 0 60 515.2441 -30 re f* .878431 .878431 .878431 rg n 0 30 515.2441 -30 re f* .960784 .960784 .862745 rg -n 0 178 515.2441 -16 re f* +n 0 238 515.2441 -16 re f* 0 .443137 .772549 rg BT /F2 10 Tf 10 TL ET q -1 0 0 1 6 165 cm +1 0 0 1 6 225 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42523,7 +42005,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 20.96902 0 Td (Vulnerability Description) Tj T Q Q q -1 0 0 1 177.748 165 cm +1 0 0 1 177.748 225 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42534,7 +42016,7 @@ BT 1 0 0 1 0 0 Tm /F2 10 Tf 10 TL 38.75902 0 Td (CHIPSEC Module) Tj T* -38.75902 Q Q q -1 0 0 1 349.4961 165 cm +1 0 0 1 349.4961 225 cm q .960784 .960784 .862745 rg n 0 0 159.748 10 re f* @@ -42547,28 +42029,49 @@ Q 0 0 0 rg BT /F1 10 Tf 12 TL ET q -1 0 0 1 6 135 cm +1 0 0 1 6 195 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Insufficient protection of S3 boot) Tj T* (script table) Tj T* ET Q Q q -1 0 0 1 177.748 135 cm +1 0 0 1 177.748 195 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.uefi.s3bootscript,) Tj T* (tools.uefi.s3script_modify) Tj T* ET Q Q q -1 0 0 1 6 93 cm +1 0 0 1 6 153 cm q 0 0 0 rg BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (Dispatch opcodes in S3 boot script) Tj T* (call functions in unprotected) Tj T* (memory) Tj T* ET Q Q q -1 0 0 1 177.748 105 cm +1 0 0 1 177.748 165 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.uefi.s3bootscript,) Tj T* (tools.uefi.s3script_modify) Tj T* ET +Q +Q +q +1 0 0 1 6 123 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (S3 boot script interpreter stored in) Tj T* (unprotected memory) Tj T* ET +Q +Q +q +1 0 0 1 6 93 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Pointer to S3 boot script table in) Tj T* (unprotected UEFI variable) Tj T* ET +Q +Q +q +1 0 0 1 177.748 93 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.uefi.s3bootscript,) Tj T* (tools.uefi.s3script_modify) Tj T* ET @@ -42578,88 +42081,17 @@ q 1 0 0 1 6 63 cm q 0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (S3 boot script interpreter stored in) Tj T* (unprotected memory) Tj T* ET -Q -Q -q -1 0 0 1 6 33 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Pointer to S3 boot script table in) Tj T* (unprotected UEFI variable) Tj T* ET -Q -Q -q -1 0 0 1 177.748 33 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (common.uefi.s3bootscript,) Tj T* (tools.uefi.s3script_modify) Tj T* ET -Q -Q -q -1 0 0 1 6 3 cm -q -0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Critical setting not recorded in S3) Tj T* (boot script table) Tj T* ET Q Q q -1 0 0 1 177.748 3 cm +1 0 0 1 177.748 63 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (chipsec_util uefi s3bootscript) Tj T* (\(manual analysis\)) Tj T* ET Q Q q -1 J -1 j -0 0 0 RG -.25 w -n 0 0 m 515.2441 0 l S -n 0 162 m 515.2441 162 l S -n 0 132 m 515.2441 132 l S -n 0 90 m 515.2441 90 l S -n 0 60 m 515.2441 60 l S -n 0 30 m 515.2441 30 l S -n 171.748 0 m 171.748 178 l S -n 343.4961 0 m 343.4961 178 l S -n 0 178 m 515.2441 178 l S -n 0 0 m 0 178 l S -n 515.2441 0 m 515.2441 178 l S -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (102) Tj T* ET -Q -Q - -endstream -endobj -1307 0 obj -<< -/Length 6742 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 715.7008 cm -q -1 1 1 rg -n 0 60 515.2441 -30 re f* -.878431 .878431 .878431 rg -n 0 30 515.2441 -30 re f* -0 0 0 rg -BT /F1 10 Tf 12 TL ET -q 1 0 0 1 6 33 cm q 0 0 0 rg @@ -42692,24 +42124,30 @@ q 1 j 0 0 0 RG .25 w +n 0 222 m 515.2441 222 l S +n 0 192 m 515.2441 192 l S +n 0 150 m 515.2441 150 l S +n 0 120 m 515.2441 120 l S +n 0 90 m 515.2441 90 l S n 0 60 m 515.2441 60 l S n 0 30 m 515.2441 30 l S -n 171.748 0 m 171.748 60 l S -n 343.4961 0 m 343.4961 60 l S -n 0 0 m 0 60 l S -n 515.2441 0 m 515.2441 60 l S +n 171.748 0 m 171.748 238 l S +n 343.4961 0 m 343.4961 238 l S +n 0 238 m 515.2441 238 l S n 0 0 m 515.2441 0 l S +n 0 0 m 0 238 l S +n 515.2441 0 m 515.2441 238 l S Q Q Q q -1 0 0 1 40.01575 715.7008 cm +1 0 0 1 40.01575 309.3008 cm Q q -1 0 0 1 40.01575 709.7008 cm +1 0 0 1 40.01575 303.3008 cm Q q -1 0 0 1 40.01575 655.3008 cm +1 0 0 1 40.01575 248.9008 cm q 1 1 1 RG .3 w @@ -42721,7 +42159,7 @@ BT 1 0 0 1 0 2.4 Tm 143.592 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vect Q Q q -1 0 0 1 40.01575 525.3008 cm +1 0 0 1 40.01575 118.9008 cm q 1 1 1 rg n 0 124 515.2441 -16 re f* @@ -42819,13 +42257,35 @@ Q Q Q q -1 0 0 1 40.01575 525.3008 cm +1 0 0 1 40.01575 118.9008 cm Q q -1 0 0 1 40.01575 519.3008 cm +1 0 0 1 40.01575 112.9008 cm Q q -1 0 0 1 40.01575 464.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (101) Tj T* ET +Q +Q + +endstream +endobj +1303 0 obj +<< +/Length 5901 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 761.3008 cm q 1 1 1 RG .3 w @@ -42837,7 +42297,7 @@ BT 1 0 0 1 0 2.4 Tm 137.922 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vect Q Q q -1 0 0 1 40.01575 370.9008 cm +1 0 0 1 40.01575 667.3008 cm q 1 1 1 rg n 0 88 515.2441 -16 re f* @@ -42915,13 +42375,13 @@ Q Q Q q -1 0 0 1 40.01575 370.9008 cm +1 0 0 1 40.01575 667.3008 cm Q q -1 0 0 1 40.01575 364.9008 cm +1 0 0 1 40.01575 661.3008 cm Q q -1 0 0 1 40.01575 310.5008 cm +1 0 0 1 40.01575 606.9008 cm q 1 1 1 RG .3 w @@ -42933,7 +42393,7 @@ BT 1 0 0 1 0 2.4 Tm 178.266 0 Td 14.4 TL /F5 12 Tf 1 1 1 rg (Attack Surface/Vect Q Q q -1 0 0 1 40.01575 228.5008 cm +1 0 0 1 40.01575 524.9008 cm q 1 1 1 rg n 0 76 515.2441 -16 re f* @@ -43018,32 +42478,10 @@ Q Q Q q -1 0 0 1 40.01575 228.5008 cm +1 0 0 1 40.01575 524.9008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (103) Tj T* ET -Q -Q - -endstream -endobj -1308 0 obj -<< -/Length 4137 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 761.3008 cm +1 0 0 1 40.01575 470.5008 cm q 1 1 1 RG .3 w @@ -43055,7 +42493,7 @@ BT 1 0 0 1 0 2.4 Tm 14.4 TL /F5 12 Tf 1 1 1 rg (Modules) Tj T* ET Q Q q -1 0 0 1 40.01575 709.3008 cm +1 0 0 1 40.01575 418.5008 cm q 1 1 1 RG .3 w @@ -43067,7 +42505,7 @@ BT 1 0 0 1 0 2 Tm 12 TL /F5 10 Tf 1 1 1 rg (modules package) Tj T* ET Q Q q -1 0 0 1 40.01575 659.7008 cm +1 0 0 1 40.01575 368.9008 cm q 1 1 1 RG .3 w @@ -43079,7 +42517,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bdw package) Tj T* ET Q Q q -1 0 0 1 40.01575 610.1008 cm +1 0 0 1 40.01575 319.3008 cm q 1 1 1 RG .3 w @@ -43091,7 +42529,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (byt package) Tj T* ET Q Q q -1 0 0 1 40.01575 560.5008 cm +1 0 0 1 40.01575 269.7008 cm q 1 1 1 RG .3 w @@ -43103,7 +42541,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (common package) Tj T* ET Q Q q -1 0 0 1 40.01575 510.9008 cm +1 0 0 1 40.01575 220.1008 cm q 1 1 1 RG .3 w @@ -43115,7 +42553,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpu package) Tj T* ET Q Q q -1 0 0 1 40.01575 461.3008 cm +1 0 0 1 40.01575 170.5008 cm q 1 1 1 RG .3 w @@ -43127,22 +42565,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpu_info module) Tj T* ET Q Q q -1 0 0 1 40.01575 443.3008 cm +1 0 0 1 40.01575 152.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Displays CPU information) Tj T* ET Q Q q -1 0 0 1 40.01575 437.3008 cm +1 0 0 1 40.01575 146.5008 cm Q q -1 0 0 1 40.01575 419.3008 cm +1 0 0 1 40.01575 128.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (cpu_info) Tj T* ET Q Q q -1 0 0 1 50.01575 407.3008 cm +1 0 0 1 50.01575 116.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -43150,96 +42588,22 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 401.3008 cm +1 0 0 1 50.01575 110.5008 cm Q q -1 0 0 1 50.01575 383.3008 cm +1 0 0 1 50.01575 92.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 359.3008 cm +1 0 0 1 60.01575 68.50079 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 353.3008 cm -Q -q -1 0 0 1 50.01575 335.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 285.7008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ia_untrusted module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 267.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (IA Untrusted checks) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 261.7008 cm -Q -q -1 0 0 1 40.01575 243.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ia_untrusted) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 231.7008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 225.7008 cm -Q -q -1 0 0 1 50.01575 207.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_untrusted) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 201.7008 cm -Q -q -1 0 0 1 50.01575 183.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 159.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 153.7008 cm -Q -q -1 0 0 1 50.01575 135.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q +1 0 0 1 50.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -43251,20 +42615,94 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (104) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (102) Tj T* ET Q Q endstream endobj -1309 0 obj +1304 0 obj << -/Length 7683 +/Length 6586 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 766.1008 cm +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 714.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ia_untrusted module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 696.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (IA Untrusted checks) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 690.1008 cm +Q +q +1 0 0 1 40.01575 672.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ia_untrusted) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 660.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 654.1008 cm +Q +q +1 0 0 1 50.01575 636.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_untrusted) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 630.1008 cm +Q +q +1 0 0 1 50.01575 612.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 588.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 582.1008 cm +Q +q +1 0 0 1 50.01575 564.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 514.5008 cm q 1 1 1 RG .3 w @@ -43276,26 +42714,26 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spectre_v2 module) Tj T* ET Q Q q -1 0 0 1 40.01575 724.1008 cm +1 0 0 1 40.01575 472.5008 cm q BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module checks if system includes hardware mitigations for Speculative Execution Side Channel. Specifically, it) Tj T* (verifies that the system supports CPU mitigations for Branch Target Injection vulnerability a.k.a. Spectre Variant 2) Tj T* (\(CVE-2017-5715\)) Tj T* ET Q Q q -1 0 0 1 40.01575 706.1008 cm +1 0 0 1 40.01575 454.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The module checks if the following hardware mitigations are supported by the CPU and enabled by the OS/software:) Tj T* ET Q Q q -1 0 0 1 40.01575 700.1008 cm +1 0 0 1 40.01575 448.5008 cm Q q -1 0 0 1 40.01575 700.1008 cm +1 0 0 1 40.01575 448.5008 cm Q q -1 0 0 1 40.01575 676.1008 cm +1 0 0 1 40.01575 424.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43318,10 +42756,10 @@ Q Q Q q -1 0 0 1 40.01575 670.1008 cm +1 0 0 1 40.01575 418.5008 cm Q q -1 0 0 1 40.01575 646.1008 cm +1 0 0 1 40.01575 394.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43344,10 +42782,10 @@ Q Q Q q -1 0 0 1 40.01575 640.1008 cm +1 0 0 1 40.01575 388.5008 cm Q q -1 0 0 1 40.01575 616.1008 cm +1 0 0 1 40.01575 364.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43370,10 +42808,10 @@ Q Q Q q -1 0 0 1 40.01575 610.1008 cm +1 0 0 1 40.01575 358.5008 cm Q q -1 0 0 1 40.01575 586.1008 cm +1 0 0 1 40.01575 334.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43396,31 +42834,31 @@ Q Q Q q -1 0 0 1 40.01575 586.1008 cm +1 0 0 1 40.01575 334.5008 cm Q q -1 0 0 1 40.01575 556.1008 cm +1 0 0 1 40.01575 304.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (In addition to checking if CPU supports and OS enables all mitigations, we need to check that relevant MSR bits are) Tj T* (set consistently on all logical processors \(CPU threads\).) Tj T* ET Q Q q -1 0 0 1 40.01575 538.1008 cm +1 0 0 1 40.01575 286.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The module returns the following results:) Tj T* ET Q Q q -1 0 0 1 40.01575 522.1008 cm +1 0 0 1 40.01575 270.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (FAILED:) Tj T* ET Q Q q -1 0 0 1 40.01575 507.1008 cm +1 0 0 1 40.01575 255.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43437,14 +42875,14 @@ Q Q Q q -1 0 0 1 40.01575 491.1008 cm +1 0 0 1 40.01575 239.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (WARNING:) Tj T* ET Q Q q -1 0 0 1 40.01575 458.1008 cm +1 0 0 1 40.01575 206.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43468,14 +42906,14 @@ Q Q Q q -1 0 0 1 40.01575 442.1008 cm +1 0 0 1 40.01575 190.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (WARNING:) Tj T* ET Q Q q -1 0 0 1 40.01575 391.1008 cm +1 0 0 1 40.01575 139.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43506,14 +42944,14 @@ Q Q Q q -1 0 0 1 40.01575 375.1008 cm +1 0 0 1 40.01575 123.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (WARNING:) Tj T* ET Q Q q -1 0 0 1 40.01575 342.1008 cm +1 0 0 1 40.01575 90.50079 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43537,14 +42975,36 @@ Q Q Q q -1 0 0 1 40.01575 326.1008 cm +1 0 0 1 40.01575 74.50079 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (PASSED:) Tj T* ET Q Q q -1 0 0 1 40.01575 257.1008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (103) Tj T* ET +Q +Q + +endstream +endobj +1305 0 obj +<< +/Length 9451 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 706.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43582,20 +43042,20 @@ Q Q Q q -1 0 0 1 40.01575 239.1008 cm +1 0 0 1 40.01575 688.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Notes:) Tj T* ET Q Q q -1 0 0 1 40.01575 233.1008 cm +1 0 0 1 40.01575 682.7008 cm Q q -1 0 0 1 40.01575 233.1008 cm +1 0 0 1 40.01575 682.7008 cm Q q -1 0 0 1 40.01575 209.1008 cm +1 0 0 1 40.01575 658.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43618,10 +43078,10 @@ Q Q Q q -1 0 0 1 40.01575 203.1008 cm +1 0 0 1 40.01575 652.7008 cm Q q -1 0 0 1 40.01575 167.1008 cm +1 0 0 1 40.01575 616.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43644,10 +43104,10 @@ Q Q Q q -1 0 0 1 40.01575 161.1008 cm +1 0 0 1 40.01575 610.7008 cm Q q -1 0 0 1 40.01575 113.1008 cm +1 0 0 1 40.01575 562.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43670,10 +43130,10 @@ Q Q Q q -1 0 0 1 40.01575 107.1008 cm +1 0 0 1 40.01575 556.7008 cm Q q -1 0 0 1 40.01575 83.10079 cm +1 0 0 1 40.01575 532.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43696,52 +43156,30 @@ Q Q Q q -1 0 0 1 40.01575 83.10079 cm +1 0 0 1 40.01575 532.7008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (105) Tj T* ET -Q -Q - -endstream -endobj -1310 0 obj -<< -/Length 8647 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 751.7008 cm +1 0 0 1 40.01575 502.7008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (@TODO: we should verify CPUID.07H:EDX on all logical CPUs as well because it may differ if ucode update wasn\222t) Tj T* (loaded on all CPU cores) Tj T* ET Q Q q -1 0 0 1 40.01575 733.7008 cm +1 0 0 1 40.01575 484.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used:) Tj T* ET Q Q q -1 0 0 1 40.01575 727.7008 cm +1 0 0 1 40.01575 478.7008 cm Q q -1 0 0 1 40.01575 727.7008 cm +1 0 0 1 40.01575 478.7008 cm Q q -1 0 0 1 40.01575 715.7008 cm +1 0 0 1 40.01575 466.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43764,10 +43202,10 @@ Q Q Q q -1 0 0 1 40.01575 709.7008 cm +1 0 0 1 40.01575 460.7008 cm Q q -1 0 0 1 40.01575 697.7008 cm +1 0 0 1 40.01575 448.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43790,10 +43228,10 @@ Q Q Q q -1 0 0 1 40.01575 691.7008 cm +1 0 0 1 40.01575 442.7008 cm Q q -1 0 0 1 40.01575 679.7008 cm +1 0 0 1 40.01575 430.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43816,10 +43254,10 @@ Q Q Q q -1 0 0 1 40.01575 673.7008 cm +1 0 0 1 40.01575 424.7008 cm Q q -1 0 0 1 40.01575 661.7008 cm +1 0 0 1 40.01575 412.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43842,10 +43280,10 @@ Q Q Q q -1 0 0 1 40.01575 655.7008 cm +1 0 0 1 40.01575 406.7008 cm Q q -1 0 0 1 40.01575 643.7008 cm +1 0 0 1 40.01575 394.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43868,10 +43306,10 @@ Q Q Q q -1 0 0 1 40.01575 637.7008 cm +1 0 0 1 40.01575 388.7008 cm Q q -1 0 0 1 40.01575 625.7008 cm +1 0 0 1 40.01575 376.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43894,10 +43332,10 @@ Q Q Q q -1 0 0 1 40.01575 619.7008 cm +1 0 0 1 40.01575 370.7008 cm Q q -1 0 0 1 40.01575 607.7008 cm +1 0 0 1 40.01575 358.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43920,23 +43358,23 @@ Q Q Q q -1 0 0 1 40.01575 607.7008 cm +1 0 0 1 40.01575 358.7008 cm Q q -1 0 0 1 40.01575 589.7008 cm +1 0 0 1 40.01575 340.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET Q Q q -1 0 0 1 40.01575 583.7008 cm +1 0 0 1 40.01575 334.7008 cm Q q -1 0 0 1 40.01575 583.7008 cm +1 0 0 1 40.01575 334.7008 cm Q q -1 0 0 1 40.01575 559.7008 cm +1 0 0 1 40.01575 310.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43958,10 +43396,10 @@ Q Q Q q -1 0 0 1 40.01575 553.7008 cm +1 0 0 1 40.01575 304.7008 cm Q q -1 0 0 1 40.01575 541.7008 cm +1 0 0 1 40.01575 292.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -43983,10 +43421,10 @@ Q Q Q q -1 0 0 1 40.01575 535.7008 cm +1 0 0 1 40.01575 286.7008 cm Q q -1 0 0 1 40.01575 523.7008 cm +1 0 0 1 40.01575 274.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -44008,10 +43446,10 @@ Q Q Q q -1 0 0 1 40.01575 517.7008 cm +1 0 0 1 40.01575 268.7008 cm Q q -1 0 0 1 21.5778 493.7008 cm +1 0 0 1 21.5778 244.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -44033,10 +43471,10 @@ Q Q Q q -1 0 0 1 40.01575 487.7008 cm +1 0 0 1 40.01575 238.7008 cm Q q -1 0 0 1 40.01575 463.7008 cm +1 0 0 1 40.01575 214.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -44058,19 +43496,19 @@ Q Q Q q -1 0 0 1 40.01575 463.7008 cm +1 0 0 1 40.01575 214.7008 cm Q q -1 0 0 1 40.01575 457.7008 cm +1 0 0 1 40.01575 208.7008 cm Q q -1 0 0 1 40.01575 439.7008 cm +1 0 0 1 40.01575 190.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spectre_v2) Tj T* ET Q Q q -1 0 0 1 50.01575 427.7008 cm +1 0 0 1 50.01575 178.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -44078,649 +43516,34 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 421.7008 cm +1 0 0 1 50.01575 172.7008 cm Q q -1 0 0 1 50.01575 403.7008 cm +1 0 0 1 50.01575 154.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_spectre_mitigations) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 397.7008 cm +1 0 0 1 50.01575 148.7008 cm Q q -1 0 0 1 50.01575 379.7008 cm +1 0 0 1 50.01575 130.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 355.7008 cm +1 0 0 1 60.01575 106.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 349.7008 cm +1 0 0 1 50.01575 100.7008 cm Q q -1 0 0 1 50.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 282.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (secureboot package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 232.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (variables module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 214.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (UEFI 2.4 spec Section 28) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 184.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Verify that all Secure Boot key UEFI variables are authenticated \(BS+RT+AT\) and protected from unauthorized) Tj T* (modification.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 166.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Use \221-a modify\222 option for the module to also try to write/corrupt the variables.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 160.5008 cm -Q -q -1 0 0 1 40.01575 142.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (variables) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 130.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 124.5008 cm -Q -q -1 0 0 1 50.01575 106.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (can_modify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -Q -q -1 0 0 1 50.01575 82.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_secureboot_variable_attributes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 76.50079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (106) Tj T* ET -Q -Q - -endstream -endobj -1311 0 obj -<< -/Length 6589 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 739.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 666.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 616.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (access_uefispec module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 598.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks protection of UEFI variables defined in the UEFI spec to have certain permissions.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 580.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns failure if variable attributes are not as defined in ) Tj 0 0 .501961 rg (table 11 \223Global Variables\224) Tj 0 0 0 rg ( of the UEFI spec.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 574.5008 cm -Q -q -1 0 0 1 40.01575 556.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (access_uefispec) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 544.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 538.5008 cm -Q -q -1 0 0 1 50.01575 520.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (can_modify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 514.5008 cm -Q -q -1 0 0 1 50.01575 496.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_vars) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 490.5008 cm -Q -q -1 0 0 1 50.01575 472.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (diff_var) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (data1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data2) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 466.5008 cm -Q -q -1 0 0 1 50.01575 448.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 424.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 418.5008 cm -Q -q -1 0 0 1 50.01575 400.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 350.9008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (s3bootscript module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 332.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks protections of the S3 resume boot-script implemented by the UEFI based firmware) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 314.9008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 296.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (VU#976132 UEFI implementations do not properly secure the EFI S3 Resume Boot Path boot script) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 278.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Technical Details of the S3 Resume Boot Script Vulnerability) Tj 0 0 0 rg ( by Intel Security\222s Advanced Threat Research team.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 260.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Attacks on UEFI Security) Tj 0 0 0 rg ( by Rafal Wojtczuk and Corey Kallenberg.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 242.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Attacking UEFI Boot Script) Tj 0 0 0 rg ( by Rafal Wojtczuk and Corey Kallenberg.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 224.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Exploiting UEFI boot script table vulnerability) Tj 0 0 0 rg ( by Dmytro Oleksiuk.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 206.9008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 190.5008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.s3bootscript [-a ) Tj (<) Tj (script_address) Tj (>) Tj (]) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 170.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 144.5008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 25.2 re B* -Q -q -BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.s3bootscript) Tj T* (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.s3bootscript -a 0x00000000BDE10000) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 130.5008 cm -Q -q -1 0 0 1 40.01575 112.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (s3bootscript) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 94.50079 cm -Q -q -1 0 0 1 50.01575 76.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_dispatch_opcodes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bootscript_entries) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 70.50079 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (107) Tj T* ET -Q -Q - -endstream -endobj -1312 0 obj -<< -/Length 6270 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_s3_bootscript) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bootscript_pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_s3_bootscripts) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bsaddress) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_inside_SMRAM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_inside_SPI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 685.7008 cm -Q -q -1 0 0 1 50.01575 667.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 643.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 637.7008 cm -Q -q -1 0 0 1 50.01575 619.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 570.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_kbrd_buffer module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 540.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (DEFCON 16: ) Tj 0 0 .501961 rg (Bypassing Pre-boot Authentication Passwords by Instrumenting the BIOS Keyboard Buffer) Tj 0 0 0 rg ( by) Tj T* (Jonathan Brossard) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 522.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Checks for BIOS/HDD password exposure through BIOS keyboard buffer.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 504.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Checks for exposure of pre-boot passwords \(BIOS/HDD/pre-bot authentication SW\) in the BIOS keyboard buffer.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 498.1008 cm -Q -q -1 0 0 1 40.01575 480.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_kbrd_buffer) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 468.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 462.1008 cm -Q -q -1 0 0 1 50.01575 444.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_BIOS_keyboard_buffer) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 438.1008 cm -Q -q -1 0 0 1 50.01575 420.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 396.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 390.1008 cm -Q -q -1 0 0 1 50.01575 372.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 322.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_smi module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 292.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module checks that SMI events configuration is locked down - Global SMI Enable/SMI Lock - TCO SMI) Tj T* (Enable/TCO Lock) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 274.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 256.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Setup for Failure: Defeating SecureBoot) Tj 0 0 0 rg ( by Corey Kallenberg, Xeno Kovah, John Butterworth, Sam Cornwell) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 214.5008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (Summary of Attacks Against BIOS and Secure Boot) Tj /F1 10 Tf ( \() Tj 0 0 .501961 rg (https://www.defcon.org/images/defcon-22/dc-22-presentations/) Tj 0 0 0 rg T* 0 0 .501961 rg (Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against) Tj T* (-BIOS-UPDATED.pdf) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 208.5008 cm -Q -q -1 0 0 1 40.01575 190.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_smi) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 178.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 172.5008 cm -Q -q -1 0 0 1 50.01575 154.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMI_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 148.5008 cm -Q -q -1 0 0 1 50.01575 130.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 106.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -Q -q -1 0 0 1 50.01575 82.50079 cm +1 0 0 1 50.01575 82.70079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q @@ -44735,15 +43558,15 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (108) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (104) Tj T* ET Q Q endstream endobj -1313 0 obj +1306 0 obj << -/Length 6426 +/Length 7111 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -44756,73 +43579,11 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_ts module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (secureboot package) Tj T* ET Q Q q -1 0 0 1 40.01575 748.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks for BIOS Interface Lock including Top Swap Mode) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 730.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (BIOS Boot Hijacking and VMware Vulnerabilities Digging) Tj 0 0 0 rg ( by Bing Sun) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 724.1008 cm -Q -q -1 0 0 1 40.01575 706.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_ts) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 694.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 688.1008 cm -Q -q -1 0 0 1 50.01575 670.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_bios_iface_lock) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 664.1008 cm -Q -q -1 0 0 1 50.01575 646.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 622.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 616.1008 cm -Q -q -1 0 0 1 50.01575 598.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 548.5008 cm +1 0 0 1 40.01575 716.5008 cm q 1 1 1 RG .3 w @@ -44830,59 +43591,40 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_wp module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (variables module) Tj T* ET Q Q q -1 0 0 1 40.01575 518.5008 cm +1 0 0 1 40.01575 698.5008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The BIOS region in flash can be protected either using SMM-based protection or using configuration in the SPI) Tj T* (controller. However, the SPI controller configuration is set once and locked, which would prevent writes later.) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (UEFI 2.4 spec Section 28) Tj T* ET Q Q q -1 0 0 1 40.01575 464.5008 cm +1 0 0 1 40.01575 668.5008 cm q 0 0 0 rg -BT 1 0 0 1 0 38 Tm /F1 10 Tf 12 TL (This module does check both mechanisms. In order to pass this test using SPI controller configuration, the SPI) Tj T* -0.028206 Tw (Protected Range registers \(PR0-4\) will need to cover the entire BIOS region. Often, if this configuration is used at all,) Tj T* 0 Tw (it is used only to protect part of the BIOS region \(usually the boot block\). If other important data \(eg. NVRAM\) is not) Tj T* (protected, however, some vulnerabilities may be possible.) Tj T* ET +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Verify that all Secure Boot key UEFI variables are authenticated \(BS+RT+AT\) and protected from unauthorized) Tj T* (modification.) Tj T* ET Q Q q -1 0 0 1 40.01575 422.5008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (A Tale of One Software Bypass of Windows 8 Secure Boot) Tj 0 0 0 rg ( described just such an attack. In a system where certain) Tj T* -0.111295 Tw (BIOS data was not protected, malware may be able to write to the Platform Key stored on the flash, thereby disabling) Tj T* 0 Tw (secure boot.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 368.5008 cm +1 0 0 1 40.01575 650.5008 cm q 0 0 0 rg -BT 1 0 0 1 0 38 Tm /F1 10 Tf 12 TL -0.058106 Tw (SMM based write protection is controlled from the BIOS Control Register. When the BIOS Write Protect Disable bit is) Tj T* 0 Tw (set \(sometimes called BIOSWE or BIOS Write Enable\), then writes are allowed. When cleared, it can also be locked) Tj T* (with the BIOS Lock Enable \(BLE\) bit. When locked, attempts to change the WPD bit will result in generation of an) Tj T* (SMI. This way, the SMI handler can decide whether to perform the write.) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Use \221-a modify\222 option for the module to also try to write/corrupt the variables.) Tj T* ET Q Q q -1 0 0 1 40.01575 326.5008 cm +1 0 0 1 40.01575 644.5008 cm +Q q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (As demonstrated in the ) Tj 0 0 .501961 rg (Speed Racer) Tj 0 0 0 rg ( issue, a race condition may exist between the outstanding write and) Tj T* (processing of the SMI that is generated. For this reason, the EISS bit \(sometimes called SMM_BWP or SMM BIOS) Tj T* (Write Protection\) must be set to ensure that only SMM can write to the SPI flash.) Tj T* ET +1 0 0 1 40.01575 626.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (variables) Tj T* ET Q Q q -1 0 0 1 40.01575 296.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (This module common.bios_wp will fail if SMM-based protection is not correctly configured and SPI protected ranges) Tj T* (\(PR registers\) do not protect the entire BIOS region.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 290.5008 cm -Q -q -1 0 0 1 40.01575 272.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_wp) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 260.5008 cm +1 0 0 1 50.01575 614.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -44890,49 +43632,49 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 254.5008 cm +1 0 0 1 50.01575 608.5008 cm Q q -1 0 0 1 50.01575 236.5008 cm +1 0 0 1 50.01575 590.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_BIOS_write_protection) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (can_modify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (attrs) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 230.5008 cm +1 0 0 1 50.01575 584.5008 cm Q q -1 0 0 1 50.01575 212.5008 cm +1 0 0 1 50.01575 566.5008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SPI_protected_ranges) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_secureboot_variable_attributes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 206.5008 cm +1 0 0 1 50.01575 560.5008 cm Q q -1 0 0 1 50.01575 188.5008 cm +1 0 0 1 50.01575 542.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 164.5008 cm +1 0 0 1 60.01575 518.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 158.5008 cm +1 0 0 1 50.01575 512.5008 cm Q q -1 0 0 1 50.01575 140.5008 cm +1 0 0 1 50.01575 494.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 90.90079 cm +1 0 0 1 40.01575 444.9008 cm q 1 1 1 RG .3 w @@ -44940,119 +43682,11 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (debugenabled module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi package) Tj T* ET Q Q q -1 0 0 1 40.01575 72.90079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if the system has debug features turned on, specifically the Direct Connect Interface \(DCI\).) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (109) Tj T* ET -Q -Q - -endstream -endobj -1314 0 obj -<< -/Length 5893 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 739.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (This module checks the following bits: 1. HDCIEN bit in the DCI Control Register 2. Debug enable bit in the) Tj T* (IA32_DEBUG_INTERFACE MSR 3. Debug lock bit in the IA32_DEBUG_INTERFACE MSR 4. Debug occurred bit in) Tj T* (the IA32_DEBUG_INTERFACE MSR) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 709.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module returns the following results: FAILED : Any one of the debug features is enabled or unlocked. PASSED :) Tj T* (All debug feature are diabled and locked.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 667.7008 cm -q -0 0 0 rg -BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (Hardware registers used: IA32_DEBUG_INTERFACE[DEBUGENABLE]) Tj T* (IA32_DEBUG_INTERFACE[DEBUGELOCK] IA32_DEBUG_INTERFACE[DEBUGEOCCURED]) Tj T* (P2SB_DCI.DCI_CONTROL_REG[HDCIEN]) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 661.7008 cm -Q -q -1 0 0 1 40.01575 643.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (debugenabled) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 631.7008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 625.7008 cm -Q -q -1 0 0 1 50.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_cpu_debug_enable) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 601.7008 cm -Q -q -1 0 0 1 50.01575 583.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_dci) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 577.7008 cm -Q -q -1 0 0 1 50.01575 559.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 535.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 529.7008 cm -Q -q -1 0 0 1 50.01575 511.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 462.1008 cm +1 0 0 1 40.01575 395.3008 cm q 1 1 1 RG .3 w @@ -45060,368 +43694,110 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ia32cfg module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (access_uefispec module) Tj T* ET Q Q q -1 0 0 1 40.01575 432.1008 cm +1 0 0 1 40.01575 377.3008 cm q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Tests that IA-32/IA-64 architectural features are configured and locked, including IA32 Model Specific Registers) Tj T* (\(MSRs\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks protection of UEFI variables defined in the UEFI spec to have certain permissions.) Tj T* ET Q Q q -1 0 0 1 40.01575 414.1008 cm +1 0 0 1 40.01575 359.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Returns failure if variable attributes are not as defined in ) Tj 0 0 .501961 rg (table 11 \223Global Variables\224) Tj 0 0 0 rg ( of the UEFI spec.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 343.3008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Reference: Intel Software Developer\222s Manual) Tj T* ET +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 408.1008 cm -Q -q -1 0 0 1 40.01575 390.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ia32cfg) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 378.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 372.1008 cm -Q -q -1 0 0 1 50.01575 354.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_ia32feature_control) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 348.1008 cm -Q -q -1 0 0 1 50.01575 330.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 306.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 300.1008 cm -Q -q -1 0 0 1 50.01575 282.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 232.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (me_mfg_mode module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 214.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks that ME Manufacturing mode is not enabled) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 196.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 178.5008 cm -q -0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (https://blog.ptsecurity.com/2018/10/intel-me-manufacturing-mode-macbook.html) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 160.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (PCI_DEVS.H) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 124.9008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 34.8 re B* -Q -q -0 0 0 rg -BT 1 0 0 1 0 20.8 Tm /F3 8 Tf 9.6 TL (#define PCH_DEV_SLOT_CSE 0x16) Tj T* (#define PCH_DEVFN_CSE _PCH_DEVFN\(CSE, 0\)) Tj T* (#define PCH_DEV_CSE _PCH_DEV\(CSE, 0\)) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 104.9008 cm -q -0 0 .501961 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/apollolake/cse.c) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 69.30079 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 34.8 re B* -Q -q -BT 1 0 0 1 0 20.8 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (fwsts1 = dump_status\(1, PCI_ME_HFSTS1\);) Tj T* (# Minimal decoding is done here in order to call out most important) Tj T* (# pieces. Manufacturing mode needs to be locked down prior to shipping) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (110) Tj T* ET -Q -Q - -endstream -endobj -1315 0 obj -<< -/Length 5822 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 749.7008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 25.2 re B* -Q -q -BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (# the product so it's called out explicitly.) Tj T* (printk\(BIOS_DEBUG, "ME: Manufacturing Mode : %s", \(fwsts1 ) Tj (&) Tj ( \(1 ) Tj (<) Tj (<) Tj ( 0x4\)\) ? "YES" : "NO"\);) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 729.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (PCH.H) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 713.3008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 15.6 re B* -Q -q -0 0 0 rg -BT 1 0 0 1 0 1.6 Tm /F3 8 Tf 9.6 TL (#define PCH_ME_DEV PCI_DEV\(0, 0x16, 0\)) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 693.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (ME.H) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 542.5008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 150 re B* -Q -q -0 0 0 rg -BT 1 0 0 1 0 136 Tm /F3 8 Tf 9.6 TL (struct me_hfs {) Tj T* ( u32 working_state: 4;) Tj T* ( u32 mfg_mode: 1;) Tj T* ( u32 fpt_bad: 1;) Tj T* ( u32 operation_state: 3;) Tj T* ( u32 fw_init_complete: 1;) Tj T* ( u32 ft_bup_ld_flr: 1;) Tj T* ( u32 update_in_progress: 1;) Tj T* ( u32 error_code: 4;) Tj T* ( u32 operation_mode: 4;) Tj T* ( u32 reserved: 4;) Tj T* ( u32 boot_options_present: 1;) Tj T* ( u32 ack_data: 3;) Tj T* ( u32 bios_msg_ack: 4;) Tj T* (} __packed;) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 522.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (ME_STATUS.C) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 506.1008 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 514.4441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (printk\(BIOS_DEBUG, "ME: Manufacturing Mode : %s", hfs-) Tj (>) Tj (mfg_mode ? "YES" : "NO"\);) Tj T* ET -Q -Q -Q -Q -Q -q -1 0 0 1 40.01575 486.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks the following:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 480.1008 cm -Q -q -1 0 0 1 40.01575 468.1008 cm +1 0 0 1 40.01575 310.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q -1 0 0 1 20 0 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (HFS.MFG_MODE BDF: 0:22:0 offset 0x40 - Bit [4]) Tj T* ET -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 468.1008 cm -Q -q -1 0 0 1 40.01575 450.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The module returns the following results:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 444.1008 cm -Q -q -1 0 0 1 40.01575 414.1008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET +BT 1 0 0 1 0 20 Tm T* ET q 1 0 0 1 20 18 cm q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (FAILED : HFS.MFG_MODE is set) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main) Tj ( ) Tj (-m) Tj ( ) Tj (common.uefi.access_uefispec) Tj ( ) Tj ([-a) Tj ( ) Tj (modify]) Tj T* ET Q Q q +1 0 0 1 20 12 cm +Q +q +1 0 0 1 20 12 cm +Q +q 1 0 0 1 20 0 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (PASSED : HFS.MFG_MODE is not set.) Tj T* ET -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 414.1008 cm -Q -q -1 0 0 1 40.01575 396.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 390.1008 cm -Q -q -1 0 0 1 40.01575 378.1008 cm -q -0 0 0 rg BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 6 -3 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET +Q +Q +q +1 0 0 1 23 -3 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (-a) Tj ( ) Tj (modify) Tj /F1 10 Tf (: Attempt to modify each variable in addition to checking attributes) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 20 0 cm +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 294.3008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Where:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 273.3008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 8 Tm T* ET +q +1 0 0 1 20 12 cm +Q +q +1 0 0 1 20 12 cm +Q q 1 0 0 1 20 0 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (HFS) Tj T* ET +BT /F1 10 Tf 12 TL ET +q +1 0 0 1 6 -3 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET +Q +Q +q +1 0 0 1 23 -3 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg ([]) Tj /F1 10 Tf (: optional line) Tj T* ET Q Q q @@ -45429,87 +43805,67 @@ Q Q Q q -1 0 0 1 40.01575 378.1008 cm +1 0 0 1 20 0 cm Q q -1 0 0 1 40.01575 372.1008 cm Q -q -1 0 0 1 40.01575 354.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (me_mfg_mode) Tj T* ET Q Q q -1 0 0 1 50.01575 342.1008 cm +1 0 0 1 40.01575 257.3008 cm q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 50.01575 336.1008 cm -Q +1 0 0 1 40.01575 228.3008 cm q -1 0 0 1 50.01575 318.1008 cm +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 16 Tm T* ET q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_me_mfg_mode) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q +1 0 0 1 20 0 cm q -1 0 0 1 50.01575 312.1008 cm -Q q -1 0 0 1 50.01575 294.1008 cm +1 0 0 1 0 0 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q +1 0 0 1 4.4 .4 cm q -1 0 0 1 60.01575 270.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 264.1008 cm -Q -q -1 0 0 1 50.01575 246.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 196.5008 cm -q -1 1 1 RG +.666667 .8 .6 RG .3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* +.933333 1 .8 rg +n -4 0 494.4441 25.2 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (memconfig module) Tj T* ET +BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.access_uefispec) Tj T* (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.access_uefispec -a modify) Tj T* ET +Q +Q +Q Q Q q -1 0 0 1 40.01575 166.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module verifies memory map secure configuration, i.e. that memory map registers are correctly configured and) Tj T* (locked down.) Tj T* ET +Q Q Q q -1 0 0 1 40.01575 160.5008 cm -Q +1 0 0 1 40.01575 210.3008 cm q -1 0 0 1 40.01575 142.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (memconfig) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (NOTE: Requires an OS with UEFI Runtime API support.) Tj T* ET Q Q q -1 0 0 1 50.01575 130.5008 cm +1 0 0 1 40.01575 204.3008 cm +Q +q +1 0 0 1 40.01575 186.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (access_uefispec) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 174.3008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -45517,19 +43873,37 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 124.5008 cm +1 0 0 1 50.01575 168.3008 cm Q q -1 0 0 1 50.01575 106.5008 cm +1 0 0 1 50.01575 150.3008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_memmap_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (can_modify) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 100.5008 cm +1 0 0 1 50.01575 144.3008 cm Q q -1 0 0 1 50.01575 82.50079 cm +1 0 0 1 50.01575 126.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_vars) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 120.3008 cm +Q +q +1 0 0 1 50.01575 102.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (diff_var) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (data1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data2) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 96.30079 cm +Q +q +1 0 0 1 50.01575 78.30079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q @@ -45544,15 +43918,15 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (111) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (105) Tj T* ET Q Q endstream endobj -1316 0 obj +1307 0 obj << -/Length 5872 +/Length 6963 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -45580,53 +43954,242 @@ q n -10 0 525.2441 15.6 re B* Q q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (memlock module) Tj T* ET +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (s3bootscript module) Tj T* ET Q Q q 1 0 0 1 40.01575 660.1008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if memory configuration is locked to protect SMM) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks protections of the S3 resume boot-script implemented by the UEFI based firmware) Tj T* ET Q Q q -1 0 0 1 40.01575 630.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reference: ) Tj 0 0 .501961 rg (https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c) Tj 0 0 0 rg T* 0 0 .501961 rg (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 612.1008 cm +1 0 0 1 40.01575 642.1008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks the following: - MSR_LT_LOCK_MEMORY MSR \(0x2E7\) - Bit [0]) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET Q Q q -1 0 0 1 40.01575 582.1008 cm +1 0 0 1 40.01575 624.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (VU#976132 UEFI implementations do not properly secure the EFI S3 Resume Boot Path boot script) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 606.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Technical Details of the S3 Resume Boot Script Vulnerability) Tj 0 0 0 rg ( by Intel Security\222s Advanced Threat Research team.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 588.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Attacks on UEFI Security) Tj 0 0 0 rg ( by Rafal Wojtczuk and Corey Kallenberg.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 570.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Attacking UEFI Boot Script) Tj 0 0 0 rg ( by Rafal Wojtczuk and Corey Kallenberg.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 552.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Exploiting UEFI boot script table vulnerability) Tj 0 0 0 rg ( by Dmytro Oleksiuk.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 536.1008 cm q 0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module returns the following results: FAILED : MSR_LT_LOCK_MEMORY[0] is not set PASSED :) Tj T* (MSR_LT_LOCK_MEMORY[0] is set.) Tj T* ET +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 564.1008 cm +1 0 0 1 40.01575 503.1008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used: MSR_LT_LOCK_MEMORY) Tj T* ET +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 20 Tm T* ET +q +1 0 0 1 20 18 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main.py) Tj ( ) Tj (-m) Tj ( ) Tj (common.uefi.s3bootscript) Tj ( ) Tj ([-a) Tj ( ) Tj (<) Tj (script_address) Tj (>) Tj (]) Tj T* ET Q Q q -1 0 0 1 40.01575 558.1008 cm +1 0 0 1 20 12 cm Q q -1 0 0 1 40.01575 540.1008 cm +1 0 0 1 20 12 cm +Q q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (memlock) Tj T* ET +1 0 0 1 20 0 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +q +1 0 0 1 6 -3 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET Q Q q -1 0 0 1 50.01575 528.1008 cm +1 0 0 1 23 -3 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (-a) Tj ( ) Tj (<) Tj (script_address) Tj (>) Tj /F1 10 Tf (: Specify the bootscript address) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 20 0 cm +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 487.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Where:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 466.1008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 8 Tm T* ET +q +1 0 0 1 20 12 cm +Q +q +1 0 0 1 20 12 cm +Q +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +q +1 0 0 1 6 -3 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET +Q +Q +q +1 0 0 1 23 -3 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg ([]) Tj /F1 10 Tf (: optional line) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 20 0 cm +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 450.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Examples:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 421.1008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 16 Tm T* ET +q +1 0 0 1 20 0 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 494.4441 25.2 re B* +Q +q +BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.s3bootscript) Tj T* (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.uefi.s3bootscript -a 0x00000000BDE10000) Tj T* ET +Q +Q +Q +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 409.1008 cm +Q +q +1 0 0 1 40.01575 352.3008 cm +q +.933333 .933333 .933333 rg +n 0 56.8 515.2441 -56.8 re f* +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 6 38.8 Tm T* ET +q +1 0 0 1 8 32 cm +q +0 0 0 rg +BT 1 0 0 1 0 2.8 Tm /F5 14 Tf 16.8 TL (Note) Tj T* ET +Q +Q +q +1 0 0 1 8 8 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Requires an OS with UEFI Runtime API support.) Tj T* ET +Q +Q +q +1 J +1 j +.8 .8 .8 RG +.5 w +n 0 56.8 m 515.2441 56.8 l S +n 0 0 m 515.2441 0 l S +n 0 0 m 0 56.8 l S +n 515.2441 0 m 515.2441 56.8 l S +Q +Q +Q +q +1 0 0 1 40.01575 346.3008 cm +Q +q +1 0 0 1 40.01575 340.3008 cm +Q +q +1 0 0 1 40.01575 322.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (s3bootscript) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 310.3008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -45634,40 +44197,1309 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 522.1008 cm +1 0 0 1 50.01575 304.3008 cm Q q -1 0 0 1 50.01575 504.1008 cm +1 0 0 1 50.01575 286.3008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_MSR_LT_LOCK_MEMORY) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_dispatch_opcodes) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bootscript_entries) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 498.1008 cm +1 0 0 1 50.01575 280.3008 cm Q q -1 0 0 1 50.01575 480.1008 cm +1 0 0 1 50.01575 262.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_s3_bootscript) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bootscript_pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 256.3008 cm +Q +q +1 0 0 1 50.01575 238.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_s3_bootscripts) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bsaddress) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (None) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 232.3008 cm +Q +q +1 0 0 1 50.01575 214.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_inside_SMRAM) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 208.3008 cm +Q +q +1 0 0 1 50.01575 190.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_inside_SPI) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 184.3008 cm +Q +q +1 0 0 1 50.01575 166.3008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 456.1008 cm +1 0 0 1 60.01575 142.3008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 450.1008 cm +1 0 0 1 50.01575 136.3008 cm Q q -1 0 0 1 50.01575 432.1008 cm +1 0 0 1 50.01575 118.3008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 382.5008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (106) Tj T* ET +Q +Q + +endstream +endobj +1308 0 obj +<< +/Length 6107 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_kbrd_buffer module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 736.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (DEFCON 16: ) Tj 0 0 .501961 rg (Bypassing Pre-boot Authentication Passwords by Instrumenting the BIOS Keyboard Buffer) Tj 0 0 0 rg ( by) Tj T* (Jonathan Brossard) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 718.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Checks for BIOS/HDD password exposure through BIOS keyboard buffer.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 700.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Checks for exposure of pre-boot passwords \(BIOS/HDD/pre-bot authentication SW\) in the BIOS keyboard buffer.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 694.1008 cm +Q +q +1 0 0 1 40.01575 676.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_kbrd_buffer) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 664.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 658.1008 cm +Q +q +1 0 0 1 50.01575 640.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_BIOS_keyboard_buffer) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 634.1008 cm +Q +q +1 0 0 1 50.01575 616.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 592.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 586.1008 cm +Q +q +1 0 0 1 50.01575 568.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 518.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_smi module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 488.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module checks that SMI events configuration is locked down - Global SMI Enable/SMI Lock - TCO SMI) Tj T* (Enable/TCO Lock) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 470.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 452.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Setup for Failure: Defeating SecureBoot) Tj 0 0 0 rg ( by Corey Kallenberg, Xeno Kovah, John Butterworth, Sam Cornwell) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 410.5008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F4 10 Tf 0 0 0 rg (Summary of Attacks Against BIOS and Secure Boot) Tj /F1 10 Tf ( \() Tj 0 0 .501961 rg (https://www.defcon.org/images/defcon-22/dc-22-presentations/) Tj 0 0 0 rg T* 0 0 .501961 rg (Bulygin-Bazhaniul-Furtak-Loucaides/DEFCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against) Tj T* (-BIOS-UPDATED.pdf) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 404.5008 cm +Q +q +1 0 0 1 40.01575 386.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_smi) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 374.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 368.5008 cm +Q +q +1 0 0 1 50.01575 350.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMI_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 344.5008 cm +Q +q +1 0 0 1 50.01575 326.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 302.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 296.5008 cm +Q +q +1 0 0 1 50.01575 278.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 228.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_ts module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 210.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks for BIOS Interface Lock including Top Swap Mode) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 192.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (BIOS Boot Hijacking and VMware Vulnerabilities Digging) Tj 0 0 0 rg ( by Bing Sun) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 186.9008 cm +Q +q +1 0 0 1 40.01575 168.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_ts) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 156.9008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 150.9008 cm +Q +q +1 0 0 1 50.01575 132.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_bios_iface_lock) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 126.9008 cm +Q +q +1 0 0 1 50.01575 108.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 84.90079 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 78.90079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (107) Tj T* ET +Q +Q + +endstream +endobj +1309 0 obj +<< +/Length 6168 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 714.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (bios_wp module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 684.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The BIOS region in flash can be protected either using SMM-based protection or using configuration in the SPI) Tj T* (controller. However, the SPI controller configuration is set once and locked, which would prevent writes later.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 630.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 38 Tm /F1 10 Tf 12 TL (This module does check both mechanisms. In order to pass this test using SPI controller configuration, the SPI) Tj T* -0.028206 Tw (Protected Range registers \(PR0-4\) will need to cover the entire BIOS region. Often, if this configuration is used at all,) Tj T* 0 Tw (it is used only to protect part of the BIOS region \(usually the boot block\). If other important data \(eg. NVRAM\) is not) Tj T* (protected, however, some vulnerabilities may be possible.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 588.1008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (A Tale of One Software Bypass of Windows 8 Secure Boot) Tj 0 0 0 rg ( described just such an attack. In a system where certain) Tj T* -0.111295 Tw (BIOS data was not protected, malware may be able to write to the Platform Key stored on the flash, thereby disabling) Tj T* 0 Tw (secure boot.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 534.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 38 Tm /F1 10 Tf 12 TL -0.058106 Tw (SMM based write protection is controlled from the BIOS Control Register. When the BIOS Write Protect Disable bit is) Tj T* 0 Tw (set \(sometimes called BIOSWE or BIOS Write Enable\), then writes are allowed. When cleared, it can also be locked) Tj T* (with the BIOS Lock Enable \(BLE\) bit. When locked, attempts to change the WPD bit will result in generation of an) Tj T* (SMI. This way, the SMI handler can decide whether to perform the write.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 492.1008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (As demonstrated in the ) Tj 0 0 .501961 rg (Speed Racer) Tj 0 0 0 rg ( issue, a race condition may exist between the outstanding write and) Tj T* (processing of the SMI that is generated. For this reason, the EISS bit \(sometimes called SMM_BWP or SMM BIOS) Tj T* (Write Protection\) must be set to ensure that only SMM can write to the SPI flash.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 462.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (This module common.bios_wp will fail if SMM-based protection is not correctly configured and SPI protected ranges) Tj T* (\(PR registers\) do not protect the entire BIOS region.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 456.1008 cm +Q +q +1 0 0 1 40.01575 438.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (bios_wp) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 426.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 420.1008 cm +Q +q +1 0 0 1 50.01575 402.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_BIOS_write_protection) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 396.1008 cm +Q +q +1 0 0 1 50.01575 378.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SPI_protected_ranges) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 372.1008 cm +Q +q +1 0 0 1 50.01575 354.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 330.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 324.1008 cm +Q +q +1 0 0 1 50.01575 306.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 256.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (debugenabled module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 238.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if the system has debug features turned on, specifically the Direct Connect Interface \(DCI\).) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 196.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (This module checks the following bits: 1. HDCIEN bit in the DCI Control Register 2. Debug enable bit in the) Tj T* (IA32_DEBUG_INTERFACE MSR 3. Debug lock bit in the IA32_DEBUG_INTERFACE MSR 4. Debug occurred bit in) Tj T* (the IA32_DEBUG_INTERFACE MSR) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 166.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module returns the following results: FAILED : Any one of the debug features is enabled or unlocked. PASSED :) Tj T* (All debug feature are diabled and locked.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 124.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 26 Tm /F1 10 Tf 12 TL (Hardware registers used: IA32_DEBUG_INTERFACE[DEBUGENABLE]) Tj T* (IA32_DEBUG_INTERFACE[DEBUGELOCK] IA32_DEBUG_INTERFACE[DEBUGEOCCURED]) Tj T* (P2SB_DCI.DCI_CONTROL_REG[HDCIEN]) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 118.5008 cm +Q +q +1 0 0 1 40.01575 100.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (debugenabled) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 88.50079 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 82.50079 cm +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (108) Tj T* ET +Q +Q + +endstream +endobj +1310 0 obj +<< +/Length 5748 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_cpu_debug_enable) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_dci) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 691.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 618.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ia32cfg module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 588.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Tests that IA-32/IA-64 architectural features are configured and locked, including IA32 Model Specific Registers) Tj T* (\(MSRs\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 570.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Reference: Intel Software Developer\222s Manual) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 564.1008 cm +Q +q +1 0 0 1 40.01575 546.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ia32cfg) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 534.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 528.1008 cm +Q +q +1 0 0 1 50.01575 510.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_ia32feature_control) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 504.1008 cm +Q +q +1 0 0 1 50.01575 486.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 462.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 456.1008 cm +Q +q +1 0 0 1 50.01575 438.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 388.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (me_mfg_mode module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 370.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks that ME Manufacturing mode is not enabled) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 352.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 334.5008 cm +q +0 0 .501961 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (https://blog.ptsecurity.com/2018/10/intel-me-manufacturing-mode-macbook.html) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 316.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (PCI_DEVS.H) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 280.9008 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 34.8 re B* +Q +q +0 0 0 rg +BT 1 0 0 1 0 20.8 Tm /F3 8 Tf 9.6 TL (#define PCH_DEV_SLOT_CSE 0x16) Tj T* (#define PCH_DEVFN_CSE _PCH_DEVFN\(CSE, 0\)) Tj T* (#define PCH_DEV_CSE _PCH_DEV\(CSE, 0\)) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 40.01575 260.9008 cm +q +0 0 .501961 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/apollolake/cse.c) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 206.1008 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 54 re B* +Q +q +BT 1 0 0 1 0 40 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (fwsts1 = dump_status\(1, PCI_ME_HFSTS1\);) Tj T* (# Minimal decoding is done here in order to call out most important) Tj T* (# pieces. Manufacturing mode needs to be locked down prior to shipping) Tj T* (# the product so it's called out explicitly.) Tj T* (printk\(BIOS_DEBUG, "ME: Manufacturing Mode : %s", \(fwsts1 ) Tj (&) Tj ( \(1 ) Tj (<) Tj (<) Tj ( 0x4\)\) ? "YES" : "NO"\);) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 40.01575 186.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (PCH.H) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 169.7008 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 15.6 re B* +Q +q +0 0 0 rg +BT 1 0 0 1 0 1.6 Tm /F3 8 Tf 9.6 TL (#define PCH_ME_DEV PCI_DEV\(0, 0x16, 0\)) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 40.01575 149.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (ME.H) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 75.70079 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 73.2 re B* +Q +q +0 0 0 rg +BT 1 0 0 1 0 59.2 Tm /F3 8 Tf 9.6 TL (struct me_hfs {) Tj T* ( u32 working_state: 4;) Tj T* ( u32 mfg_mode: 1;) Tj T* ( u32 fpt_bad: 1;) Tj T* ( u32 operation_state: 3;) Tj T* ( u32 fw_init_complete: 1;) Tj T* ( u32 ft_bup_ld_flr: 1;) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (109) Tj T* ET +Q +Q + +endstream +endobj +1311 0 obj +<< +/Length 6091 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 692.1008 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 82.8 re B* +Q +q +0 0 0 rg +BT 1 0 0 1 0 68.8 Tm /F3 8 Tf 9.6 TL ( u32 update_in_progress: 1;) Tj T* ( u32 error_code: 4;) Tj T* ( u32 operation_mode: 4;) Tj T* ( u32 reserved: 4;) Tj T* ( u32 boot_options_present: 1;) Tj T* ( u32 ack_data: 3;) Tj T* ( u32 bios_msg_ack: 4;) Tj T* (} __packed;) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 40.01575 672.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (ME_STATUS.C) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 655.7008 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 514.4441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (printk\(BIOS_DEBUG, "ME: Manufacturing Mode : %s", hfs-) Tj (>) Tj (mfg_mode ? "YES" : "NO"\);) Tj T* ET +Q +Q +Q +Q +Q +q +1 0 0 1 40.01575 635.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks the following:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 629.7008 cm +Q +q +1 0 0 1 40.01575 617.7008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (HFS.MFG_MODE BDF: 0:22:0 offset 0x40 - Bit [4]) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 617.7008 cm +Q +q +1 0 0 1 40.01575 599.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The module returns the following results:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 593.7008 cm +Q +q +1 0 0 1 40.01575 563.7008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 18 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (FAILED : HFS.MFG_MODE is set) Tj T* ET +Q +Q +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (PASSED : HFS.MFG_MODE is not set.) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 563.7008 cm +Q +q +1 0 0 1 40.01575 545.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 539.7008 cm +Q +q +1 0 0 1 40.01575 527.7008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (HFS) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 527.7008 cm +Q +q +1 0 0 1 40.01575 521.7008 cm +Q +q +1 0 0 1 40.01575 503.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (me_mfg_mode) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 491.7008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 485.7008 cm +Q +q +1 0 0 1 50.01575 467.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_me_mfg_mode) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 461.7008 cm +Q +q +1 0 0 1 50.01575 443.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 419.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 413.7008 cm +Q +q +1 0 0 1 50.01575 395.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 346.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (memconfig module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 316.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module verifies memory map secure configuration, i.e. that memory map registers are correctly configured and) Tj T* (locked down.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 310.1008 cm +Q +q +1 0 0 1 40.01575 292.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (memconfig) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 280.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 274.1008 cm +Q +q +1 0 0 1 50.01575 256.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_memmap_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 250.1008 cm +Q +q +1 0 0 1 50.01575 232.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 208.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 202.1008 cm +Q +q +1 0 0 1 50.01575 184.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 134.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (memlock module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 116.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if memory configuration is locked to protect SMM) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 86.50079 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reference: ) Tj 0 0 .501961 rg (https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c) Tj 0 0 0 rg T* 0 0 .501961 rg (https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 68.50079 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks the following: - MSR_LT_LOCK_MEMORY MSR \(0x2E7\) - Bit [0]) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (110) Tj T* ET +Q +Q + +endstream +endobj +1312 0 obj +<< +/Length 6211 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 751.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module returns the following results: FAILED : MSR_LT_LOCK_MEMORY[0] is not set PASSED :) Tj T* (MSR_LT_LOCK_MEMORY[0] is set.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 733.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used: MSR_LT_LOCK_MEMORY) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 717.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 702.7008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main) Tj ( ) Tj (-m) Tj ( ) Tj (common.memlock) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 686.7008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Example:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 667.3008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 6.4 Tm T* ET +q +1 0 0 1 20 0 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 494.4441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.memlock) Tj T* ET +Q +Q +Q +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 655.3008 cm +Q +q +1 0 0 1 40.01575 598.5008 cm +q +.933333 .933333 .933333 rg +n 0 56.8 515.2441 -56.8 re f* +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 6 38.8 Tm T* ET +q +1 0 0 1 8 32 cm +q +0 0 0 rg +BT 1 0 0 1 0 2.8 Tm /F5 14 Tf 16.8 TL (Note) Tj T* ET +Q +Q +q +1 0 0 1 8 8 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module will not run on Atom based platforms.) Tj T* ET +Q +Q +q +1 J +1 j +.8 .8 .8 RG +.5 w +n 0 56.8 m 515.2441 56.8 l S +n 0 0 m 515.2441 0 l S +n 0 0 m 0 56.8 l S +n 515.2441 0 m 515.2441 56.8 l S +Q +Q +Q +q +1 0 0 1 40.01575 592.5008 cm +Q +q +1 0 0 1 40.01575 586.5008 cm +Q +q +1 0 0 1 40.01575 568.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (memlock) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 556.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 550.5008 cm +Q +q +1 0 0 1 50.01575 532.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_MSR_LT_LOCK_MEMORY) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 526.5008 cm +Q +q +1 0 0 1 50.01575 508.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 484.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 478.5008 cm +Q +q +1 0 0 1 50.01575 460.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 410.9008 cm q 1 1 1 RG .3 w @@ -45679,29 +45511,128 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (remap module) Tj T* ET Q Q q -1 0 0 1 40.01575 364.5008 cm +1 0 0 1 40.01575 392.9008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (Preventing & Detecting Xen Hypervisor Subversions) Tj 0 0 0 rg ( by Joanna Rutkowska & Rafal Wojtczuk) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check Memory Remapping Configuration) Tj T* ET Q Q q -1 0 0 1 40.01575 346.5008 cm +1 0 0 1 40.01575 374.9008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reference: ) Tj 0 0 .501961 rg (Preventing & Detecting Xen Hypervisor Subversions) Tj 0 0 0 rg ( by Joanna Rutkowska & Rafal Wojtczuk) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 358.9008 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Check Memory Remapping Configuration) Tj T* ET +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 340.5008 cm +1 0 0 1 40.01575 343.9008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main) Tj ( ) Tj (-m) Tj ( ) Tj (common.remap) Tj T* ET +Q Q q -1 0 0 1 40.01575 322.5008 cm +Q +Q +Q +q +1 0 0 1 40.01575 327.9008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Example:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 308.5008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 6.4 Tm T* ET +q +1 0 0 1 20 0 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 494.4441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.remap) Tj T* ET +Q +Q +Q +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 296.5008 cm +Q +q +1 0 0 1 40.01575 239.7008 cm +q +.933333 .933333 .933333 rg +n 0 56.8 515.2441 -56.8 re f* +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 6 38.8 Tm T* ET +q +1 0 0 1 8 32 cm +q +0 0 0 rg +BT 1 0 0 1 0 2.8 Tm /F5 14 Tf 16.8 TL (Note) Tj T* ET +Q +Q +q +1 0 0 1 8 8 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module will only run on Core platforms.) Tj T* ET +Q +Q +q +1 J +1 j +.8 .8 .8 RG +.5 w +n 0 56.8 m 515.2441 56.8 l S +n 0 0 m 515.2441 0 l S +n 0 0 m 0 56.8 l S +n 515.2441 0 m 515.2441 56.8 l S +Q +Q +Q +q +1 0 0 1 40.01575 233.7008 cm +Q +q +1 0 0 1 40.01575 227.7008 cm +Q +q +1 0 0 1 40.01575 209.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (remap) Tj T* ET Q Q q -1 0 0 1 50.01575 310.5008 cm +1 0 0 1 50.01575 197.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -45709,40 +45640,62 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 304.5008 cm +1 0 0 1 50.01575 191.7008 cm Q q -1 0 0 1 50.01575 286.5008 cm +1 0 0 1 50.01575 173.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_remap_config) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 280.5008 cm +1 0 0 1 50.01575 167.7008 cm Q q -1 0 0 1 50.01575 262.5008 cm +1 0 0 1 50.01575 149.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 238.5008 cm +1 0 0 1 60.01575 125.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 232.5008 cm +1 0 0 1 50.01575 119.7008 cm Q q -1 0 0 1 50.01575 214.5008 cm +1 0 0 1 50.01575 101.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 164.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (111) Tj T* ET +Q +Q + +endstream +endobj +1313 0 obj +<< +/Length 6367 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -45754,22 +45707,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rtclock module) Tj T* ET Q Q q -1 0 0 1 40.01575 134.9008 cm +1 0 0 1 40.01575 736.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks for RTC memory locks. Since we do not know what RTC memory will be used for on a specific platform, we) Tj T* (return WARNING \(rather than FAILED\) if the memory is not locked.) Tj T* ET Q Q q -1 0 0 1 40.01575 128.9008 cm +1 0 0 1 40.01575 730.1008 cm Q q -1 0 0 1 40.01575 110.9008 cm +1 0 0 1 40.01575 712.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (rtclock) Tj T* ET Q Q q -1 0 0 1 50.01575 98.90079 cm +1 0 0 1 50.01575 700.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -45777,16 +45730,237 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 92.90079 cm +1 0 0 1 50.01575 694.1008 cm Q q -1 0 0 1 50.01575 74.90079 cm +1 0 0 1 50.01575 676.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_rtclock) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 68.90079 cm +1 0 0 1 50.01575 670.1008 cm +Q +q +1 0 0 1 50.01575 652.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 628.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 622.1008 cm +Q +q +1 0 0 1 50.01575 604.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 554.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (sgx_check module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 536.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check SGX related configuration Reference: SGX BWG, CDI/IBP#: 565432) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 530.5008 cm +Q +q +1 0 0 1 40.01575 512.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (sgx_check) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 500.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 494.5008 cm +Q +q +1 0 0 1 50.01575 476.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_sgx_config) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 470.5008 cm +Q +q +1 0 0 1 50.01575 452.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 428.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 422.5008 cm +Q +q +1 0 0 1 50.01575 404.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 354.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 324.9008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Compatible SMM memory \(SMRAM\) Protection check module This CHIPSEC module simply reads SMRAMC and) Tj T* (checks that D_LCK is set.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 282.9008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (Reference: In 2006, ) Tj 0 0 .501961 rg (Security Issues Related to Pentium System Management Mode) Tj 0 0 0 rg ( outlined a configuration issue) Tj T* (where compatibility SMRAM was not locked on some platforms. This means that ring 0 software was able to modify) Tj T* (System Management Mode \(SMM\) code and data that should have been protected.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 240.9008 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (In Compatability SMRAM \(CSEG\), access to memory is defined by the SMRAMC register. When SMRAMC[D_LCK]) Tj T* (is not set by the BIOS, SMRAM can be accessed even when the CPU is not in SMM. Such attacks were also) Tj T* (described in ) Tj 0 0 .501961 rg (Using CPU SMM to Circumvent OS Security Functions) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (Using SMM for Other Purposes) Tj 0 0 0 rg (.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 224.9008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 209.9008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main) Tj ( ) Tj (-m) Tj ( ) Tj (common.smm) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 193.9008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Examples:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 174.5008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 6.4 Tm T* ET +q +1 0 0 1 20 0 cm +q +q +1 0 0 1 0 0 cm +q +1 0 0 1 4.4 .4 cm +q +.666667 .8 .6 RG +.3 w +.933333 1 .8 rg +n -4 0 494.4441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (>) Tj (>) Tj (>) Tj ( chipsec_main.py -m common.smm) Tj T* ET +Q +Q +Q +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 156.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module will only run on client \(core\) platforms that have PCI0.0.0_SMRAMC defined.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 150.5008 cm +Q +q +1 0 0 1 40.01575 132.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 120.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 114.5008 cm +Q +q +1 0 0 1 50.01575 96.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRAMC) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 90.50079 cm +Q +q +1 0 0 1 50.01575 72.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -45804,184 +45978,29 @@ Q endstream endobj -1317 0 obj +1314 0 obj << -/Length 6159 +/Length 5767 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 739.7008 cm +1 0 0 1 60.01575 751.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 50.01575 745.7008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 50.01575 727.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 666.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (sgx_check module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 648.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Check SGX related configuration Reference: SGX BWG, CDI/IBP#: 565432) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 642.1008 cm -Q -q -1 0 0 1 40.01575 624.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (sgx_check) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 612.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 606.1008 cm -Q -q -1 0 0 1 50.01575 588.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_sgx_config) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 582.1008 cm -Q -q -1 0 0 1 50.01575 564.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 540.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 534.1008 cm -Q -q -1 0 0 1 50.01575 516.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 466.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 424.5008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (In 2006, ) Tj 0 0 .501961 rg (Security Issues Related to Pentium System Management Mode) Tj 0 0 0 rg ( outlined a configuration issue where) Tj T* -0.026995 Tw (compatibility SMRAM was not locked on some platforms. This means that ring 0 software was able to modify System) Tj T* 0 Tw (Management Mode \(SMM\) code and data that should have been protected.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 382.5008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (In Compatability SMRAM \(CSEG\), access to memory is defined by the SMRAMC register. When SMRAMC[D_LCK]) Tj T* (is not set by the BIOS, SMRAM can be accessed even when the CPU is not in SMM. Such attacks were also) Tj T* (described in ) Tj 0 0 .501961 rg (Using CPU SMM to Circumvent OS Security Functions) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (Using SMM for Other Purposes) Tj 0 0 0 rg (.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 364.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This CHIPSEC module simply reads SMRAMC and checks that D_LCK is set.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 358.5008 cm -Q -q -1 0 0 1 40.01575 340.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 328.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 322.5008 cm -Q -q -1 0 0 1 50.01575 304.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRAMC) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 298.5008 cm -Q -q -1 0 0 1 50.01575 280.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 256.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 250.5008 cm -Q -q -1 0 0 1 50.01575 232.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 182.9008 cm +1 0 0 1 40.01575 678.1008 cm q 1 1 1 RG .3 w @@ -45993,22 +46012,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm_code_chk module) Tj T* ET Q Q q -1 0 0 1 40.01575 128.9008 cm +1 0 0 1 40.01575 624.1008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (SMM_Code_Chk_En is a bit found in the MSR_SMM_FEATURE_CONTROL register. Once set to \2211\222, any CPU that) Tj T* (attempts to execute SMM code not within the ranges defined by the SMRR will assert an unrecoverable MCE. As) Tj T* (such, enabling and locking this bit is an important step in mitigating SMM call-out vulnerabilities. This CHIPSEC) Tj T* (module simply reads the register and checks that SMM_Code_Chk_En is set and locked.) Tj T* ET Q Q q -1 0 0 1 40.01575 122.9008 cm +1 0 0 1 40.01575 618.1008 cm Q q -1 0 0 1 40.01575 104.9008 cm +1 0 0 1 40.01575 600.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm_code_chk) Tj T* ET Q Q q -1 0 0 1 50.01575 92.90079 cm +1 0 0 1 50.01575 588.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46016,16 +46035,127 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 86.90079 cm +1 0 0 1 50.01575 582.1008 cm Q q -1 0 0 1 50.01575 68.90079 cm +1 0 0 1 50.01575 564.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMM_Code_Chk_En) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 50.01575 558.1008 cm +Q +q +1 0 0 1 50.01575 540.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 516.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 510.1008 cm +Q +q +1 0 0 1 50.01575 492.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 442.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm_dma module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 376.5008 cm +q +BT 1 0 0 1 0 50 Tm 12 TL /F1 10 Tf 0 0 0 rg (Just like SMRAM needs to be protected from software executing on the CPU, it also needs to be protected from) Tj T* (devices that have direct access to DRAM \(DMA\). Protection from DMA is configured through proper programming of) Tj T* (SMRAM memory range. If BIOS does not correctly configure and lock the configuration, then malware could) Tj T* (reprogram configuration and open SMRAM area to DMA access, allowing manipulation of memory that should have) Tj T* (been protected.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 322.5008 cm +q +BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (DMA attacks were discussed in ) Tj 0 0 .501961 rg (Programmed I/O accesses: a threat to Virtual Machine Monitors?) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (System) Tj T* (Management Mode Design and Security Issues) Tj 0 0 0 rg (. This is also discussed in ) Tj /F4 10 Tf (Summary of Attack against BIOS and) Tj T* (Secure Boot) Tj /F1 10 Tf ( ) Tj 0 0 .501961 rg (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DE) Tj T* (FCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 292.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL -0.136619 Tw (This module examines the configuration and locking of SMRAM range configuration protecting from DMA attacks. If it) Tj T* 0 Tw (fails, then DMA protection may not be securely configured to protect SMRAM.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 286.5008 cm +Q +q +1 0 0 1 40.01575 268.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm_dma) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 256.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 250.5008 cm +Q +q +1 0 0 1 50.01575 232.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_tseg_config) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 226.5008 cm +Q +q +1 0 0 1 50.01575 208.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_tseg_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 202.5008 cm +Q +q +1 0 0 1 50.01575 184.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 160.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 154.5008 cm +Q +q +1 0 0 1 50.01575 136.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -46043,217 +46173,9 @@ Q endstream endobj -1318 0 obj +1315 0 obj << -/Length 6330 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 739.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 666.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm_dma module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 600.1008 cm -q -BT 1 0 0 1 0 50 Tm 12 TL /F1 10 Tf 0 0 0 rg (Just like SMRAM needs to be protected from software executing on the CPU, it also needs to be protected from) Tj T* (devices that have direct access to DRAM \(DMA\). Protection from DMA is configured through proper programming of) Tj T* (SMRAM memory range. If BIOS does not correctly configure and lock the configuration, then malware could) Tj T* (reprogram configuration and open SMRAM area to DMA access, allowing manipulation of memory that should have) Tj T* (been protected.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 546.1008 cm -q -BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (DMA attacks were discussed in ) Tj 0 0 .501961 rg (Programmed I/O accesses: a threat to Virtual Machine Monitors?) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (System) Tj T* (Management Mode Design and Security Issues) Tj 0 0 0 rg (. This is also discussed in ) Tj /F4 10 Tf (Summary of Attack against BIOS and) Tj T* (Secure Boot) Tj /F1 10 Tf ( ) Tj 0 0 .501961 rg (https://www.defcon.org/images/defcon-22/dc-22-presentations/Bulygin-Bazhaniul-Furtak-Loucaides/DE) Tj T* (FCON-22-Bulygin-Bazhaniul-Furtak-Loucaides-Summary-of-attacks-against-BIOS-UPDATED.pdf) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 516.1008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL -0.136619 Tw (This module examines the configuration and locking of SMRAM range configuration protecting from DMA attacks. If it) Tj T* 0 Tw (fails, then DMA protection may not be securely configured to protect SMRAM.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 510.1008 cm -Q -q -1 0 0 1 40.01575 492.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm_dma) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 480.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 474.1008 cm -Q -q -1 0 0 1 50.01575 456.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_tseg_config) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 450.1008 cm -Q -q -1 0 0 1 50.01575 432.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_tseg_locks) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 426.1008 cm -Q -q -1 0 0 1 50.01575 408.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 384.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 378.1008 cm -Q -q -1 0 0 1 50.01575 360.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 310.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smrr module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 232.5008 cm -q -BT 1 0 0 1 0 62 Tm 12 TL /F1 10 Tf 0 0 0 rg (Researchers demonstrated a way to use CPU cache to effectively change values in SMRAM in ) Tj 0 0 .501961 rg (Attacking SMM) Tj T* (Memory via Intel CPU Cache Poisoning) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (Getting into the SMRAM: SMM Reloaded) Tj 0 0 0 rg ( . If ring 0 software can make) Tj T* (SMRAM cacheable and then populate cache lines at SMBASE with exploit code, then when an SMI is triggered, the) Tj T* (CPU could execute the exploit code from cache. System Management Mode Range Registers \(SMRRs\) force) Tj T* (non-cachable behavior and block access to SMRAM when the CPU is not in SMM. These registers need to be) Tj T* (enabled/configured by the BIOS.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 214.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks to see that SMRRs are enabled and configured.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 208.5008 cm -Q -q -1 0 0 1 40.01575 190.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smrr) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 178.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 172.5008 cm -Q -q -1 0 0 1 50.01575 154.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 148.5008 cm -Q -q -1 0 0 1 50.01575 130.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 106.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 100.5008 cm -Q -q -1 0 0 1 50.01575 82.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (114) Tj T* ET -Q -Q - -endstream -endobj -1319 0 obj -<< -/Length 6390 +/Length 6326 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET @@ -46266,41 +46188,116 @@ q n -10 0 525.2441 15.6 re B* Q q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smrr module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 688.1008 cm +q +BT 1 0 0 1 0 62 Tm 12 TL /F1 10 Tf 0 0 0 rg (Researchers demonstrated a way to use CPU cache to effectively change values in SMRAM in ) Tj 0 0 .501961 rg (Attacking SMM) Tj T* (Memory via Intel CPU Cache Poisoning) Tj 0 0 0 rg ( and ) Tj 0 0 .501961 rg (Getting into the SMRAM: SMM Reloaded) Tj 0 0 0 rg ( . If ring 0 software can make) Tj T* (SMRAM cacheable and then populate cache lines at SMBASE with exploit code, then when an SMI is triggered, the) Tj T* (CPU could execute the exploit code from cache. System Management Mode Range Registers \(SMRRs\) force) Tj T* (non-cachable behavior and block access to SMRAM when the CPU is not in SMM. These registers need to be) Tj T* (enabled/configured by the BIOS.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 670.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks to see that SMRRs are enabled and configured.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 664.1008 cm +Q +q +1 0 0 1 40.01575 646.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smrr) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 634.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 628.1008 cm +Q +q +1 0 0 1 50.01575 610.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_SMRR) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (do_modify) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 604.1008 cm +Q +q +1 0 0 1 50.01575 586.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 562.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 556.1008 cm +Q +q +1 0 0 1 50.01575 538.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 488.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spd_wd module) Tj T* ET Q Q q -1 0 0 1 40.01575 748.1008 cm +1 0 0 1 40.01575 470.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks that SPD Write Disable bit in SMBus controller has been set) Tj T* ET Q Q q -1 0 0 1 40.01575 730.1008 cm +1 0 0 1 40.01575 452.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET Q Q q -1 0 0 1 40.01575 700.1008 cm +1 0 0 1 40.01575 422.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Intel 8 Series/C220 Series Chipset Family Platform Controller Hub datasheet Intel 300 Series Chipset Families) Tj T* (Platform Controller Hub datasheet) Tj T* ET Q Q q -1 0 0 1 40.01575 682.1008 cm +1 0 0 1 40.01575 404.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks the following:) Tj T* ET Q Q q -1 0 0 1 40.01575 676.1008 cm +1 0 0 1 40.01575 398.5008 cm Q q -1 0 0 1 40.01575 664.1008 cm +1 0 0 1 40.01575 386.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -46317,20 +46314,20 @@ Q Q Q q -1 0 0 1 40.01575 664.1008 cm +1 0 0 1 40.01575 386.5008 cm Q q -1 0 0 1 40.01575 646.1008 cm +1 0 0 1 40.01575 368.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The module returns the following results:) Tj T* ET Q Q q -1 0 0 1 40.01575 640.1008 cm +1 0 0 1 40.01575 362.5008 cm Q q -1 0 0 1 40.01575 592.1008 cm +1 0 0 1 40.01575 314.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -46361,20 +46358,20 @@ Q Q Q q -1 0 0 1 40.01575 592.1008 cm +1 0 0 1 40.01575 314.5008 cm Q q -1 0 0 1 40.01575 574.1008 cm +1 0 0 1 40.01575 296.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Hardware registers used:) Tj T* ET Q Q q -1 0 0 1 40.01575 568.1008 cm +1 0 0 1 40.01575 290.5008 cm Q q -1 0 0 1 40.01575 556.1008 cm +1 0 0 1 40.01575 278.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -46391,19 +46388,19 @@ Q Q Q q -1 0 0 1 40.01575 556.1008 cm +1 0 0 1 40.01575 278.5008 cm Q q -1 0 0 1 40.01575 550.1008 cm +1 0 0 1 40.01575 272.5008 cm Q q -1 0 0 1 40.01575 532.1008 cm +1 0 0 1 40.01575 254.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spd_wd) Tj T* ET Q Q q -1 0 0 1 50.01575 520.1008 cm +1 0 0 1 50.01575 242.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46411,40 +46408,40 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 514.1008 cm +1 0 0 1 50.01575 236.5008 cm Q q -1 0 0 1 50.01575 496.1008 cm +1 0 0 1 50.01575 218.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_spd_wd) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 490.1008 cm +1 0 0 1 50.01575 212.5008 cm Q q -1 0 0 1 50.01575 472.1008 cm +1 0 0 1 50.01575 194.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 448.1008 cm +1 0 0 1 60.01575 170.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 442.1008 cm +1 0 0 1 50.01575 164.5008 cm Q q -1 0 0 1 50.01575 424.1008 cm +1 0 0 1 50.01575 146.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 374.5008 cm +1 0 0 1 40.01575 96.90079 cm q 1 1 1 RG .3 w @@ -46456,22 +46453,44 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_access module) Tj T* ET Q Q q -1 0 0 1 40.01575 356.5008 cm +1 0 0 1 40.01575 78.90079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks SPI Flash Region Access Permissions programmed in the Flash Descriptor) Tj T* ET Q Q q -1 0 0 1 40.01575 350.5008 cm +1 0 0 1 40.01575 72.90079 cm Q q -1 0 0 1 40.01575 332.5008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (114) Tj T* ET +Q +Q + +endstream +endobj +1316 0 obj +<< +/Length 6165 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spi_access) Tj T* ET Q Q q -1 0 0 1 50.01575 320.5008 cm +1 0 0 1 50.01575 751.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46479,40 +46498,40 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 314.5008 cm +1 0 0 1 50.01575 745.7008 cm Q q -1 0 0 1 50.01575 296.5008 cm +1 0 0 1 50.01575 727.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_flash_access_permissions) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 290.5008 cm +1 0 0 1 50.01575 721.7008 cm Q q -1 0 0 1 50.01575 272.5008 cm +1 0 0 1 50.01575 703.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 248.5008 cm +1 0 0 1 60.01575 679.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 242.5008 cm +1 0 0 1 50.01575 673.7008 cm Q q -1 0 0 1 50.01575 224.5008 cm +1 0 0 1 50.01575 655.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 174.9008 cm +1 0 0 1 40.01575 606.1008 cm q 1 1 1 RG .3 w @@ -46524,29 +46543,29 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_desc module) Tj T* ET Q Q q -1 0 0 1 40.01575 120.9008 cm +1 0 0 1 40.01575 552.1008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (The SPI Flash Descriptor indicates read/write permissions for devices to access regions of the flash memory. This) Tj T* (module simply reads the Flash Descriptor and checks that software cannot modify the Flash Descriptor itself. If) Tj T* (software can write to the Flash Descriptor, then software could bypass any protection defined by it. While often used) Tj T* (for debugging, this should not be the case on production systems.) Tj T* ET Q Q q -1 0 0 1 40.01575 102.9008 cm +1 0 0 1 40.01575 534.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks that software cannot write to the flash descriptor.) Tj T* ET Q Q q -1 0 0 1 40.01575 96.90079 cm +1 0 0 1 40.01575 528.1008 cm Q q -1 0 0 1 40.01575 78.90079 cm +1 0 0 1 40.01575 510.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spi_desc) Tj T* ET Q Q q -1 0 0 1 50.01575 66.90079 cm +1 0 0 1 50.01575 498.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46554,7 +46573,129 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 50.01575 492.1008 cm +Q +q +1 0 0 1 50.01575 474.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_flash_access_permissions) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 468.1008 cm +Q +q +1 0 0 1 50.01575 450.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 426.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 420.1008 cm +Q +q +1 0 0 1 50.01575 402.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 352.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_fdopss module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 322.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks for SPI Controller Flash Descriptor Security Override Pin Strap \(FDOPSS\). On some systems, this may be) Tj T* (routed to a jumper on the motherboard.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 316.5008 cm +Q +q +1 0 0 1 40.01575 298.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spi_fdopss) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 286.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 280.5008 cm +Q +q +1 0 0 1 50.01575 262.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_fd_security_override_strap) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 256.5008 cm +Q +q +1 0 0 1 50.01575 238.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 214.5008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 208.5008 cm +Q +q +1 0 0 1 50.01575 190.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 140.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_lock module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 110.9008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The configuration of the SPI controller, including protected ranges \(PR0-PR4\), is locked by HSFS[FLOCKDN] until) Tj T* (reset. If not locked, the controller configuration may be bypassed by reprogramming these registers.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 68.90079 cm +q +BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (This vulnerability \(not setting FLOCKDN\) is also checked by other tools, including ) Tj 0 0 .501961 rg (flashrom) Tj 0 0 0 rg ( and Copernicus by) Tj T* (MITRE \(ref: ) Tj /F4 10 Tf (Copernicus: Question Your Assumptions about BIOS Security) Tj /F1 10 Tf ( ) Tj 0 0 .501961 rg (http://www.mitre.org/capabilities/cybersec) Tj T* (urity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) Tj 0 0 0 rg (\).) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -46572,152 +46713,30 @@ Q endstream endobj -1320 0 obj +1317 0 obj << -/Length 6170 +/Length 4763 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_flash_access_permissions) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 715.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 642.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_fdopss module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 612.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Checks for SPI Controller Flash Descriptor Security Override Pin Strap \(FDOPSS\). On some systems, this may be) Tj T* (routed to a jumper on the motherboard.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 606.1008 cm -Q -q -1 0 0 1 40.01575 588.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spi_fdopss) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 576.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 570.1008 cm -Q -q -1 0 0 1 50.01575 552.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_fd_security_override_strap) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 546.1008 cm -Q -q -1 0 0 1 50.01575 528.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 504.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 498.1008 cm -Q -q -1 0 0 1 50.01575 480.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 430.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (spi_lock module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 400.5008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The configuration of the SPI controller, including protected ranges \(PR0-PR4\), is locked by HSFS[FLOCKDN] until) Tj T* (reset. If not locked, the controller configuration may be bypassed by reprogramming these registers.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 358.5008 cm -q -BT 1 0 0 1 0 26 Tm 12 TL /F1 10 Tf 0 0 0 rg (This vulnerability \(not setting FLOCKDN\) is also checked by other tools, including ) Tj 0 0 .501961 rg (flashrom) Tj 0 0 0 rg ( and Copernicus by) Tj T* (MITRE \(ref: ) Tj /F4 10 Tf (Copernicus: Question Your Assumptions about BIOS Security) Tj /F1 10 Tf ( ) Tj 0 0 .501961 rg (http://www.mitre.org/capabilities/cybersec) Tj T* (urity/overview/cybersecurity-blog/copernicus-question-your-assumptions-about) Tj 0 0 0 rg (\).) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 340.5008 cm +1 0 0 1 40.01575 763.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module checks that the SPI Flash Controller configuration is locked.) Tj T* ET Q Q q -1 0 0 1 40.01575 334.5008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 40.01575 316.5008 cm +1 0 0 1 40.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (spi_lock) Tj T* ET Q Q q -1 0 0 1 50.01575 304.5008 cm +1 0 0 1 50.01575 727.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46725,40 +46744,40 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 298.5008 cm +1 0 0 1 50.01575 721.7008 cm Q q -1 0 0 1 50.01575 280.5008 cm +1 0 0 1 50.01575 703.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_spi_lock) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 274.5008 cm +1 0 0 1 50.01575 697.7008 cm Q q -1 0 0 1 50.01575 256.5008 cm +1 0 0 1 50.01575 679.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 232.5008 cm +1 0 0 1 60.01575 655.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 226.5008 cm +1 0 0 1 50.01575 649.7008 cm Q q -1 0 0 1 50.01575 208.5008 cm +1 0 0 1 50.01575 631.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 158.9008 cm +1 0 0 1 40.01575 582.1008 cm q 1 1 1 RG .3 w @@ -46770,22 +46789,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (wsmt module) Tj T* ET Q Q q -1 0 0 1 40.01575 104.9008 cm +1 0 0 1 40.01575 528.1008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (The Windows SMM Security Mitigation Table \(WSMT\) is an ACPI table defined by Microsoft that allows system) Tj T* (firmware to confirm to the operating system that certain security best practices have been implemented in System) Tj T* (Management Mode \(SMM\) software. See) Tj T* (<) Tj 0 0 .501961 rg (https://docs.microsoft.com/en-us/windows-hardware/design/device-experiences/oem-uefi-wsmt) Tj 0 0 0 rg (> for more details.) Tj T* ET Q Q q -1 0 0 1 40.01575 98.90079 cm +1 0 0 1 40.01575 522.1008 cm Q q -1 0 0 1 40.01575 80.90079 cm +1 0 0 1 40.01575 504.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (wsmt) Tj T* ET Q Q q -1 0 0 1 50.01575 68.90079 cm +1 0 0 1 50.01575 492.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46793,7 +46812,116 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 66.18898 cm +1 0 0 1 50.01575 486.1008 cm +Q +q +1 0 0 1 50.01575 468.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_wsmt) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 462.1008 cm +Q +q +1 0 0 1 50.01575 444.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 420.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 414.1008 cm +Q +q +1 0 0 1 50.01575 396.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 346.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hsw package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 296.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ivb package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 247.3008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (snb package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 197.7008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (tools package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 148.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +1 1 1 rg +BT 1 0 0 1 0 1.6 Tm /F5 8 Tf 9.6 TL (cpu package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 98.50079 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (sinkhole module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 80.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if CPU is affected by \221The SMM memory sinkhole\222 vulnerability by Christopher Domas) Tj T* ET +Q Q q 1 0 0 1 34.01575 795.874 cm @@ -46811,152 +46939,43 @@ Q endstream endobj -1321 0 obj +1318 0 obj << -/Length 4484 +/Length 8174 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_wsmt) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 715.7008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 709.7008 cm -Q -q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 642.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hsw package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 592.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ivb package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 542.9008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (snb package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 493.3008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (tools package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 443.7008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -1 1 1 rg -BT 1 0 0 1 0 1.6 Tm /F5 8 Tf 9.6 TL (cpu package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 394.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (sinkhole module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 376.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks if CPU is affected by \221The SMM memory sinkhole\222 vulnerability by Christopher Domas) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 346.1008 cm +1 0 0 1 40.01575 751.7008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (NOTE: The system may hang when running this test. In that case, the mitigation to this issue is likely working but we) Tj T* (may not be handling the exception generated.) Tj T* ET Q Q q -1 0 0 1 40.01575 328.1008 cm +1 0 0 1 40.01575 733.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (References:) Tj T* ET Q Q q -1 0 0 1 40.01575 274.1008 cm +1 0 0 1 40.01575 679.7008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (The Memory Sinkhole by Christopher Domas: ) Tj 0 0 .501961 rg (https://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Me) Tj T* (mory-Sinkhole-Unleashing-An-x86-Design-Flaw-Allowing-Universal-Privilege-Escalation.pdf) Tj 0 0 0 rg ( \(presentation\) and ) Tj 0 0 .501961 rg (https) Tj T* (://www.blackhat.com/docs/us-15/materials/us-15-Domas-The-Memory-Sinkhole-Unleashing-An-x86-Design-Flaw-All) Tj T* (owing-Universal-Privilege-Escalation-wp.pdf) Tj 0 0 0 rg ( \(whitepaper\).) Tj T* ET Q Q q -1 0 0 1 40.01575 268.1008 cm +1 0 0 1 40.01575 673.7008 cm Q q -1 0 0 1 40.01575 250.1008 cm +1 0 0 1 40.01575 655.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (sinkhole) Tj T* ET Q Q q -1 0 0 1 50.01575 238.1008 cm +1 0 0 1 50.01575 643.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -46964,62 +46983,40 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 232.1008 cm +1 0 0 1 50.01575 637.7008 cm Q q -1 0 0 1 50.01575 214.1008 cm +1 0 0 1 50.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_LAPIC_SMRR_overlap) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 208.1008 cm +1 0 0 1 50.01575 613.7008 cm Q q -1 0 0 1 50.01575 190.1008 cm +1 0 0 1 50.01575 595.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 166.1008 cm +1 0 0 1 60.01575 571.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 160.1008 cm +1 0 0 1 50.01575 565.7008 cm Q q -1 0 0 1 50.01575 142.1008 cm +1 0 0 1 50.01575 547.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (117) Tj T* ET -Q -Q - -endstream -endobj -1322 0 obj -<< -/Length 8951 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 766.1008 cm +1 0 0 1 40.01575 498.1008 cm q 1 1 1 RG .3 w @@ -47031,7 +47028,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (secureboot package) Tj T* ET Q Q q -1 0 0 1 40.01575 716.5008 cm +1 0 0 1 40.01575 448.5008 cm q 1 1 1 RG .3 w @@ -47043,20 +47040,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (te module) Tj T* ET Q Q q -1 0 0 1 40.01575 686.5008 cm +1 0 0 1 40.01575 418.5008 cm q BT 1 0 0 1 0 14 Tm -0.0861 Tw 12 TL /F1 10 Tf 0 0 0 rg (Tool to test for \221TE Header\222 vulnerability in Secure Boot implementations as described in ) Tj 0 0 .501961 rg (All Your Boot Are Belong To) Tj T* 0 Tw (Us) Tj T* ET Q Q q -1 0 0 1 40.01575 670.5008 cm +1 0 0 1 40.01575 402.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 514.5008 cm +1 0 0 1 40.01575 246.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47260,24 +47257,24 @@ Q Q Q q -1 0 0 1 40.01575 496.5008 cm +1 0 0 1 40.01575 228.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 478.5008 cm +1 0 0 1 40.01575 210.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Convert Shell.efi PE/COFF EFI executable to TE executable:) Tj T* ET Q Q q -1 0 0 1 40.01575 472.5008 cm +1 0 0 1 40.01575 204.5008 cm Q q -1 0 0 1 40.01575 460.5008 cm +1 0 0 1 40.01575 192.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47293,20 +47290,20 @@ Q Q Q q -1 0 0 1 40.01575 460.5008 cm +1 0 0 1 40.01575 192.5008 cm Q q -1 0 0 1 40.01575 442.5008 cm +1 0 0 1 40.01575 174.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Replace bootloaders listed in te.cfg file with TE version of Shell.efi executable:) Tj T* ET Q Q q -1 0 0 1 40.01575 436.5008 cm +1 0 0 1 40.01575 168.5008 cm Q q -1 0 0 1 40.01575 424.5008 cm +1 0 0 1 40.01575 156.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47322,20 +47319,20 @@ Q Q Q q -1 0 0 1 40.01575 424.5008 cm +1 0 0 1 40.01575 156.5008 cm Q q -1 0 0 1 40.01575 406.5008 cm +1 0 0 1 40.01575 138.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Restore bootloaders listed in te.cfg file:) Tj T* ET Q Q q -1 0 0 1 40.01575 400.5008 cm +1 0 0 1 40.01575 132.5008 cm Q q -1 0 0 1 40.01575 388.5008 cm +1 0 0 1 40.01575 120.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47351,123 +47348,28 @@ Q Q Q q -1 0 0 1 40.01575 388.5008 cm +1 0 0 1 40.01575 120.5008 cm Q q -1 0 0 1 40.01575 382.5008 cm +1 0 0 1 40.01575 114.5008 cm Q q -1 0 0 1 40.01575 364.5008 cm +1 0 0 1 40.01575 96.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (IsValidPEHeader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 358.5008 cm +1 0 0 1 40.01575 90.50079 cm Q q -1 0 0 1 40.01575 340.5008 cm +1 0 0 1 40.01575 72.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (confirm) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 334.5008 cm -Q -q -1 0 0 1 40.01575 316.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_bootloader_paths) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (cfg_file) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 310.5008 cm -Q -q -1 0 0 1 40.01575 292.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_efi_mount) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 286.5008 cm -Q -q -1 0 0 1 40.01575 268.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (produce_te) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (fname) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (outfname) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 262.5008 cm -Q -q -1 0 0 1 40.01575 244.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_bootloader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (bootloader_paths) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (new_bootloader_file) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (do_mount) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 238.5008 cm -Q -q -1 0 0 1 40.01575 220.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_efi_binary) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (orig_efi_binary) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (new_efi_binary) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 214.5008 cm -Q -q -1 0 0 1 40.01575 196.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_header) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 190.5008 cm -Q -q -1 0 0 1 40.01575 172.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (restore_bootloader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (bootloader_paths) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (do_mount) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 166.5008 cm -Q -q -1 0 0 1 40.01575 148.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (restore_efi_binary) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (orig_efi_binary) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 142.5008 cm -Q -q -1 0 0 1 40.01575 124.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (te) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 112.5008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 106.5008 cm -Q -q -1 0 0 1 50.01575 88.50079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q +1 0 0 1 40.01575 66.50079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -47479,53 +47381,148 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (118) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (117) Tj T* ET Q Q endstream endobj -1323 0 obj +1319 0 obj << -/Length 9170 +/Length 7901 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 60.01575 751.7008 cm +1 0 0 1 40.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_bootloader_paths) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (cfg_file) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 757.7008 cm +Q +q +1 0 0 1 40.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_efi_mount) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 733.7008 cm +Q +q +1 0 0 1 40.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (produce_te) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (fname) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (outfname) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 709.7008 cm +Q +q +1 0 0 1 40.01575 691.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_bootloader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (bootloader_paths) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (new_bootloader_file) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (do_mount) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 685.7008 cm +Q +q +1 0 0 1 40.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_efi_binary) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (orig_efi_binary) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (new_efi_binary) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 661.7008 cm +Q +q +1 0 0 1 40.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (replace_header) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (data) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 637.7008 cm +Q +q +1 0 0 1 40.01575 619.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (restore_bootloader) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (bootloader_paths) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (do_mount) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 613.7008 cm +Q +q +1 0 0 1 40.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (restore_efi_binary) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (orig_efi_binary) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 589.7008 cm +Q +q +1 0 0 1 40.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (te) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 559.7008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 553.7008 cm +Q +q +1 0 0 1 50.01575 535.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 511.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 745.7008 cm +1 0 0 1 50.01575 505.7008 cm Q q -1 0 0 1 50.01575 727.7008 cm +1 0 0 1 50.01575 487.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 721.7008 cm +1 0 0 1 40.01575 481.7008 cm Q q -1 0 0 1 40.01575 703.7008 cm +1 0 0 1 40.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (umount) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (drive) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 697.7008 cm +1 0 0 1 40.01575 457.7008 cm Q q -1 0 0 1 40.01575 679.7008 cm +1 0 0 1 40.01575 439.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 630.1008 cm +1 0 0 1 40.01575 390.1008 cm q 1 1 1 RG .3 w @@ -47537,7 +47534,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm package) Tj T* ET Q Q q -1 0 0 1 40.01575 580.5008 cm +1 0 0 1 40.01575 340.5008 cm q 1 1 1 RG .3 w @@ -47549,26 +47546,26 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (rogue_mmio_bar module) Tj T* ET Q Q q -1 0 0 1 40.01575 550.5008 cm +1 0 0 1 40.01575 310.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Experimental module that may help checking SMM firmware for MMIO BAR hijacking vulnerabilities described in the) Tj T* (following presentation:) Tj T* ET Q Q q -1 0 0 1 40.01575 520.5008 cm +1 0 0 1 40.01575 280.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 .501961 rg (BARing the System: New vulnerabilities in Coreboot & UEFI based systems) Tj 0 0 0 rg ( by Intel Advanced Threat Research) Tj T* (team at RECon Brussels 2017) Tj T* ET Q Q q -1 0 0 1 40.01575 504.5008 cm +1 0 0 1 40.01575 264.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 489.5008 cm +1 0 0 1 40.01575 249.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47584,13 +47581,13 @@ Q Q Q q -1 0 0 1 40.01575 483.5008 cm +1 0 0 1 40.01575 243.5008 cm Q q -1 0 0 1 40.01575 483.5008 cm +1 0 0 1 40.01575 243.5008 cm Q q -1 0 0 1 40.01575 471.5008 cm +1 0 0 1 40.01575 231.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47612,10 +47609,10 @@ Q Q Q q -1 0 0 1 40.01575 465.5008 cm +1 0 0 1 40.01575 225.5008 cm Q q -1 0 0 1 40.01575 453.5008 cm +1 0 0 1 40.01575 213.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47637,17 +47634,17 @@ Q Q Q q -1 0 0 1 40.01575 453.5008 cm +1 0 0 1 40.01575 213.5008 cm Q q -1 0 0 1 40.01575 437.5008 cm +1 0 0 1 40.01575 197.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Example:) Tj T* ET Q Q q -1 0 0 1 40.01575 408.5008 cm +1 0 0 1 40.01575 168.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47677,25 +47674,25 @@ Q Q Q q -1 0 0 1 40.01575 402.5008 cm +1 0 0 1 40.01575 162.5008 cm Q q -1 0 0 1 40.01575 384.5008 cm +1 0 0 1 40.01575 144.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DIFF) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (t) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (sz) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 378.5008 cm +1 0 0 1 40.01575 138.5008 cm Q q -1 0 0 1 40.01575 360.5008 cm +1 0 0 1 40.01575 120.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (rogue_mmio_bar) Tj T* ET Q Q q -1 0 0 1 50.01575 348.5008 cm +1 0 0 1 50.01575 108.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -47703,52 +47700,74 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 342.5008 cm +1 0 0 1 50.01575 102.5008 cm Q q -1 0 0 1 50.01575 324.5008 cm +1 0 0 1 50.01575 84.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (copy_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_base_mem) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 318.5008 cm +1 0 0 1 50.01575 78.50079 cm Q q -1 0 0 1 50.01575 300.5008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (118) Tj T* ET +Q +Q + +endstream +endobj +1320 0 obj +<< +/Length 10830 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (b) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (d) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (f) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_bar) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 294.5008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 276.5008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (restore_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (b) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (d) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (f) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 270.5008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 252.5008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 246.5008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 228.5008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (smi_mmio_range_fuzz) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (b) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (d) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (f) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar_off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 178.9008 cm +1 0 0 1 40.01575 642.1008 cm q 1 1 1 RG .3 w @@ -47760,65 +47779,65 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (smm_ptr module) Tj T* ET Q Q q -1 0 0 1 40.01575 160.9008 cm +1 0 0 1 40.01575 624.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (CanSecWest 2015 ) Tj 0 0 .501961 rg (A New Class of Vulnerability in SMI Handlers of BIOS/UEFI Firmware) Tj T* ET Q Q q -1 0 0 1 40.01575 142.9008 cm +1 0 0 1 40.01575 606.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (A tool to test SMI handlers for pointer validation vulnerabilities) Tj T* ET Q Q q -1 0 0 1 40.01575 112.9008 cm +1 0 0 1 40.01575 576.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Usage: ) Tj /F3 10 Tf (chipsec_main) Tj ( ) Tj (-m) Tj ( ) Tj (tools.smm.smm_ptr) Tj ( ) Tj (-l) Tj ( ) Tj (log.txt) Tj ( ) Tj (\\) Tj /F1 10 Tf T* /F3 10 Tf ([-a) Tj ( ) Tj (<) Tj (mode) Tj (>) Tj (,) Tj (<) Tj (config_file) Tj (>) Tj (|) Tj (<) Tj (smic_start:smic_end) Tj (>) Tj (,) Tj (<) Tj (size) Tj (>) Tj (,) Tj (<) Tj (address) Tj (>) Tj (]) Tj T* ET Q Q q -1 0 0 1 40.01575 106.9008 cm +1 0 0 1 40.01575 570.1008 cm Q q -1 0 0 1 40.01575 106.9008 cm +1 0 0 1 40.01575 570.1008 cm Q q -1 0 0 1 40.01575 66.18898 cm +1 0 0 1 40.01575 498.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET q -1 0 0 1 6 25.71181 cm +1 0 0 1 6 57 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET Q Q q -1 0 0 1 23 25.71181 cm +1 0 0 1 23 57 cm q BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (mode) Tj /F1 10 Tf (: SMI fuzzing mode) Tj T* ET Q Q q -1 0 0 1 23 19.71181 cm +1 0 0 1 23 51 cm Q q -1 0 0 1 23 1.711811 cm +1 0 0 1 23 -3 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET BT 1 0 0 1 0 2 Tm T* ET q -1 0 0 1 20 12 cm +1 0 0 1 20 48 cm Q q -1 0 0 1 20 12 cm +1 0 0 1 20 48 cm Q q -1 0 0 1 20 0 cm +1 0 0 1 20 36 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47840,48 +47859,6 @@ Q Q Q q -Q -Q -Q -q -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (119) Tj T* ET -Q -Q - -endstream -endobj -1324 0 obj -<< -/Length 11027 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 739.7008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 6 23 Tm T* ET -q -1 0 0 1 23 -3 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q 1 0 0 1 20 30 cm Q q @@ -47946,10 +47923,10 @@ Q Q Q q -1 0 0 1 40.01575 733.7008 cm +1 0 0 1 40.01575 492.1008 cm Q q -1 0 0 1 40.01575 721.7008 cm +1 0 0 1 40.01575 480.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -47971,10 +47948,10 @@ Q Q Q q -1 0 0 1 40.01575 715.7008 cm +1 0 0 1 40.01575 474.1008 cm Q q -1 0 0 1 40.01575 679.7008 cm +1 0 0 1 40.01575 438.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48043,16 +48020,16 @@ Q Q Q q -1 0 0 1 40.01575 679.7008 cm +1 0 0 1 40.01575 438.1008 cm Q q -1 0 0 1 40.01575 661.7008 cm +1 0 0 1 40.01575 420.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (In ) Tj /F3 10 Tf (config) Tj /F1 10 Tf ( mode, SMI configuration file should have the following format) Tj T* ET Q Q q -1 0 0 1 40.01575 530.1008 cm +1 0 0 1 40.01575 288.5008 cm q q 1 0 0 1 0 0 cm @@ -48072,20 +48049,20 @@ Q Q Q q -1 0 0 1 40.01575 510.1008 cm +1 0 0 1 40.01575 268.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Where) Tj T* ET Q Q q -1 0 0 1 40.01575 504.1008 cm +1 0 0 1 40.01575 262.5008 cm Q q -1 0 0 1 40.01575 504.1008 cm +1 0 0 1 40.01575 262.5008 cm Q q -1 0 0 1 40.01575 492.1008 cm +1 0 0 1 40.01575 250.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48107,10 +48084,10 @@ Q Q Q q -1 0 0 1 40.01575 486.1008 cm +1 0 0 1 40.01575 244.5008 cm Q q -1 0 0 1 40.01575 474.1008 cm +1 0 0 1 40.01575 232.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48132,10 +48109,10 @@ Q Q Q q -1 0 0 1 40.01575 468.1008 cm +1 0 0 1 40.01575 226.5008 cm Q q -1 0 0 1 40.01575 444.1008 cm +1 0 0 1 40.01575 202.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48157,10 +48134,10 @@ Q Q Q q -1 0 0 1 40.01575 438.1008 cm +1 0 0 1 40.01575 196.5008 cm Q q -1 0 0 1 40.01575 414.1008 cm +1 0 0 1 40.01575 172.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48182,54 +48159,37 @@ Q Q Q q -1 0 0 1 40.01575 414.1008 cm +1 0 0 1 40.01575 172.5008 cm Q q -1 0 0 1 40.01575 408.1008 cm +1 0 0 1 40.01575 166.5008 cm Q q -1 0 0 1 40.01575 390.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (exception ) Tj /F6 10 Tf (BadSMIDetected) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 378.1008 cm -q -.933333 1 .8 rg -n 33.35 0 72 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (RuntimeError) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 372.1008 cm -Q -q -1 0 0 1 40.01575 354.1008 cm +1 0 0 1 40.01575 148.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DIFF) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (s) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (t) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (sz) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 348.1008 cm +1 0 0 1 40.01575 142.5008 cm Q q -1 0 0 1 40.01575 330.1008 cm +1 0 0 1 40.01575 124.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (FILL_BUFFER) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (_fill_byte) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_fill_size) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_ptr_in_buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_ptr) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_ptr_offset) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_sig) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (_sig_offset) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 324.1008 cm +1 0 0 1 40.01575 118.5008 cm Q q -1 0 0 1 40.01575 306.1008 cm +1 0 0 1 40.01575 100.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smi_desc) Tj T* ET Q Q q -1 0 0 1 50.01575 294.1008 cm +1 0 0 1 50.01575 88.50079 cm q .933333 1 .8 rg n 33.35 0 36 12 re f* @@ -48237,84 +48197,7 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* Q Q q -1 0 0 1 40.01575 288.1008 cm -Q -q -1 0 0 1 40.01575 270.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm_ptr) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 258.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 252.1008 cm -Q -q -1 0 0 1 50.01575 234.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_smi_desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fn) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (restore_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 228.1008 cm -Q -q -1 0 0 1 50.01575 210.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fill_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is_ptr_in_buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_ptr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_ptr_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_sig) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_sig_offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 204.1008 cm -Q -q -1 0 0 1 50.01575 186.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 162.1008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 156.1008 cm -Q -q -1 0 0 1 50.01575 138.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 132.1008 cm -Q -q -1 0 0 1 50.01575 114.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smi_code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smi_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 108.1008 cm -Q -q -1 0 0 1 50.01575 90.10079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (smi_fuzz_iter) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_smi_desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fill_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (restore_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 84.10079 cm +1 0 0 1 40.01575 82.50079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -48326,35 +48209,112 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (120) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (119) Tj T* ET Q Q endstream endobj -1325 0 obj +1321 0 obj << -/Length 7062 +/Length 9374 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (smm_ptr) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 751.7008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 745.7008 cm +Q +q +1 0 0 1 50.01575 727.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_smi_desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fn) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (restore_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 721.7008 cm +Q +q +1 0 0 1 50.01575 703.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fill_memory) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is_ptr_in_buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_ptr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_ptr_offset) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_sig) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_sig_offset) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 697.7008 cm +Q +q +1 0 0 1 50.01575 679.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 655.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 649.7008 cm +Q +q +1 0 0 1 50.01575 631.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 625.7008 cm +Q +q +1 0 0 1 50.01575 607.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_smi) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smi_code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smi_data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rbx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rcx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rsi) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (rdi) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 601.7008 cm +Q +q +1 0 0 1 50.01575 583.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (smi_fuzz_iter) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_smi_desc) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fill_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (True) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (restore_contents) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 577.7008 cm +Q +q +1 0 0 1 50.01575 559.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (test_config) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_smi_config_fname) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 50.01575 535.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (test_fuzz) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (thread_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smic_start) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (smic_end) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (_addr1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 690.1008 cm +1 0 0 1 40.01575 486.1008 cm q 1 1 1 RG .3 w @@ -48366,7 +48326,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefi package) Tj T* ET Q Q q -1 0 0 1 40.01575 640.5008 cm +1 0 0 1 40.01575 436.5008 cm q 1 1 1 RG .3 w @@ -48378,27 +48338,27 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (reputation module) Tj T* ET Q Q q -1 0 0 1 40.01575 586.5008 cm +1 0 0 1 40.01575 382.5008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks current contents of UEFI firmware ROM or specified firmware image for bad EFI binaries as per) Tj T* -0.094465 Tw (the VirusTotal API. These can be EFI firmware volumes, EFI executable binaries \(PEI modules, DXE drivers..\) or EFI) Tj T* 0 Tw (sections. The module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes or contents) Tj T* (matching specified regular expressions.) Tj T* ET Q Q q -1 0 0 1 40.01575 568.5008 cm +1 0 0 1 40.01575 364.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Important! This module can only detect bad or vulnerable EFI modules based on the file\222s reputation on VT.) Tj T* ET Q Q q -1 0 0 1 40.01575 552.5008 cm +1 0 0 1 40.01575 348.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 433.5008 cm +1 0 0 1 40.01575 229.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -48493,16 +48453,16 @@ Q Q Q q -1 0 0 1 40.01575 427.5008 cm +1 0 0 1 40.01575 223.5008 cm Q q -1 0 0 1 40.01575 409.5008 cm +1 0 0 1 40.01575 205.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (reputation) Tj T* ET Q Q q -1 0 0 1 50.01575 397.5008 cm +1 0 0 1 50.01575 193.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -48510,117 +48470,49 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 391.5008 cm +1 0 0 1 50.01575 187.5008 cm Q q -1 0 0 1 50.01575 373.5008 cm +1 0 0 1 50.01575 169.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_reputation) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 367.5008 cm +1 0 0 1 50.01575 163.5008 cm Q q -1 0 0 1 50.01575 349.5008 cm +1 0 0 1 50.01575 145.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 325.5008 cm +1 0 0 1 60.01575 121.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 319.5008 cm +1 0 0 1 50.01575 115.5008 cm Q q -1 0 0 1 50.01575 301.5008 cm +1 0 0 1 50.01575 97.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (reputation_callback) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_module) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 295.5008 cm +1 0 0 1 50.01575 91.50079 cm Q q -1 0 0 1 50.01575 277.5008 cm +1 0 0 1 50.01575 73.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 271.5008 cm -Q -q -1 0 0 1 50.01575 253.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 203.9008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (s3script_modify module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 173.9008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module will attempt to modify the S3 Boot Script on the platform. Doing this could cause the platform to) Tj T* (malfunction. Use with care!) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 157.9008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 66.18898 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 78.71181 Tm T* ET -q -1 0 0 1 20 76.71181 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Replacing existing opcode:) Tj T* ET -Q -Q -q -1 0 0 1 20 12.31181 cm -q -q -1 0 0 1 0 0 cm -q -1 0 0 1 4.4 .4 cm -q -.666667 .8 .6 RG -.3 w -.933333 1 .8 rg -n -4 0 488.4441 63.6 re B* -Q -q -BT 1 0 0 1 0 49.6 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,) Tj (<) Tj (reg_opcode) Tj (>) Tj (,) Tj (<) Tj (address) Tj (>) Tj (,) Tj (<) Tj (value) Tj (>) Tj T* ( ) Tj (<) Tj (reg_opcode) Tj (>) Tj ( = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw) Tj T* T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem[,) Tj (<) Tj (address) Tj (>) Tj (,) Tj (<) Tj (value) Tj (>) Tj (]) Tj T* T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch``) Tj T* ET -Q -Q -Q -Q -Q -q -Q -Q +1 0 0 1 50.01575 67.50079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -48632,24 +48524,62 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (121) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (120) Tj T* ET Q Q endstream endobj -1326 0 obj +1322 0 obj << -/Length 7439 +/Length 7269 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 675.5008 cm +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 714.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (s3script_modify module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 684.1008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module will attempt to modify the S3 Boot Script on the platform. Doing this could cause the platform to) Tj T* (malfunction. Use with care!) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 668.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 498.3008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 87.2 Tm T* ET +BT 1 0 0 1 0 156.8 Tm T* ET +q +1 0 0 1 20 154.8 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Replacing existing opcode:) Tj T* ET +Q +Q q 1 0 0 1 20 71.2 cm q @@ -48661,10 +48591,10 @@ q .666667 .8 .6 RG .3 w .933333 1 .8 rg -n -4 0 488.4441 25.2 re B* +n -4 0 494.4441 82.8 re B* Q q -BT 1 0 0 1 0 11.2 Tm 9.6 TL /F3 8 Tf 0 0 0 rg T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep``) Tj T* ET +BT 1 0 0 1 0 68.8 Tm 9.6 TL /F3 8 Tf 0 0 0 rg (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,) Tj (<) Tj (reg_opcode) Tj (>) Tj (,) Tj (<) Tj (address) Tj (>) Tj (,) Tj (<) Tj (value) Tj (>) Tj T* ( ) Tj (<) Tj (reg_opcode) Tj (>) Tj ( = pci_wr|mmio_wr|io_wr|pci_rw|mmio_rw|io_rw) Tj T* T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,mem[,) Tj (<) Tj (address) Tj (>) Tj (,) Tj (<) Tj (value) Tj (>) Tj (]) Tj T* T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch``) Tj T* T* (chipsec_main.py -m tools.uefi.s3script_modify -a replace_op,dispatch_ep``) Tj T* ET Q Q Q @@ -48702,14 +48632,14 @@ Q Q Q q -1 0 0 1 40.01575 657.5008 cm +1 0 0 1 40.01575 480.3008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 631.5008 cm +1 0 0 1 40.01575 454.3008 cm q q 1 0 0 1 0 0 cm @@ -48729,20 +48659,20 @@ Q Q Q q -1 0 0 1 40.01575 599.5008 cm +1 0 0 1 40.01575 422.3008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will look for a script opcode that writes to PCI config, MMIO or I/O registers and modify the opcode to) Tj T* (write the given value to the register with the given address.) Tj T* ET Q Q q -1 0 0 1 40.01575 569.5008 cm +1 0 0 1 40.01575 392.3008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (After executing this, if the system is vulnerable to boot script modification, the hardware configuration will have) Tj T* (changed according to given <) Tj (reg_opcode) Tj (>) Tj (.) Tj T* ET Q Q q -1 0 0 1 40.01575 553.1008 cm +1 0 0 1 40.01575 375.9008 cm q q 1 0 0 1 0 0 cm @@ -48762,27 +48692,27 @@ Q Q Q q -1 0 0 1 40.01575 521.1008 cm +1 0 0 1 40.01575 343.9008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will look for a script opcode that writes to memory and modify the opcode to write the given value to the) Tj T* (given address.) Tj T* ET Q Q q -1 0 0 1 40.01575 503.1008 cm +1 0 0 1 40.01575 325.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (By default this test will allocate memory and write write ) Tj /F3 10 Tf (0xB007B007) Tj /F1 10 Tf ( that location.) Tj T* ET Q Q q -1 0 0 1 40.01575 473.1008 cm +1 0 0 1 40.01575 295.9008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (After executing this, if the system is vulnerable to boot script modification, you should find the given value in the) Tj T* (allocated memory location.) Tj T* ET Q Q q -1 0 0 1 40.01575 456.7008 cm +1 0 0 1 40.01575 279.5008 cm q q 1 0 0 1 0 0 cm @@ -48802,21 +48732,21 @@ Q Q Q q -1 0 0 1 40.01575 424.7008 cm +1 0 0 1 40.01575 247.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will look for a dispatch opcode in the script and modify the opcode to point to a different entry point. The) Tj T* (new entry point will contain a HLT instruction.) Tj T* ET Q Q q -1 0 0 1 40.01575 394.7008 cm +1 0 0 1 40.01575 217.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (After executing this, if the system is vulnerable to boot script modification, the system should hang on resume from) Tj T* (S3.) Tj T* ET Q Q q -1 0 0 1 40.01575 378.3008 cm +1 0 0 1 40.01575 201.1008 cm q q 1 0 0 1 0 0 cm @@ -48836,21 +48766,21 @@ Q Q Q q -1 0 0 1 40.01575 346.3008 cm +1 0 0 1 40.01575 169.1008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will look for a dispatch opcode in the script and will modify memory at the entry point for that opcode. The) Tj T* (modified instructions will contain a HLT instruction.) Tj T* ET Q Q q -1 0 0 1 40.01575 316.3008 cm +1 0 0 1 40.01575 139.1008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (After executing this, if the system is vulnerable to dispatch opcode entry point modification, the system should hang) Tj T* (on resume from S3.) Tj T* ET Q Q q -1 0 0 1 40.01575 290.3008 cm +1 0 0 1 40.01575 113.1008 cm q q 1 0 0 1 0 0 cm @@ -48870,14 +48800,14 @@ Q Q Q q -1 0 0 1 40.01575 270.3008 cm +1 0 0 1 40.01575 93.10079 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (The option will add a new opcode which writes to PCI config, MMIO or I/O registers with specified values.) Tj T* ET Q Q q -1 0 0 1 40.01575 253.9008 cm +1 0 0 1 40.01575 76.70079 cm q q 1 0 0 1 0 0 cm @@ -48897,66 +48827,6 @@ Q Q Q q -1 0 0 1 40.01575 221.9008 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will add a new DISPATCH opcode to the script with entry point to either existing or newly allocated) Tj T* (memory.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 215.9008 cm -Q -q -1 0 0 1 40.01575 197.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (s3script_modify) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 185.9008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 179.9008 cm -Q -q -1 0 0 1 50.01575 161.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DISPATCH_ENTRYPOINT_INSTR) Tj /F4 10 Tf ( = '\\x90\\x90\364\364') Tj T* ET -Q -Q -q -1 0 0 1 50.01575 155.9008 cm -Q -q -1 0 0 1 50.01575 137.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_bootscript) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 131.9008 cm -Q -q -1 0 0 1 50.01575 113.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 89.90079 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 83.90079 cm -Q -q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -48966,40 +48836,40 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (122) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (121) Tj T* ET Q Q endstream endobj -1327 0 obj +1323 0 obj << -/Length 7312 +/Length 7508 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 40.01575 751.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_add) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (new_opcode) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The option will add a new DISPATCH opcode to the script with entry point to either existing or newly allocated) Tj T* (memory.) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 40.01575 745.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 40.01575 727.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_dispatch) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (s3script_modify) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm -Q -q 1 0 0 1 50.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_dispatch_ep) Tj /F2 10 Tf ( \(\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET Q Q q @@ -49008,7 +48878,7 @@ Q q 1 0 0 1 50.01575 691.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (DISPATCH_ENTRYPOINT_INSTR) Tj /F4 10 Tf ( = '\\x90\\x90\364\364') Tj T* ET Q Q q @@ -49017,7 +48887,7 @@ Q q 1 0 0 1 50.01575 667.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (opcode) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_bootscript) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -49026,11 +48896,71 @@ Q q 1 0 0 1 50.01575 643.7008 cm q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 619.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 613.7008 cm +Q +q +1 0 0 1 50.01575 595.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_add) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (new_opcode) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 589.7008 cm +Q +q +1 0 0 1 50.01575 571.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_dispatch) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 565.7008 cm +Q +q +1 0 0 1 50.01575 547.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_dispatch_ep) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 541.7008 cm +Q +q +1 0 0 1 50.01575 523.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 517.7008 cm +Q +q +1 0 0 1 50.01575 499.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (modify_s3_reg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (opcode) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (address) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (new_value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 493.7008 cm +Q +q +1 0 0 1 50.01575 475.7008 cm +q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 594.1008 cm +1 0 0 1 40.01575 426.1008 cm q 1 1 1 RG .3 w @@ -49042,27 +48972,27 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (scan_blocked module) Tj T* ET Q Q q -1 0 0 1 40.01575 540.1008 cm +1 0 0 1 40.01575 372.1008 cm q BT 1 0 0 1 0 38 Tm 12 TL /F1 10 Tf 0 0 0 rg (This module checks current contents of UEFI firmware ROM or specified firmware image for blocked EFI binaries) Tj T* (which can be EFI firmware volumes, EFI executable binaries \(PEI modules, DXE drivers..\) or EFI sections. The) Tj T* (module can find EFI binaries by their UI names, EFI GUIDs, MD5/SHA-1/SHA-256 hashes or contents matching) Tj T* (specified regular expressions.) Tj T* ET Q Q q -1 0 0 1 40.01575 510.1008 cm +1 0 0 1 40.01575 342.1008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Important! This module can only detect what it knows about from its config file. If a bad or vulnerable binary is not) Tj T* (detected then its \221signature\222 needs to be added to the config.) Tj T* ET Q Q q -1 0 0 1 40.01575 494.1008 cm +1 0 0 1 40.01575 326.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 416.1008 cm +1 0 0 1 40.01575 248.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -49144,14 +49074,14 @@ Q Q Q q -1 0 0 1 40.01575 398.1008 cm +1 0 0 1 40.01575 230.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 381.7008 cm +1 0 0 1 40.01575 213.7008 cm q q 1 0 0 1 0 0 cm @@ -49171,13 +49101,13 @@ Q Q Q q -1 0 0 1 40.01575 349.7008 cm +1 0 0 1 40.01575 181.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Dumps UEFI firmware image from flash memory device, decodes it and checks for blocked EFI modules defined in) Tj T* (the default config ) Tj /F3 10 Tf (blockedlist.json) Tj T* ET Q Q q -1 0 0 1 40.01575 333.3008 cm +1 0 0 1 40.01575 165.3008 cm q q 1 0 0 1 0 0 cm @@ -49197,28 +49127,28 @@ Q Q Q q -1 0 0 1 40.01575 301.3008 cm +1 0 0 1 40.01575 133.3008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Decodes ) Tj /F3 10 Tf (uefi.rom) Tj /F1 10 Tf ( binary with UEFI firmware image and checks for blocked EFI modules defined in) Tj T* /F3 10 Tf (blockedlist.json) Tj /F1 10 Tf ( config) Tj T* ET Q Q q -1 0 0 1 40.01575 271.3008 cm +1 0 0 1 40.01575 103.3008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: ) Tj /F3 10 Tf (-i) Tj /F1 10 Tf ( and ) Tj /F3 10 Tf (--no_driver) Tj /F1 10 Tf ( arguments can be used in this case because the test does not depend on the platform) Tj T* (and no kernel driver is required when firmware image is specified) Tj T* ET Q Q q -1 0 0 1 40.01575 265.3008 cm +1 0 0 1 40.01575 97.30079 cm Q q -1 0 0 1 40.01575 247.3008 cm +1 0 0 1 40.01575 79.30079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (scan_blocked) Tj T* ET Q Q q -1 0 0 1 50.01575 235.3008 cm +1 0 0 1 50.01575 67.30079 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -49226,55 +49156,7 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 229.3008 cm -Q -q -1 0 0 1 50.01575 211.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (blockedlist_callback) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_module) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 205.3008 cm -Q -q -1 0 0 1 50.01575 187.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_blockedlist) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 181.3008 cm -Q -q -1 0 0 1 50.01575 163.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 60.01575 139.3008 cm -q -BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 133.3008 cm -Q -q -1 0 0 1 50.01575 115.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 109.3008 cm -Q -q -1 0 0 1 50.01575 91.30079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q +1 0 0 1 50.01575 66.18898 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -49286,20 +49168,68 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (123) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (122) Tj T* ET Q Q endstream endobj -1328 0 obj +1324 0 obj << -/Length 8319 +/Length 8318 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 766.1008 cm +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (blockedlist_callback) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_module) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_blockedlist) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 733.7008 cm +Q +q +1 0 0 1 50.01575 715.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 60.01575 691.7008 cm +q +BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 685.7008 cm +Q +q +1 0 0 1 50.01575 667.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 661.7008 cm +Q +q +1 0 0 1 50.01575 643.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 594.1008 cm q 1 1 1 RG .3 w @@ -49311,20 +49241,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (scan_image module) Tj T* ET Q Q q -1 0 0 1 40.01575 736.1008 cm +1 0 0 1 40.01575 564.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module can generate a list of EFI executables from \(U\)EFI firmware file or extracted from flash ROM, and then) Tj T* (later check firmware image in flash ROM or file against this list of expected executables) Tj T* ET Q Q q -1 0 0 1 40.01575 720.1008 cm +1 0 0 1 40.01575 548.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 570.1008 cm +1 0 0 1 40.01575 398.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -49523,14 +49453,14 @@ Q Q Q q -1 0 0 1 40.01575 552.1008 cm +1 0 0 1 40.01575 380.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 535.7008 cm +1 0 0 1 40.01575 363.7008 cm q q 1 0 0 1 0 0 cm @@ -49550,13 +49480,13 @@ Q Q Q q -1 0 0 1 40.01575 515.7008 cm +1 0 0 1 40.01575 343.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Creates a list of EFI executable binaries in ) Tj /F3 10 Tf (efilist.json) Tj /F1 10 Tf ( from the firmware image extracted from ROM) Tj T* ET Q Q q -1 0 0 1 40.01575 499.3008 cm +1 0 0 1 40.01575 327.3008 cm q q 1 0 0 1 0 0 cm @@ -49576,13 +49506,13 @@ Q Q Q q -1 0 0 1 40.01575 479.3008 cm +1 0 0 1 40.01575 307.3008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Creates a list of EFI executable binaries in ) Tj /F3 10 Tf (efilist.json) Tj /F1 10 Tf ( from ) Tj /F3 10 Tf (uefi.rom) Tj /F1 10 Tf ( firmware binary) Tj T* ET Q Q q -1 0 0 1 40.01575 462.9008 cm +1 0 0 1 40.01575 290.9008 cm q q 1 0 0 1 0 0 cm @@ -49602,28 +49532,28 @@ Q Q Q q -1 0 0 1 40.01575 430.9008 cm +1 0 0 1 40.01575 258.9008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Decodes ) Tj /F3 10 Tf (uefi.rom) Tj /F1 10 Tf ( UEFI firmware image binary and checks all EFI executables in it against a list defined in) Tj T* /F3 10 Tf (efilist.json) Tj T* ET Q Q q -1 0 0 1 40.01575 400.9008 cm +1 0 0 1 40.01575 228.9008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: ) Tj /F3 10 Tf (-i) Tj /F1 10 Tf ( and ) Tj /F3 10 Tf (-n) Tj /F1 10 Tf ( arguments can be used when specifying firmware file because the module doesn\222t depend on the) Tj T* (platform and doesn\222t need kernel driver) Tj T* ET Q Q q -1 0 0 1 40.01575 394.9008 cm +1 0 0 1 40.01575 222.9008 cm Q q -1 0 0 1 40.01575 376.9008 cm +1 0 0 1 40.01575 204.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (scan_image) Tj T* ET Q Q q -1 0 0 1 50.01575 364.9008 cm +1 0 0 1 50.01575 192.9008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -49631,96 +49561,49 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 358.9008 cm +1 0 0 1 50.01575 186.9008 cm Q q -1 0 0 1 50.01575 340.9008 cm +1 0 0 1 50.01575 168.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (check_list) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (json_pth) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 334.9008 cm +1 0 0 1 50.01575 162.9008 cm Q q -1 0 0 1 50.01575 316.9008 cm +1 0 0 1 50.01575 144.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (generate_efilist) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (json_pth) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 310.9008 cm +1 0 0 1 50.01575 138.9008 cm Q q -1 0 0 1 50.01575 292.9008 cm +1 0 0 1 50.01575 120.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (genlist_callback) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (efi_module) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 286.9008 cm +1 0 0 1 50.01575 114.9008 cm Q q -1 0 0 1 50.01575 268.9008 cm +1 0 0 1 50.01575 96.90079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 244.9008 cm +1 0 0 1 60.01575 72.90079 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 238.9008 cm -Q -q -1 0 0 1 50.01575 220.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 214.9008 cm -Q -q -1 0 0 1 50.01575 196.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 147.3008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefivar_fuzz module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 129.3008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module is fuzzing UEFI Variable interface.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 99.30079 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module is using UEFI SetVariable interface to write new UEFI variables to SPI flash NVRAM with randomized) Tj T* (name/attributes/GUID/data/size.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 69.30079 cm -q -0 0 0 rg -BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Note: this module modifies contents of non-volatile SPI flash memory \(UEFI Variable NVRAM\). This may render) Tj T* (system unbootable if firmware doesn\222t properly handle variable update/delete operations.) Tj T* ET -Q +1 0 0 1 50.01575 66.90079 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -49732,30 +49615,77 @@ q 1 0 0 1 34.01575 34.01575 cm q 0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (124) Tj T* ET +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (123) Tj T* ET Q Q endstream endobj -1329 0 obj +1325 0 obj << -/Length 6960 +/Length 6134 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 763.7008 cm +1 0 0 1 50.01575 763.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 757.7008 cm +Q +q +1 0 0 1 50.01575 739.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 690.1008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (uefivar_fuzz module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 672.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (The module is fuzzing UEFI Variable interface.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 642.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The module is using UEFI SetVariable interface to write new UEFI variables to SPI flash NVRAM with randomized) Tj T* (name/attributes/GUID/data/size.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 612.1008 cm +q +0 0 0 rg +BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (Note: this module modifies contents of non-volatile SPI flash memory \(UEFI Variable NVRAM\). This may render) Tj T* (system unbootable if firmware doesn\222t properly handle variable update/delete operations.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 594.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 757.7008 cm +1 0 0 1 40.01575 588.1008 cm Q q -1 0 0 1 40.01575 745.7008 cm +1 0 0 1 40.01575 576.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -49771,20 +49701,20 @@ Q Q Q q -1 0 0 1 40.01575 745.7008 cm +1 0 0 1 40.01575 576.1008 cm Q q -1 0 0 1 40.01575 727.7008 cm +1 0 0 1 40.01575 558.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Options:) Tj T* ET Q Q q -1 0 0 1 40.01575 721.7008 cm +1 0 0 1 40.01575 552.1008 cm Q q -1 0 0 1 40.01575 613.7008 cm +1 0 0 1 40.01575 444.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -49929,17 +49859,17 @@ Q Q Q q -1 0 0 1 40.01575 613.7008 cm +1 0 0 1 40.01575 444.1008 cm Q q -1 0 0 1 40.01575 595.7008 cm +1 0 0 1 40.01575 426.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 550.5008 cm +1 0 0 1 40.01575 380.9008 cm q q 1 0 0 1 0 0 cm @@ -49959,16 +49889,16 @@ Q Q Q q -1 0 0 1 40.01575 536.5008 cm +1 0 0 1 40.01575 366.9008 cm Q q -1 0 0 1 40.01575 518.5008 cm +1 0 0 1 40.01575 348.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (uefivar_fuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 506.5008 cm +1 0 0 1 50.01575 336.9008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -49976,49 +49906,71 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 500.5008 cm +1 0 0 1 50.01575 330.9008 cm Q q -1 0 0 1 50.01575 482.5008 cm +1 0 0 1 50.01575 312.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 458.5008 cm +1 0 0 1 60.01575 288.9008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 452.5008 cm +1 0 0 1 50.01575 282.9008 cm Q q -1 0 0 1 50.01575 434.5008 cm +1 0 0 1 50.01575 264.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rnd) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (n) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 428.5008 cm +1 0 0 1 50.01575 258.9008 cm Q q -1 0 0 1 50.01575 410.5008 cm +1 0 0 1 50.01575 240.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 404.5008 cm +1 0 0 1 50.01575 234.9008 cm Q q -1 0 0 1 50.01575 386.5008 cm +1 0 0 1 50.01575 216.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 336.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (124) Tj T* ET +Q +Q + +endstream +endobj +1326 0 obj +<< +/Length 7009 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -50030,7 +49982,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmm package) Tj T* ET Q Q q -1 0 0 1 40.01575 287.3008 cm +1 0 0 1 40.01575 716.5008 cm q 1 1 1 RG .3 w @@ -50042,7 +49994,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hv package) Tj T* ET Q Q q -1 0 0 1 40.01575 237.7008 cm +1 0 0 1 40.01575 666.9008 cm q 1 1 1 RG .3 w @@ -50054,48 +50006,221 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (define module) Tj T* ET Q Q q -1 0 0 1 40.01575 219.7008 cm +1 0 0 1 40.01575 648.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V specific defines) Tj T* ET Q Q q -1 0 0 1 40.01575 213.7008 cm +1 0 0 1 40.01575 642.9008 cm Q q -1 0 0 1 40.01575 195.7008 cm +1 0 0 1 40.01575 624.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 189.7008 cm +1 0 0 1 40.01575 618.9008 cm Q q -1 0 0 1 40.01575 171.7008 cm +1 0 0 1 40.01575 600.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_status) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 165.7008 cm +1 0 0 1 40.01575 594.9008 cm Q q -1 0 0 1 40.01575 147.7008 cm +1 0 0 1 40.01575 576.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_msr_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 141.7008 cm +1 0 0 1 40.01575 570.9008 cm Q q -1 0 0 1 40.01575 123.7008 cm +1 0 0 1 40.01575 552.9008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (varlist) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 40.01575 503.3008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercall module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 485.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V specific hypercall functionality) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 479.3008 cm +Q +q +1 0 0 1 40.01575 461.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HyperVHypercall) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 449.3008 cm +q +.933333 1 .8 rg +n 33.35 0 306 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleHwAccess) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 443.3008 cm +Q +q +1 0 0 1 50.01575 425.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (custom_fuzzing) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (call_code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 419.3008 cm +Q +q +1 0 0 1 50.01575 401.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (input_parameters_fuzzing) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 395.3008 cm +Q +q +1 0 0 1 50.01575 377.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_connectionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 371.3008 cm +Q +q +1 0 0 1 50.01575 353.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypercall_status) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 347.3008 cm +Q +q +1 0 0 1 50.01575 329.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypervisor_cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpuid_eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cpuid_ecx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 323.3008 cm +Q +q +1 0 0 1 50.01575 305.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypervisor_info) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 299.3008 cm +Q +q +1 0 0 1 50.01575 281.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_input_parameters) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 275.3008 cm +Q +q +1 0 0 1 50.01575 257.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_partition_properties) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 251.3008 cm +Q +q +1 0 0 1 50.01575 233.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_partitionid) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 227.3008 cm +Q +q +1 0 0 1 50.01575 209.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_synthetic_msrs) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 203.3008 cm +Q +q +1 0 0 1 50.01575 185.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_connectionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (id_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 179.3008 cm +Q +q +1 0 0 1 50.01575 161.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_for_success_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 155.3008 cm +Q +q +1 0 0 1 50.01575 137.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_hypercalls) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (code_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 131.3008 cm +Q +q +1 0 0 1 50.01575 113.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_input_parameters) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 107.3008 cm +Q +q +1 0 0 1 50.01575 89.30079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_partitionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (id_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 83.30079 cm +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -50111,202 +50236,29 @@ Q endstream endobj -1330 0 obj +1327 0 obj << -/Length 9139 +/Length 8826 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 766.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercall module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 748.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V specific hypercall functionality) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 742.1008 cm -Q -q -1 0 0 1 40.01575 724.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HyperVHypercall) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 712.1008 cm -q -.933333 1 .8 rg -n 33.35 0 306 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleHwAccess) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 706.1008 cm -Q -q -1 0 0 1 50.01575 688.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (custom_fuzzing) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (call_code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 682.1008 cm -Q -q -1 0 0 1 50.01575 664.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (input_parameters_fuzzing) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 658.1008 cm -Q -q -1 0 0 1 50.01575 640.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_connectionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 634.1008 cm -Q -q -1 0 0 1 50.01575 616.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypercall_status) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 610.1008 cm -Q -q -1 0 0 1 50.01575 592.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypervisor_cpuid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cpuid_eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (cpuid_ecx) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 586.1008 cm -Q -q -1 0 0 1 50.01575 568.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypervisor_info) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 562.1008 cm -Q -q -1 0 0 1 50.01575 544.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_input_parameters) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 538.1008 cm -Q -q -1 0 0 1 50.01575 520.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_partition_properties) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 514.1008 cm -Q -q -1 0 0 1 50.01575 496.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_partitionid) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 490.1008 cm -Q -q -1 0 0 1 50.01575 472.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_synthetic_msrs) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 466.1008 cm -Q -q -1 0 0 1 50.01575 448.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_connectionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (id_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 442.1008 cm -Q -q -1 0 0 1 50.01575 424.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_for_success_status) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total_tests) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 418.1008 cm -Q -q -1 0 0 1 50.01575 400.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_hypercalls) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (code_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 394.1008 cm -Q -q -1 0 0 1 50.01575 376.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_input_parameters) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (i) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (maxlen) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 370.1008 cm -Q -q -1 0 0 1 50.01575 352.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_partitionid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (id_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 346.1008 cm -Q -q -1 0 0 1 50.01575 328.1008 cm +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_partition_property) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (part) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (prop) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 322.1008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 40.01575 304.1008 cm +1 0 0 1 40.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 254.5008 cm +1 0 0 1 40.01575 690.1008 cm q 1 1 1 RG .3 w @@ -50318,20 +50270,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercallfuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 236.5008 cm +1 0 0 1 40.01575 672.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V hypercall fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 220.5008 cm +1 0 0 1 40.01575 656.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 20.6378 67.50079 cm +1 0 0 1 20.6378 503.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -50566,44 +50518,22 @@ Q Q Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (126) Tj T* ET -Q -Q - -endstream -endobj -1331 0 obj -<< -/Length 7119 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 763.7008 cm +1 0 0 1 40.01575 485.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: the fuzzer is incompatible with native VMBus driver \() Tj /F3 10 Tf (vmbus.sys) Tj /F1 10 Tf (\). To use it, remove ) Tj /F3 10 Tf (vmbus.sys) Tj T* ET Q Q q -1 0 0 1 40.01575 757.7008 cm +1 0 0 1 40.01575 479.1008 cm Q q -1 0 0 1 40.01575 739.7008 cm +1 0 0 1 40.01575 461.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HypercallFuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 727.7008 cm +1 0 0 1 50.01575 449.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -50611,34 +50541,34 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 721.7008 cm +1 0 0 1 50.01575 443.1008 cm Q q -1 0 0 1 50.01575 703.7008 cm +1 0 0 1 50.01575 425.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 697.7008 cm +1 0 0 1 50.01575 419.1008 cm Q q -1 0 0 1 50.01575 679.7008 cm +1 0 0 1 50.01575 401.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 673.7008 cm +1 0 0 1 40.01575 395.1008 cm Q q -1 0 0 1 40.01575 655.7008 cm +1 0 0 1 40.01575 377.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 606.1008 cm +1 0 0 1 40.01575 327.5008 cm q 1 1 1 RG .3 w @@ -50650,23 +50580,23 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (synth_dev module) Tj T* ET Q Q q -1 0 0 1 40.01575 588.1008 cm +1 0 0 1 40.01575 309.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V VMBus synthetic device generic fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 570.1008 cm +1 0 0 1 40.01575 291.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 564.1008 cm +1 0 0 1 40.01575 285.5008 cm Q q -1 0 0 1 40.01575 498.1008 cm +1 0 0 1 40.01575 219.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -50702,25 +50632,25 @@ Q Q Q q -1 0 0 1 40.01575 498.1008 cm +1 0 0 1 40.01575 219.5008 cm Q q -1 0 0 1 40.01575 480.1008 cm +1 0 0 1 40.01575 201.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: the fuzzer is incompatible with native VMBus driver \() Tj /F3 10 Tf (vmbus.sys) Tj /F1 10 Tf (\). To use it, remove ) Tj /F3 10 Tf (vmbus.sys) Tj T* ET Q Q q -1 0 0 1 40.01575 474.1008 cm +1 0 0 1 40.01575 195.5008 cm Q q -1 0 0 1 40.01575 456.1008 cm +1 0 0 1 40.01575 177.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMBusDeviceFuzzer) Tj T* ET Q Q q -1 0 0 1 50.01575 444.1008 cm +1 0 0 1 50.01575 165.5008 cm q .933333 1 .8 rg n 33.35 0 294 12 re f* @@ -50728,61 +50658,83 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 438.1008 cm +1 0 0 1 50.01575 159.5008 cm Q q -1 0 0 1 50.01575 420.1008 cm +1 0 0 1 50.01575 141.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (device_fuzzing) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 414.1008 cm +1 0 0 1 50.01575 135.5008 cm Q q -1 0 0 1 50.01575 396.1008 cm +1 0 0 1 50.01575 117.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_1) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (info) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (indent) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 390.1008 cm +1 0 0 1 50.01575 111.5008 cm Q q -1 0 0 1 50.01575 372.1008 cm +1 0 0 1 50.01575 93.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_statistics) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 366.1008 cm +1 0 0 1 50.01575 87.50079 cm Q q -1 0 0 1 50.01575 348.1008 cm +1 0 0 1 50.01575 69.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (send_1) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (messages) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (info) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (order) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 342.1008 cm +1 0 0 1 40.01575 66.18898 cm Q q -1 0 0 1 40.01575 324.1008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (126) Tj T* ET +Q +Q + +endstream +endobj +1328 0 obj +<< +/Length 6735 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 318.1008 cm +1 0 0 1 40.01575 757.7008 cm Q q -1 0 0 1 40.01575 300.1008 cm +1 0 0 1 40.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (synth_dev) Tj T* ET Q Q q -1 0 0 1 50.01575 288.1008 cm +1 0 0 1 50.01575 727.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -50790,25 +50742,25 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 282.1008 cm +1 0 0 1 50.01575 721.7008 cm Q q -1 0 0 1 50.01575 264.1008 cm +1 0 0 1 50.01575 703.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 258.1008 cm +1 0 0 1 50.01575 697.7008 cm Q q -1 0 0 1 50.01575 240.1008 cm +1 0 0 1 50.01575 679.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 190.5008 cm +1 0 0 1 40.01575 630.1008 cm q 1 1 1 RG .3 w @@ -50820,20 +50772,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (synth_kbd module) Tj T* ET Q Q q -1 0 0 1 40.01575 172.5008 cm +1 0 0 1 40.01575 612.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V VMBus synthetic keyboard fuzzer. Fuzzes inbound ring buffer in VMBus virtual keyboard device.) Tj T* ET Q Q q -1 0 0 1 40.01575 156.5008 cm +1 0 0 1 40.01575 596.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 141.5008 cm +1 0 0 1 40.01575 581.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -50849,22 +50801,22 @@ Q Q Q q -1 0 0 1 40.01575 123.5008 cm +1 0 0 1 40.01575 563.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: the fuzzer is incompatible with native VMBus driver \() Tj /F3 10 Tf (vmbus.sys) Tj /F1 10 Tf (\). To use it, remove ) Tj /F3 10 Tf (vmbus.sys) Tj T* ET Q Q q -1 0 0 1 40.01575 117.5008 cm +1 0 0 1 40.01575 557.1008 cm Q q -1 0 0 1 40.01575 99.50079 cm +1 0 0 1 40.01575 539.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RingBufferFuzzer) Tj T* ET Q Q q -1 0 0 1 50.01575 87.50079 cm +1 0 0 1 50.01575 527.1008 cm q .933333 1 .8 rg n 33.35 0 270 12 re f* @@ -50872,6 +50824,174 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q +1 0 0 1 50.01575 521.1008 cm +Q +q +1 0 0 1 50.01575 503.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_read) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 497.1008 cm +Q +q +1 0 0 1 40.01575 479.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 473.1008 cm +Q +q +1 0 0 1 40.01575 455.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (synth_kbd) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 443.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 437.1008 cm +Q +q +1 0 0 1 50.01575 419.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 413.1008 cm +Q +q +1 0 0 1 50.01575 395.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 345.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmbus module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 327.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V VMBus functionality) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 321.5008 cm +Q +q +1 0 0 1 40.01575 303.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HyperV) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 291.5008 cm +q +.933333 1 .8 rg +n 33.35 0 288 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 285.5008 cm +Q +q +1 0 0 1 50.01575 267.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_init) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 261.5008 cm +Q +q +1 0 0 1 50.01575 243.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_post_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 237.5008 cm +Q +q +1 0 0 1 50.01575 219.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_recv_events) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sint) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 213.5008 cm +Q +q +1 0 0 1 50.01575 195.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_recv_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sint) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 189.5008 cm +Q +q +1 0 0 1 50.01575 171.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_signal_event) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (connection_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (flag_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 165.5008 cm +Q +q +1 0 0 1 40.01575 147.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RingBuffer) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 135.5008 cm +q +.933333 1 .8 rg +n 33.35 0 288 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 129.5008 cm +Q +q +1 0 0 1 50.01575 111.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_alloc) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pages) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 105.5008 cm +Q +q +1 0 0 1 50.01575 87.50079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_copyfrom) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 81.50079 cm Q q @@ -50890,242 +51010,74 @@ Q endstream endobj -1332 0 obj +1329 0 obj << -/Length 7190 +/Length 8011 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_read) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 757.7008 cm -Q -q -1 0 0 1 40.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 733.7008 cm -Q -q -1 0 0 1 40.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (synth_kbd) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 697.7008 cm -Q -q -1 0 0 1 50.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 673.7008 cm -Q -q -1 0 0 1 50.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 606.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmbus module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 588.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V VMBus functionality) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 582.1008 cm -Q -q -1 0 0 1 40.01575 564.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HyperV) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 552.1008 cm -q -.933333 1 .8 rg -n 33.35 0 288 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 546.1008 cm -Q -q -1 0 0 1 50.01575 528.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_init) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 522.1008 cm -Q -q -1 0 0 1 50.01575 504.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_post_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 498.1008 cm -Q -q -1 0 0 1 50.01575 480.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_recv_events) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sint) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 474.1008 cm -Q -q -1 0 0 1 50.01575 456.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_recv_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (sint) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 450.1008 cm -Q -q -1 0 0 1 50.01575 432.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_signal_event) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (connection_id) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (flag_number) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 426.1008 cm -Q -q -1 0 0 1 40.01575 408.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (RingBuffer) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 396.1008 cm -q -.933333 1 .8 rg -n 33.35 0 288 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 390.1008 cm -Q -q -1 0 0 1 50.01575 372.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_alloc) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pages) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 366.1008 cm -Q -q -1 0 0 1 50.01575 348.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_copyfrom) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (total) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 342.1008 cm -Q -q -1 0 0 1 50.01575 324.1008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_copyto) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (index) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 318.1008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 300.1008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_init) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 294.1008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 276.1008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_read) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 270.1008 cm +1 0 0 1 50.01575 709.7008 cm Q q -1 0 0 1 50.01575 252.1008 cm +1 0 0 1 50.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_read_with_timeout) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (timeout) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 246.1008 cm +1 0 0 1 50.01575 685.7008 cm Q q -1 0 0 1 50.01575 228.1008 cm +1 0 0 1 50.01575 667.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 222.1008 cm +1 0 0 1 50.01575 661.7008 cm Q q -1 0 0 1 50.01575 204.1008 cm +1 0 0 1 50.01575 643.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (ringbuffer_write_with_timeout) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (timeout) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 198.1008 cm +1 0 0 1 40.01575 637.7008 cm Q q -1 0 0 1 40.01575 180.1008 cm +1 0 0 1 40.01575 619.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMBus) Tj T* ET Q Q q -1 0 0 1 50.01575 168.1008 cm +1 0 0 1 50.01575 607.7008 cm q .933333 1 .8 rg n 33.35 0 246 12 re f* @@ -51133,42 +51085,186 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 162.1008 cm +1 0 0 1 50.01575 601.7008 cm Q q -1 0 0 1 50.01575 144.1008 cm +1 0 0 1 50.01575 583.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_clear) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 138.1008 cm +1 0 0 1 50.01575 577.7008 cm Q q -1 0 0 1 50.01575 120.1008 cm +1 0 0 1 50.01575 559.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_close) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 114.1008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 50.01575 96.10079 cm +1 0 0 1 50.01575 535.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_connect) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vmbus_version) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (131076) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (target_vcpu) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 90.10079 cm +1 0 0 1 50.01575 529.7008 cm Q q -1 0 0 1 50.01575 72.10079 cm +1 0 0 1 50.01575 511.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_disconnect) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q +1 0 0 1 50.01575 505.7008 cm +Q +q +1 0 0 1 50.01575 487.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_establish_gpadl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pfn) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 481.7008 cm +Q +q +1 0 0 1 50.01575 463.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_get_next_gpadl) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 457.7008 cm +Q +q +1 0 0 1 50.01575 439.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_get_next_version) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (current_version) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 433.7008 cm +Q +q +1 0 0 1 50.01575 415.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_init) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 409.7008 cm +Q +q +1 0 0 1 50.01575 391.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_onmessage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 385.7008 cm +Q +q +1 0 0 1 50.01575 307.7008 cm +q +BT 1 0 0 1 0 62 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_open) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pageoffset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (userdata) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00) Tj .396078 .588235 .639216 rg T* .419608 .623529 1 rg (\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0) Tj T* (0\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x) Tj T* (00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00) Tj T* (\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0) Tj T* (0') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 301.7008 cm +Q +q +1 0 0 1 50.01575 283.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_post_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 277.7008 cm +Q +q +1 0 0 1 50.01575 259.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_process_rescind_offer) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 253.7008 cm +Q +q +1 0 0 1 50.01575 235.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recv_events) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 229.7008 cm +Q +q +1 0 0 1 50.01575 211.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recv_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (timeout) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 205.7008 cm +Q +q +1 0 0 1 50.01575 187.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recvpacket) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 181.7008 cm +Q +q +1 0 0 1 50.01575 163.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recvpacket_raw) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 157.7008 cm +Q +q +1 0 0 1 50.01575 139.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_request_offers) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 133.7008 cm +Q +q +1 0 0 1 50.01575 115.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (requestid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (packet_type) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (flags) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 109.7008 cm +Q +q +1 0 0 1 50.01575 91.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket_multipagebuffer) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 85.70079 cm +Q +q +1 0 0 1 50.01575 67.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket_pagebuffer) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 66.18898 cm Q q @@ -51187,16 +51283,16 @@ Q endstream endobj -1333 0 obj +1330 0 obj << -/Length 7618 +/Length 7182 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_establish_gpadl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pfn) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_setevent) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -51205,43 +51301,69 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_get_next_gpadl) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_teardown_gpadl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 40.01575 733.7008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_get_next_version) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (current_version) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMBusDiscovery) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm -Q +1 0 0 1 50.01575 703.7008 cm q -1 0 0 1 50.01575 691.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_init) Tj /F2 10 Tf ( \(\)) Tj T* ET +.933333 1 .8 rg +n 33.35 0 240 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.hv.vmbus.VMBus) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 697.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 679.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_onmessage) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_relid_by_guid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 50.01575 673.7008 cm +Q +q +1 0 0 1 50.01575 655.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_created_gpadl) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 649.7008 cm +Q +q +1 0 0 1 50.01575 631.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_events) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 625.7008 cm +Q +q +1 0 0 1 50.01575 607.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_offer_channels) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 601.7008 cm Q q 1 0 0 1 50.01575 583.7008 cm q -BT 1 0 0 1 0 62 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_open) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pageoffset) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (userdata) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00) Tj .396078 .588235 .639216 rg T* .419608 .623529 1 rg (\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0) Tj T* (0\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x) Tj T* (00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00) Tj T* (\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x00\\x0) Tj T* (0') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_open_channels) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -51250,7 +51372,7 @@ Q q 1 0 0 1 50.01575 559.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_post_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_supported_versions) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -51259,7 +51381,7 @@ Q q 1 0 0 1 50.01575 535.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_process_rescind_offer) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_physical_addresses) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (version) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -51268,7 +51390,7 @@ Q q 1 0 0 1 50.01575 511.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recv_events) Tj /F2 10 Tf ( \(\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_supported_versions) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mask) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (983055) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -51277,212 +51399,20 @@ Q q 1 0 0 1 50.01575 487.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recv_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (timeout) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 481.7008 cm -Q -q -1 0 0 1 50.01575 463.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recvpacket) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 457.7008 cm -Q -q -1 0 0 1 50.01575 439.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_recvpacket_raw) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 433.7008 cm -Q -q -1 0 0 1 50.01575 415.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_request_offers) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 409.7008 cm -Q -q -1 0 0 1 50.01575 391.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (requestid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (packet_type) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (flags) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 385.7008 cm -Q -q -1 0 0 1 50.01575 367.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket_multipagebuffer) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 361.7008 cm -Q -q -1 0 0 1 50.01575 343.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_sendpacket_pagebuffer) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 337.7008 cm -Q -q -1 0 0 1 50.01575 319.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_setevent) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 313.7008 cm -Q -q -1 0 0 1 50.01575 295.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_teardown_gpadl) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (child_relid) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (gpadl) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 289.7008 cm -Q -q -1 0 0 1 40.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMBusDiscovery) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 259.7008 cm -q -.933333 1 .8 rg -n 33.35 0 240 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.hv.vmbus.VMBus) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 253.7008 cm -Q -q -1 0 0 1 50.01575 235.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_relid_by_guid) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (guid) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 229.7008 cm -Q -q -1 0 0 1 50.01575 211.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_created_gpadl) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 205.7008 cm -Q -q -1 0 0 1 50.01575 187.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_events) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 181.7008 cm -Q -q -1 0 0 1 50.01575 163.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_offer_channels) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 157.7008 cm -Q -q -1 0 0 1 50.01575 139.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_open_channels) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 133.7008 cm -Q -q -1 0 0 1 50.01575 115.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_supported_versions) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 109.7008 cm -Q -q -1 0 0 1 50.01575 91.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_physical_addresses) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (version) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 85.70079 cm -Q -q -1 0 0 1 50.01575 67.70079 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_supported_versions) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (mask) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (983055) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 66.18898 cm -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (129) Tj T* ET -Q -Q - -endstream -endobj -1334 0 obj -<< -/Length 6395 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_rescind_all_offers) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 757.7008 cm +1 0 0 1 40.01575 481.7008 cm Q q -1 0 0 1 40.01575 739.7008 cm +1 0 0 1 40.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 690.1008 cm +1 0 0 1 40.01575 414.1008 cm q 1 1 1 RG .3 w @@ -51494,20 +51424,20 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vmbusfuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 672.1008 cm +1 0 0 1 40.01575 396.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Hyper-V VMBus generic fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 656.1008 cm +1 0 0 1 40.01575 380.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 551.1008 cm +1 0 0 1 40.01575 275.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -51636,22 +51566,22 @@ Q Q Q q -1 0 0 1 40.01575 533.1008 cm +1 0 0 1 40.01575 257.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Note: the fuzzer is incompatible with native VMBus driver \() Tj /F3 10 Tf (vmbus.sys) Tj /F1 10 Tf (\). To use it, remove ) Tj /F3 10 Tf (vmbus.sys) Tj T* ET Q Q q -1 0 0 1 40.01575 527.1008 cm +1 0 0 1 40.01575 251.1008 cm Q q -1 0 0 1 40.01575 509.1008 cm +1 0 0 1 40.01575 233.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (VMBusFuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 497.1008 cm +1 0 0 1 50.01575 221.1008 cm q .933333 1 .8 rg n 33.35 0 294 12 re f* @@ -51659,52 +51589,74 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 491.1008 cm +1 0 0 1 50.01575 215.1008 cm Q q -1 0 0 1 50.01575 473.1008 cm +1 0 0 1 50.01575 197.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_post_msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 467.1008 cm +1 0 0 1 50.01575 191.1008 cm Q q -1 0 0 1 50.01575 449.1008 cm +1 0 0 1 50.01575 173.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 443.1008 cm +1 0 0 1 50.01575 167.1008 cm Q q -1 0 0 1 50.01575 425.1008 cm +1 0 0 1 50.01575 149.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 419.1008 cm +1 0 0 1 50.01575 143.1008 cm Q q -1 0 0 1 50.01575 401.1008 cm +1 0 0 1 50.01575 125.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (vmbus_test1_run) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 395.1008 cm +1 0 0 1 40.01575 119.1008 cm Q q -1 0 0 1 40.01575 377.1008 cm +1 0 0 1 40.01575 101.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 327.5008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (129) Tj T* ET +Q +Q + +endstream +endobj +1331 0 obj +<< +/Length 6705 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -51716,7 +51668,7 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vbox package) Tj T* ET Q Q q -1 0 0 1 40.01575 277.9008 cm +1 0 0 1 40.01575 716.5008 cm q 1 1 1 RG .3 w @@ -51728,16 +51680,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (vbox_crash_apicbase module) Tj T* Q Q q -1 0 0 1 40.01575 247.9008 cm +1 0 0 1 40.01575 686.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (PoC test for Host OS Crash when writing to IA32_APIC_BASE MSR \(Oracle VirtualBox CVE-2015-0377\)) Tj T* 0 0 .501961 rg (http://www.oracle.com/technetwork/topics/security/cpujan2015-1972971.html) Tj T* ET Q Q q -1 0 0 1 40.01575 241.9008 cm +1 0 0 1 40.01575 680.5008 cm Q q -1 0 0 1 40.01575 214.9008 cm +1 0 0 1 40.01575 653.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -51770,19 +51722,19 @@ Q Q Q q -1 0 0 1 40.01575 214.9008 cm +1 0 0 1 40.01575 653.5008 cm Q q -1 0 0 1 40.01575 208.9008 cm +1 0 0 1 40.01575 647.5008 cm Q q -1 0 0 1 40.01575 190.9008 cm +1 0 0 1 40.01575 629.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (vbox_crash_apicbase) Tj T* ET Q Q q -1 0 0 1 50.01575 178.9008 cm +1 0 0 1 50.01575 617.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -51790,15 +51742,191 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 172.9008 cm +1 0 0 1 50.01575 611.5008 cm Q q -1 0 0 1 50.01575 154.9008 cm +1 0 0 1 50.01575 593.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 40.01575 543.9008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (xen package) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 494.3008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (define module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 476.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Xen specific defines) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 470.3008 cm +Q +q +1 0 0 1 40.01575 452.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vector) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 446.3008 cm +Q +q +1 0 0 1 40.01575 428.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_status) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (brief) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 422.3008 cm +Q +q +1 0 0 1 40.01575 404.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_status_extended) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 398.3008 cm +Q +q +1 0 0 1 40.01575 380.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_invalid_hypercall_code) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 374.3008 cm +Q +q +1 0 0 1 40.01575 356.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_iverr) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (status) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (bits) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (64) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 350.3008 cm +Q +q +1 0 0 1 40.01575 332.3008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (varlist) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 282.7008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercall module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 264.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Xen specific hypercall functionality) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 258.7008 cm +Q +q +1 0 0 1 40.01575 240.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XenHypercall) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 228.7008 cm +q +.933333 1 .8 rg +n 33.35 0 306 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleHwAccess) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 222.7008 cm +Q +q +1 0 0 1 50.01575 204.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (iterations) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 198.7008 cm +Q +q +1 0 0 1 50.01575 180.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_hypercalls_randomly) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (codes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (iterations) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 174.7008 cm +Q +q +1 0 0 1 50.01575 156.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypervisor_info) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 150.7008 cm +Q +q +1 0 0 1 50.01575 132.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_value) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (arg) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 126.7008 cm +Q +q +1 0 0 1 50.01575 108.7008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 102.7008 cm +Q +q +1 0 0 1 50.01575 84.70079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypercall_status) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 78.70079 cm +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -51814,223 +51942,47 @@ Q endstream endobj -1335 0 obj +1332 0 obj << -/Length 7570 +/Length 9159 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 40.01575 766.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (xen package) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 716.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (define module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 698.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Xen specific defines) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 692.5008 cm -Q -q -1 0 0 1 40.01575 674.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_name) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (vector) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 668.5008 cm -Q -q -1 0 0 1 40.01575 650.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_status) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (brief) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 644.5008 cm -Q -q -1 0 0 1 40.01575 626.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypercall_status_extended) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (code) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 620.5008 cm -Q -q -1 0 0 1 40.01575 602.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_invalid_hypercall_code) Tj /F1 10 Tf .839216 .701961 0 rg ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 596.5008 cm -Q -q -1 0 0 1 40.01575 578.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_iverr) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (status) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (bits) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (64) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 572.5008 cm -Q -q -1 0 0 1 40.01575 554.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (set_variables) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (varlist) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 504.9008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercall module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 486.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Xen specific hypercall functionality) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 480.9008 cm -Q -q -1 0 0 1 40.01575 462.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (XenHypercall) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 450.9008 cm -q -.933333 1 .8 rg -n 33.35 0 306 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleHwAccess) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 444.9008 cm -Q -q -1 0 0 1 50.01575 426.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (code) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (iterations) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 420.9008 cm -Q -q -1 0 0 1 50.01575 402.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_hypercalls_randomly) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (codes) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (iterations) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 396.9008 cm -Q -q -1 0 0 1 50.01575 378.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_hypervisor_info) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 372.9008 cm -Q -q -1 0 0 1 50.01575 354.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_value) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (arg) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 348.9008 cm -Q -q -1 0 0 1 50.01575 330.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hypercall) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (args) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 324.9008 cm -Q -q -1 0 0 1 50.01575 306.9008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypercall_status) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 300.9008 cm -Q -q -1 0 0 1 50.01575 282.9008 cm +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (print_hypervisor_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (info) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 276.9008 cm +1 0 0 1 50.01575 757.7008 cm Q q -1 0 0 1 50.01575 258.9008 cm +1 0 0 1 50.01575 739.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (scan_hypercalls) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vector_list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 252.9008 cm +1 0 0 1 50.01575 733.7008 cm Q q -1 0 0 1 50.01575 234.9008 cm +1 0 0 1 50.01575 715.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (xen_version) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (cmd) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 228.9008 cm +1 0 0 1 40.01575 709.7008 cm Q q -1 0 0 1 40.01575 210.9008 cm +1 0 0 1 40.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 161.3008 cm +1 0 0 1 40.01575 642.1008 cm q 1 1 1 RG .3 w @@ -52042,119 +51994,67 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercallfuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 143.3008 cm +1 0 0 1 40.01575 624.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Xen hypercall fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 127.3008 cm +1 0 0 1 40.01575 608.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 66.18898 cm +1 0 0 1 40.01575 425.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 48.11181 Tm T* ET +BT 1 0 0 1 0 170 Tm T* ET q -1 0 0 1 20 34.11181 cm +1 0 0 1 20 156 cm q BT 1 0 0 1 0 14 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main.py) Tj ( ) Tj (-i) Tj ( ) Tj (-m) Tj ( ) Tj (tools.vmm.xen.hypercallfuzz) Tj ( ) Tj (\\) Tj /F1 10 Tf T* /F3 10 Tf (-a) Tj ( ) Tj (<) Tj (mode) Tj (>) Tj ([,) Tj (<) Tj (vector) Tj (>) Tj (,) Tj (<) Tj (iterations) Tj (>) Tj (]) Tj ( ) Tj (-l) Tj ( ) Tj (log.txt) Tj T* ET Q Q q -1 0 0 1 20 28.11181 cm -Q -q -1 0 0 1 20 -3 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q -1 0 0 1 20 18 cm -Q -q -1 0 0 1 20 18 cm +1 0 0 1 20 150 cm Q q 1 0 0 1 20 0 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET q -1 0 0 1 6 3 cm +1 0 0 1 20 144 cm +Q +q +1 0 0 1 20 144 cm +Q +q +1 0 0 1 20 36 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +q +1 0 0 1 6 93 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL 10.5 0 Td (\177) Tj T* -10.5 0 Td ET Q Q q -1 0 0 1 23 3 cm +1 0 0 1 23 93 cm q BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (mode) Tj /F1 10 Tf ( fuzzing mode) Tj T* ET Q Q q -1 0 0 1 23 -3 cm +1 0 0 1 23 87 cm Q q -Q -Q -Q -q -Q -Q -Q -q -Q -Q -Q -q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (131) Tj T* ET -Q -Q - -endstream -endobj -1336 0 obj -<< -/Length 8838 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 646.7008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 116 Tm T* ET -q -1 0 0 1 20 0 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q -1 0 0 1 20 36 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 6 77 Tm T* ET -q 1 0 0 1 23 -3 cm q 0 0 0 rg @@ -52367,17 +52267,17 @@ Q Q Q q -1 0 0 1 40.01575 628.7008 cm +1 0 0 1 40.01575 407.1008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Examples:) Tj T* ET Q Q q -1 0 0 1 40.01575 622.7008 cm +1 0 0 1 40.01575 401.1008 cm Q q -1 0 0 1 17.6378 586.7008 cm +1 0 0 1 17.6378 365.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -52393,19 +52293,19 @@ Q Q Q q -1 0 0 1 40.01575 586.7008 cm +1 0 0 1 40.01575 365.1008 cm Q q -1 0 0 1 40.01575 580.7008 cm +1 0 0 1 40.01575 359.1008 cm Q q -1 0 0 1 40.01575 562.7008 cm +1 0 0 1 40.01575 341.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (HypercallFuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 550.7008 cm +1 0 0 1 50.01575 329.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -52413,43 +52313,43 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 544.7008 cm +1 0 0 1 50.01575 323.1008 cm Q q -1 0 0 1 50.01575 526.7008 cm +1 0 0 1 50.01575 305.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_int) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (arg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (base) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (10) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (defvalue) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (10000) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 520.7008 cm +1 0 0 1 50.01575 299.1008 cm Q q -1 0 0 1 50.01575 502.7008 cm +1 0 0 1 50.01575 281.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 496.7008 cm +1 0 0 1 50.01575 275.1008 cm Q q -1 0 0 1 50.01575 478.7008 cm +1 0 0 1 50.01575 257.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 472.7008 cm +1 0 0 1 40.01575 251.1008 cm Q q -1 0 0 1 40.01575 454.7008 cm +1 0 0 1 40.01575 233.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET Q Q q -1 0 0 1 40.01575 405.1008 cm +1 0 0 1 40.01575 183.5008 cm q 1 1 1 RG .3 w @@ -52461,27 +52361,27 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (xsa188 module) Tj T* ET Q Q q -1 0 0 1 40.01575 375.1008 cm +1 0 0 1 40.01575 153.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Proof-of-concept module for Xen XSA-188 \() Tj 0 0 .501961 rg (https://xenbits.xen.org/xsa/advisory-188.html) Tj 0 0 0 rg (\) CVE-2016-7154: \223use) Tj T* (after free in FIFO event channel code\224 Discovered by Mikhail Gorobets) Tj T* ET Q Q q -1 0 0 1 40.01575 357.1008 cm +1 0 0 1 40.01575 135.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (This module triggers host crash on vulnerable Xen 4.4) Tj T* ET Q Q q -1 0 0 1 40.01575 341.1008 cm +1 0 0 1 40.01575 119.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 326.1008 cm +1 0 0 1 40.01575 104.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -52497,16 +52397,16 @@ Q Q Q q -1 0 0 1 40.01575 320.1008 cm +1 0 0 1 40.01575 98.50079 cm Q q -1 0 0 1 40.01575 302.1008 cm +1 0 0 1 40.01575 80.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (xsa188) Tj T* ET Q Q q -1 0 0 1 50.01575 290.1008 cm +1 0 0 1 50.01575 68.50079 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -52514,16 +52414,38 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 284.1008 cm +1 0 0 1 50.01575 66.18898 cm Q q -1 0 0 1 50.01575 266.1008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (131) Tj T* ET +Q +Q + +endstream +endobj +1333 0 obj +<< +/Length 8613 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 50.01575 763.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 216.5008 cm +1 0 0 1 40.01575 714.1008 cm q 1 1 1 RG .3 w @@ -52535,22 +52457,22 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (common module) Tj T* ET Q Q q -1 0 0 1 40.01575 198.5008 cm +1 0 0 1 40.01575 696.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Common functionality for VMM related modules/tools) Tj T* ET Q Q q -1 0 0 1 40.01575 192.5008 cm +1 0 0 1 40.01575 690.1008 cm Q q -1 0 0 1 40.01575 174.5008 cm +1 0 0 1 40.01575 672.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BaseModuleDebug) Tj T* ET Q Q q -1 0 0 1 50.01575 162.5008 cm +1 0 0 1 50.01575 660.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -52558,42 +52480,237 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 156.5008 cm +1 0 0 1 50.01575 654.1008 cm Q q -1 0 0 1 50.01575 138.5008 cm +1 0 0 1 50.01575 636.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dbg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 132.5008 cm +1 0 0 1 50.01575 630.1008 cm Q q -1 0 0 1 50.01575 114.5008 cm +1 0 0 1 50.01575 612.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (err) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 108.5008 cm +1 0 0 1 50.01575 606.1008 cm Q q -1 0 0 1 50.01575 90.50079 cm +1 0 0 1 50.01575 588.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fatal) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 84.50079 cm +1 0 0 1 50.01575 582.1008 cm Q q -1 0 0 1 50.01575 66.50079 cm +1 0 0 1 50.01575 564.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hex) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (title) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (data) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (w) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (16) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q +1 0 0 1 50.01575 558.1008 cm +Q +q +1 0 0 1 50.01575 540.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (info_bitwise) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 534.1008 cm +Q +q +1 0 0 1 50.01575 516.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 510.1008 cm +Q +q +1 0 0 1 40.01575 492.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BaseModuleHwAccess) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 480.1008 cm +q +.933333 1 .8 rg +n 33.35 0 300 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleSupport) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 474.1008 cm +Q +q +1 0 0 1 50.01575 456.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 450.1008 cm +Q +q +1 0 0 1 50.01575 432.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rdmsr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (msr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 426.1008 cm +Q +q +1 0 0 1 50.01575 408.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (wrmsr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (msr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 402.1008 cm +Q +q +1 0 0 1 40.01575 384.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BaseModuleSupport) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 372.1008 cm +q +.933333 1 .8 rg +n 33.35 0 288 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 366.1008 cm +Q +q +1 0 0 1 50.01575 348.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 342.1008 cm +Q +q +1 0 0 1 50.01575 324.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 318.1008 cm +Q +q +1 0 0 1 50.01575 300.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (statuses) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (padding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 294.1008 cm +Q +q +1 0 0 1 50.01575 276.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_event) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 270.1008 cm +Q +q +1 0 0 1 50.01575 252.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_print) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (title) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 246.1008 cm +Q +q +1 0 0 1 50.01575 228.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_reset) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 222.1008 cm +Q +q +1 0 0 1 40.01575 204.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_int_arg) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (arg) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 198.1008 cm +Q +q +1 0 0 1 40.01575 180.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 174.1008 cm +Q +q +1 0 0 1 40.01575 156.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_hciv) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (rep_start) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rep_count) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (call_code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fast) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 150.1008 cm +Q +q +1 0 0 1 40.01575 132.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (overwrite) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (string) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (position) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 126.1008 cm +Q +q +1 0 0 1 40.01575 108.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rand_dd) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (n) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rndbytes) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rndbits) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 102.1008 cm +Q +q +1 0 0 1 40.01575 84.10079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (session_logger) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (log) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (details) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 72.10079 cm +q +.933333 1 .8 rg +n 33.35 0 36 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET +Q +Q +q 1 0 0 1 50.01575 66.18898 cm Q q @@ -52612,16 +52729,16 @@ Q endstream endobj -1337 0 obj +1334 0 obj << -/Length 8432 +/Length 7458 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q 1 0 0 1 50.01575 763.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (info_bitwise) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (reg) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (closefile) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q @@ -52630,7 +52747,7 @@ Q q 1 0 0 1 50.01575 739.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (msg) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q @@ -52639,215 +52756,20 @@ Q q 1 0 0 1 40.01575 715.7008 cm q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BaseModuleHwAccess) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 703.7008 cm -q -.933333 1 .8 rg -n 33.35 0 300 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleSupport) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 697.7008 cm -Q -q -1 0 0 1 50.01575 679.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (cpuid_info) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (ecx) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (desc) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 673.7008 cm -Q -q -1 0 0 1 50.01575 655.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rdmsr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (msr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 649.7008 cm -Q -q -1 0 0 1 50.01575 631.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (wrmsr) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (msr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (value) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 625.7008 cm -Q -q -1 0 0 1 40.01575 607.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (BaseModuleSupport) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 595.7008 cm -q -.933333 1 .8 rg -n 33.35 0 288 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modules.tools.vmm.common.BaseModuleDebug) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 589.7008 cm -Q -q -1 0 0 1 50.01575 571.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (add_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (status) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 565.7008 cm -Q -q -1 0 0 1 50.01575 547.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 541.7008 cm -Q -q -1 0 0 1 50.01575 523.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_initial_data) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (statuses) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (vector) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (padding) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg ('\\x00') Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 517.7008 cm -Q -q -1 0 0 1 50.01575 499.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_event) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 493.7008 cm -Q -q -1 0 0 1 50.01575 475.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_print) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (title) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 469.7008 cm -Q -q -1 0 0 1 50.01575 451.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (stats_reset) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 445.7008 cm -Q -q -1 0 0 1 40.01575 427.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_int_arg) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (arg) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 421.7008 cm -Q -q -1 0 0 1 40.01575 403.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (getrandbits) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (k) Tj .839216 .701961 0 rg (\) ) Tj /F7 10 Tf 12 TL (\256) Tj /F1 10 Tf 12 TL ( ) Tj 0 0 0 rg (x. Generates an int with k random bits.) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 397.7008 cm -Q -q -1 0 0 1 40.01575 379.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (hv_hciv) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (rep_start) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rep_count) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (call_code) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (fast) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (0) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 373.7008 cm -Q -q -1 0 0 1 40.01575 355.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (overwrite) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (buffer) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (string) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (position) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 349.7008 cm -Q -q -1 0 0 1 40.01575 331.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (rand_dd) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (n) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rndbytes) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (, ) Tj .396078 .588235 .639216 rg (rndbits) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1) Tj .839216 .701961 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 325.7008 cm -Q -q -1 0 0 1 40.01575 307.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (session_logger) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (log) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (details) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 295.7008 cm -q -.933333 1 .8 rg -n 33.35 0 36 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (object) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 289.7008 cm -Q -q -1 0 0 1 50.01575 271.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (closefile) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 265.7008 cm -Q -q -1 0 0 1 50.01575 247.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (write) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (message) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 241.7008 cm -Q -q -1 0 0 1 40.01575 223.7008 cm -q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (uuid) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (id) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 217.7008 cm +1 0 0 1 40.01575 709.7008 cm Q q -1 0 0 1 40.01575 199.7008 cm +1 0 0 1 40.01575 691.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (weighted_choice) Tj /F1 10 Tf .839216 .701961 0 rg ( \() Tj .396078 .588235 .639216 rg (choices) Tj .839216 .701961 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 150.1008 cm +1 0 0 1 40.01575 642.1008 cm q 1 1 1 RG .3 w @@ -52859,16 +52781,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (cpuid_fuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 132.1008 cm +1 0 0 1 40.01575 624.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple CPUID VMM emulation fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 126.1008 cm +1 0 0 1 40.01575 618.1008 cm Q q -1 0 0 1 40.01575 99.10079 cm +1 0 0 1 40.01575 591.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -52901,18 +52823,212 @@ Q Q Q q -1 0 0 1 40.01575 99.10079 cm +1 0 0 1 40.01575 591.1008 cm Q q -1 0 0 1 40.01575 93.10079 cm +1 0 0 1 40.01575 585.1008 cm Q q -1 0 0 1 40.01575 75.10079 cm +1 0 0 1 40.01575 567.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (cpuid_fuzz) Tj T* ET Q Q q +1 0 0 1 50.01575 555.1008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 549.1008 cm +Q +q +1 0 0 1 50.01575 531.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_CPUID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax_start) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (random_order) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 525.1008 cm +Q +q +1 0 0 1 50.01575 507.1008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 457.5008 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ept_finder module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 439.5008 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 424.5008 cm +q +0 0 0 rg +BT /F1 10 Tf 12 TL ET +BT 1 0 0 1 0 2 Tm T* ET +q +1 0 0 1 20 0 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main.py) Tj ( ) Tj (-i) Tj ( ) Tj (-m) Tj ( ) Tj (tools.vmm.ept_finder) Tj T* ET +Q +Q +q +Q +Q +Q +q +1 0 0 1 40.01575 418.5008 cm +Q +q +1 0 0 1 40.01575 400.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_extended_page_tables_from_file) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (read_from_file) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (par) Tj 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 388.5008 cm +q +.933333 1 .8 rg +n 33.35 0 246 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_extended_page_tables) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 382.5008 cm +Q +q +1 0 0 1 50.01575 364.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 358.5008 cm +Q +q +1 0 0 1 40.01575 340.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ept_finder) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 328.5008 cm +q +.933333 1 .8 rg +n 33.35 0 192 12 re f* +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 322.5008 cm +Q +q +1 0 0 1 50.01575 304.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_dram) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (end_pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1048576) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 298.5008 cm +Q +q +1 0 0 1 50.01575 280.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_ept_pt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_addr_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mincount) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (level) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 274.5008 cm +Q +q +1 0 0 1 50.01575 256.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_vmcs_by_ept) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ept_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (revision_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 250.5008 cm +Q +q +1 0 0 1 50.01575 232.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_memory_ranges) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 226.5008 cm +Q +q +1 0 0 1 50.01575 208.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 202.5008 cm +Q +q +1 0 0 1 50.01575 184.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 178.5008 cm +Q +q +1 0 0 1 50.01575 160.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET +Q +Q +q +1 0 0 1 50.01575 154.5008 cm +Q +q +1 0 0 1 50.01575 136.5008 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 86.90079 cm +q +1 1 1 RG +.3 w +.870588 .556863 .086275 rg +n -10 0 525.2441 15.6 re B* +Q +q +BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercallfuzz module) Tj T* ET +Q +Q +q +1 0 0 1 40.01575 68.90079 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Pretty simple VMM hypercall fuzzer) Tj T* ET +Q +Q +q 1 0 0 1 34.01575 795.874 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET @@ -52928,215 +53044,21 @@ Q endstream endobj -1338 0 obj +1335 0 obj << -/Length 8994 +/Length 8421 >> stream 1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET q -1 0 0 1 50.01575 763.7008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 757.7008 cm -Q -q -1 0 0 1 50.01575 739.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_CPUID) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (eax_start) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (random_order) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 733.7008 cm -Q -q -1 0 0 1 50.01575 715.7008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 666.1008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (ept_finder module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 648.1008 cm +1 0 0 1 40.01575 763.7008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET Q Q q -1 0 0 1 40.01575 633.1008 cm -q -0 0 0 rg -BT /F1 10 Tf 12 TL ET -BT 1 0 0 1 0 2 Tm T* ET -q -1 0 0 1 20 0 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F3 10 Tf 0 0 0 rg (chipsec_main.py) Tj ( ) Tj (-i) Tj ( ) Tj (-m) Tj ( ) Tj (tools.vmm.ept_finder) Tj T* ET -Q -Q -q -Q -Q -Q -q -1 0 0 1 40.01575 627.1008 cm -Q -q -1 0 0 1 40.01575 609.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (c_extended_page_tables_from_file) Tj /F1 10 Tf ( \() Tj .396078 .588235 .639216 rg (cs) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (read_from_file) Tj 0 0 0 rg (, ) Tj .396078 .588235 .639216 rg (par) Tj 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 597.1008 cm -q -.933333 1 .8 rg -n 33.35 0 246 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.hal.paging.c_extended_page_tables) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 591.1008 cm -Q -q -1 0 0 1 50.01575 573.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (readmem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (name) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 567.1008 cm -Q -q -1 0 0 1 40.01575 549.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (ept_finder) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 537.1008 cm -q -.933333 1 .8 rg -n 33.35 0 192 12 re f* -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.module_common.BaseModule) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 531.1008 cm -Q -q -1 0 0 1 50.01575 513.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (dump_dram) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (filename) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (end_pa) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (buffer_size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (1048576) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 507.1008 cm -Q -q -1 0 0 1 50.01575 489.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_ept_pt) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pt_addr_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (mincount) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (level) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 483.1008 cm -Q -q -1 0 0 1 50.01575 465.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_vmcs_by_ept) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (ept_list) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (revision_id) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 459.1008 cm -Q -q -1 0 0 1 50.01575 441.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (get_memory_ranges) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 435.1008 cm -Q -q -1 0 0 1 50.01575 417.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 411.1008 cm -Q -q -1 0 0 1 50.01575 393.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (read_physical_mem_dword) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (addr) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 387.1008 cm -Q -q -1 0 0 1 50.01575 369.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET -Q -Q -q -1 0 0 1 50.01575 363.1008 cm -Q -q -1 0 0 1 50.01575 345.1008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 295.5008 cm -q -1 1 1 RG -.3 w -.870588 .556863 .086275 rg -n -10 0 525.2441 15.6 re B* -Q -q -BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (hypercallfuzz module) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 277.5008 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Pretty simple VMM hypercall fuzzer) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 261.5008 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F2 10 Tf 12 TL (Usage:) Tj T* ET -Q -Q -q -1 0 0 1 40.01575 117.5008 cm +1 0 0 1 40.01575 619.7008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53340,16 +53262,16 @@ Q Q Q q -1 0 0 1 40.01575 111.5008 cm +1 0 0 1 40.01575 613.7008 cm Q q -1 0 0 1 40.01575 93.50079 cm +1 0 0 1 40.01575 595.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (hypercallfuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 81.50079 cm +1 0 0 1 50.01575 583.7008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -53357,71 +53279,49 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 75.50079 cm +1 0 0 1 50.01575 577.7008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (134) Tj T* ET -Q -Q - -endstream -endobj -1339 0 obj -<< -/Length 7439 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 50.01575 559.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_generic_hypercalls) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 50.01575 553.7008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 50.01575 535.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (is_supported) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 60.01575 715.7008 cm +1 0 0 1 60.01575 511.7008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (This method should be overwritten by the module returning True or False depending whether or not this module) Tj T* (is supported in the currently running platform. To access the currently running platform use) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 50.01575 505.7008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 487.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 481.7008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 463.7008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (usage) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 40.01575 618.1008 cm +1 0 0 1 40.01575 414.1008 cm q 1 1 1 RG .3 w @@ -53433,16 +53333,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (iofuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 600.1008 cm +1 0 0 1 40.01575 396.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple port I/O VMM emulation fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 594.1008 cm +1 0 0 1 40.01575 390.1008 cm Q q -1 0 0 1 40.01575 567.1008 cm +1 0 0 1 40.01575 363.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53475,19 +53375,19 @@ Q Q Q q -1 0 0 1 40.01575 567.1008 cm +1 0 0 1 40.01575 363.1008 cm Q q -1 0 0 1 40.01575 561.1008 cm +1 0 0 1 40.01575 357.1008 cm Q q -1 0 0 1 40.01575 543.1008 cm +1 0 0 1 40.01575 339.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (iofuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 531.1008 cm +1 0 0 1 50.01575 327.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -53495,25 +53395,25 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 525.1008 cm +1 0 0 1 50.01575 321.1008 cm Q q -1 0 0 1 50.01575 507.1008 cm +1 0 0 1 50.01575 303.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_ports) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (iterations) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (write_count) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (random_order) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 501.1008 cm +1 0 0 1 50.01575 297.1008 cm Q q -1 0 0 1 50.01575 483.1008 cm +1 0 0 1 50.01575 279.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 433.5008 cm +1 0 0 1 40.01575 229.5008 cm q 1 1 1 RG .3 w @@ -53525,16 +53425,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (msr_fuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 415.5008 cm +1 0 0 1 40.01575 211.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple CPU Module Specific Register \(MSR\) VMM emulation fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 409.5008 cm +1 0 0 1 40.01575 205.5008 cm Q q -1 0 0 1 40.01575 382.5008 cm +1 0 0 1 40.01575 178.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53567,19 +53467,19 @@ Q Q Q q -1 0 0 1 40.01575 382.5008 cm +1 0 0 1 40.01575 178.5008 cm Q q -1 0 0 1 40.01575 376.5008 cm +1 0 0 1 40.01575 172.5008 cm Q q -1 0 0 1 40.01575 358.5008 cm +1 0 0 1 40.01575 154.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (msr_fuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 346.5008 cm +1 0 0 1 50.01575 142.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -53587,25 +53487,47 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 340.5008 cm +1 0 0 1 50.01575 136.5008 cm Q q -1 0 0 1 50.01575 322.5008 cm +1 0 0 1 50.01575 118.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_MSRs) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (msr_addr_start) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (random_order) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (False) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 316.5008 cm +1 0 0 1 50.01575 112.5008 cm Q q -1 0 0 1 50.01575 298.5008 cm +1 0 0 1 50.01575 94.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 248.9008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (134) Tj T* ET +Q +Q + +endstream +endobj +1336 0 obj +<< +/Length 10289 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -53617,16 +53539,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (pcie_fuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 230.9008 cm +1 0 0 1 40.01575 748.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Simple PCIe device Memory-Mapped I/O \(MMIO\) and I/O ranges VMM emulation fuzzer) Tj T* ET Q Q q -1 0 0 1 40.01575 224.9008 cm +1 0 0 1 40.01575 742.1008 cm Q q -1 0 0 1 40.01575 197.9008 cm +1 0 0 1 40.01575 715.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53659,19 +53581,19 @@ Q Q Q q -1 0 0 1 40.01575 197.9008 cm +1 0 0 1 40.01575 715.1008 cm Q q -1 0 0 1 40.01575 191.9008 cm +1 0 0 1 40.01575 709.1008 cm Q q -1 0 0 1 40.01575 173.9008 cm +1 0 0 1 40.01575 691.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (pcie_fuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 161.9008 cm +1 0 0 1 50.01575 679.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -53679,128 +53601,106 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 155.9008 cm +1 0 0 1 50.01575 673.1008 cm Q q -1 0 0 1 50.01575 137.9008 cm +1 0 0 1 50.01575 655.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (find_active_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 131.9008 cm +1 0 0 1 50.01575 649.1008 cm Q q -1 0 0 1 50.01575 113.9008 cm +1 0 0 1 50.01575 631.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_io_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (256) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 107.9008 cm +1 0 0 1 50.01575 625.1008 cm Q q -1 0 0 1 50.01575 89.90079 cm +1 0 0 1 50.01575 607.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 83.90079 cm +1 0 0 1 50.01575 601.1008 cm Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (135) Tj T* ET -Q -Q - -endstream -endobj -1340 0 obj -<< -/Length 9600 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 50.01575 763.7008 cm +1 0 0 1 50.01575 583.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar_in_active_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 757.7008 cm +1 0 0 1 50.01575 577.1008 cm Q q -1 0 0 1 50.01575 739.7008 cm +1 0 0 1 50.01575 559.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar_in_active_range_bit_flip) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 733.7008 cm +1 0 0 1 50.01575 553.1008 cm Q q -1 0 0 1 50.01575 715.7008 cm +1 0 0 1 50.01575 535.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar_in_active_range_random) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (list) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 709.7008 cm +1 0 0 1 50.01575 529.1008 cm Q q -1 0 0 1 50.01575 691.7008 cm +1 0 0 1 50.01575 511.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar_random) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 685.7008 cm +1 0 0 1 50.01575 505.1008 cm Q q -1 0 0 1 50.01575 667.7008 cm +1 0 0 1 50.01575 487.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_offset) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 661.7008 cm +1 0 0 1 50.01575 481.1008 cm Q q -1 0 0 1 50.01575 643.7008 cm +1 0 0 1 50.01575 463.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_pcie_device) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (b) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (d) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (f) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 637.7008 cm +1 0 0 1 50.01575 457.1008 cm Q q -1 0 0 1 50.01575 619.7008 cm +1 0 0 1 50.01575 439.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_unaligned) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 613.7008 cm +1 0 0 1 50.01575 433.1008 cm Q q -1 0 0 1 50.01575 595.7008 cm +1 0 0 1 50.01575 415.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 546.1008 cm +1 0 0 1 40.01575 365.5008 cm q 1 1 1 RG .3 w @@ -53812,16 +53712,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (pcie_overlap_fuzz module) Tj T* ET Q Q q -1 0 0 1 40.01575 516.1008 cm +1 0 0 1 40.01575 335.5008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (PCIe device Memory-Mapped I/O \(MMIO\) ranges VMM emulation fuzzer which first overlaps MMIO BARs of all) Tj T* (available PCIe devices then fuzzes them by writing garbage if corresponding option is enabled) Tj T* ET Q Q q -1 0 0 1 40.01575 510.1008 cm +1 0 0 1 40.01575 329.5008 cm Q q -1 0 0 1 40.01575 483.1008 cm +1 0 0 1 40.01575 302.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53854,19 +53754,19 @@ Q Q Q q -1 0 0 1 40.01575 483.1008 cm +1 0 0 1 40.01575 302.5008 cm Q q -1 0 0 1 40.01575 477.1008 cm +1 0 0 1 40.01575 296.5008 cm Q q -1 0 0 1 40.01575 459.1008 cm +1 0 0 1 40.01575 278.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (pcie_overlap_fuzz) Tj T* ET Q Q q -1 0 0 1 50.01575 447.1008 cm +1 0 0 1 50.01575 266.5008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -53874,70 +53774,92 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 441.1008 cm +1 0 0 1 50.01575 260.5008 cm Q q -1 0 0 1 50.01575 423.1008 cm +1 0 0 1 50.01575 242.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 417.1008 cm +1 0 0 1 50.01575 236.5008 cm Q q -1 0 0 1 50.01575 399.1008 cm +1 0 0 1 50.01575 218.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_mmio_bar_random) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (size) Tj .619608 .415686 .533333 rg (=) Tj .419608 .623529 1 rg (4096) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 393.1008 cm +1 0 0 1 50.01575 212.5008 cm Q q -1 0 0 1 50.01575 375.1008 cm +1 0 0 1 50.01575 194.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_offset) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_value) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 369.1008 cm +1 0 0 1 50.01575 188.5008 cm Q q -1 0 0 1 50.01575 351.1008 cm +1 0 0 1 50.01575 170.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_overlap_pcie_device) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (pcie_devices) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 345.1008 cm +1 0 0 1 50.01575 164.5008 cm Q q -1 0 0 1 50.01575 327.1008 cm +1 0 0 1 50.01575 146.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (fuzz_unaligned) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bar) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (reg_off) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 321.1008 cm +1 0 0 1 50.01575 140.5008 cm Q q -1 0 0 1 50.01575 303.1008 cm +1 0 0 1 50.01575 122.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (overlap_mmio_range) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (bus1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off1) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (bus2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (dev2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (fun2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (is64bit2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (off2) Tj /F2 10 Tf 0 0 0 rg (, ) Tj /F1 10 Tf .396078 .588235 .639216 rg (direction) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 297.1008 cm +1 0 0 1 50.01575 116.5008 cm Q q -1 0 0 1 50.01575 279.1008 cm +1 0 0 1 50.01575 98.50079 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 229.5008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (135) Tj T* ET +Q +Q + +endstream +endobj +1337 0 obj +<< +/Length 12827 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 766.1008 cm q 1 1 1 RG .3 w @@ -53949,16 +53871,16 @@ BT 1 0 0 1 0 1.6 Tm 9.6 TL /F5 8 Tf 1 1 1 rg (venom module) Tj T* ET Q Q q -1 0 0 1 40.01575 199.5008 cm +1 0 0 1 40.01575 736.1008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (QEMU VENOM vulnerability DoS PoC test Module is based on PoC by Marcus Meissner) Tj T* (\() Tj 0 0 .501961 rg (https://marc.info/?l=oss-security) Tj (&) Tj (m=143155206320935) Tj (&) Tj (w=2) Tj 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 40.01575 193.5008 cm +1 0 0 1 40.01575 730.1008 cm Q q -1 0 0 1 40.01575 166.5008 cm +1 0 0 1 40.01575 703.1008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -53991,19 +53913,19 @@ Q Q Q q -1 0 0 1 40.01575 166.5008 cm +1 0 0 1 40.01575 703.1008 cm Q q -1 0 0 1 40.01575 160.5008 cm +1 0 0 1 40.01575 697.1008 cm Q q -1 0 0 1 40.01575 142.5008 cm +1 0 0 1 40.01575 679.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F4 10 Tf 0 0 0 rg (class ) Tj /F6 10 Tf (venom) Tj T* ET Q Q q -1 0 0 1 50.01575 130.5008 cm +1 0 0 1 50.01575 667.1008 cm q .933333 1 .8 rg n 33.35 0 192 12 re f* @@ -54011,47 +53933,25 @@ BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Bases: ) Tj /F6 10 Tf (chipsec.modul Q Q q -1 0 0 1 50.01575 124.5008 cm +1 0 0 1 50.01575 661.1008 cm Q q -1 0 0 1 50.01575 106.5008 cm +1 0 0 1 50.01575 643.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (run) Tj /F2 10 Tf ( \() Tj /F1 10 Tf .396078 .588235 .639216 rg (module_argv) Tj /F2 10 Tf 0 0 0 rg (\)) Tj T* ET Q Q q -1 0 0 1 50.01575 100.5008 cm +1 0 0 1 50.01575 637.1008 cm Q q -1 0 0 1 50.01575 82.50079 cm +1 0 0 1 50.01575 619.1008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F6 10 Tf 0 0 0 rg (venom_impl) Tj /F2 10 Tf ( \(\)) Tj T* ET Q Q q -1 0 0 1 34.01575 795.874 cm -q -BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET -Q -Q -q -1 0 0 1 34.01575 34.01575 cm -q -0 0 0 rg -BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (136) Tj T* ET -Q -Q - -endstream -endobj -1341 0 obj -<< -/Length 11653 ->> -stream -1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET -q -1 0 0 1 40.01575 758.9008 cm +1 0 0 1 40.01575 562.3008 cm q 1 1 1 RG .3 w @@ -54063,32 +53963,32 @@ BT 1 0 0 1 0 2.8 Tm 16.8 TL /F5 14 Tf 1 1 1 rg (Writing Your Own Modules) Tj T* Q Q q -1 0 0 1 40.01575 728.9008 cm +1 0 0 1 40.01575 532.3008 cm q BT 1 0 0 1 0 14 Tm 12 TL /F1 10 Tf 0 0 0 rg (Your module class should subclass BaseModule and implement at least the methods named ) Tj /F3 10 Tf (is_supported) Tj /F1 10 Tf ( and) Tj T* /F3 10 Tf (run) Tj /F1 10 Tf (. When chipsec_main runs, it will first run ) Tj /F3 10 Tf (is_supported) Tj /F1 10 Tf ( and if that returns true, then it will call ) Tj /F3 10 Tf (run) Tj /F1 10 Tf (.) Tj T* ET Q Q q -1 0 0 1 40.01575 662.9008 cm +1 0 0 1 40.01575 466.3008 cm q BT 1 0 0 1 0 50 Tm 12 TL /F1 10 Tf 0 0 0 rg (As of CHIPSEC version 1.2.0, CHIPSEC implements an abstract name for platform ) Tj /F4 10 Tf (controls) Tj /F1 10 Tf (. Module authors are) Tj T* (encouraged to create controls in the XML configuration files for important platform configuration information and then) Tj T* (use ) Tj /F3 10 Tf (get_control) Tj /F1 10 Tf ( and ) Tj /F3 10 Tf (set_control) Tj /F1 10 Tf ( within modules. This abstraction allows modules to test for the abstract) Tj T* (control without knowning which register provides it. \(This is especially important for test reuse across platform) Tj T* (generations.\)) Tj T* ET Q Q q -1 0 0 1 40.01575 644.9008 cm +1 0 0 1 40.01575 448.3008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (Most modules read some platform configuration and then pass or fail based on the result. For example:) Tj T* ET Q Q q -1 0 0 1 40.01575 638.9008 cm +1 0 0 1 40.01575 442.3008 cm Q q -1 0 0 1 40.01575 638.9008 cm +1 0 0 1 40.01575 442.3008 cm Q q -1 0 0 1 40.01575 610.5008 cm +1 0 0 1 40.01575 413.9008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54154,10 +54054,10 @@ Q Q Q q -1 0 0 1 40.01575 604.5008 cm +1 0 0 1 40.01575 407.9008 cm Q q -1 0 0 1 40.01575 576.1008 cm +1 0 0 1 40.01575 379.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54228,10 +54128,10 @@ Q Q Q q -1 0 0 1 40.01575 570.1008 cm +1 0 0 1 40.01575 373.5008 cm Q q -1 0 0 1 40.01575 532.1008 cm +1 0 0 1 40.01575 335.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54316,10 +54216,10 @@ Q Q Q q -1 0 0 1 40.01575 526.1008 cm +1 0 0 1 40.01575 329.5008 cm Q q -1 0 0 1 40.01575 488.1008 cm +1 0 0 1 40.01575 291.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54388,29 +54288,29 @@ Q Q Q q -1 0 0 1 40.01575 488.1008 cm +1 0 0 1 40.01575 291.5008 cm Q q -1 0 0 1 40.01575 458.1008 cm +1 0 0 1 40.01575 261.5008 cm q 0 0 0 rg BT 1 0 0 1 0 14 Tm /F1 10 Tf 12 TL (The CHIPSEC HAL and other APIs are also available within these modules. See the next sections for details about) Tj T* (the available functionality.) Tj T* ET Q Q q -1 0 0 1 40.01575 440.1008 cm +1 0 0 1 40.01575 243.5008 cm q BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Copy your module into the ) Tj /F3 10 Tf (chipsec/modules/) Tj /F1 10 Tf ( directory structure) Tj T* ET Q Q q -1 0 0 1 40.01575 434.1008 cm +1 0 0 1 40.01575 237.5008 cm Q q -1 0 0 1 40.01575 434.1008 cm +1 0 0 1 40.01575 237.5008 cm Q q -1 0 0 1 40.01575 410.1008 cm +1 0 0 1 40.01575 213.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54432,10 +54332,10 @@ Q Q Q q -1 0 0 1 40.01575 404.1008 cm +1 0 0 1 40.01575 207.5008 cm Q q -1 0 0 1 40.01575 368.1008 cm +1 0 0 1 40.01575 171.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54457,10 +54357,10 @@ Q Q Q q -1 0 0 1 40.01575 362.1008 cm +1 0 0 1 40.01575 165.5008 cm Q q -1 0 0 1 40.01575 338.1008 cm +1 0 0 1 40.01575 141.5008 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54482,23 +54382,23 @@ Q Q Q q -1 0 0 1 40.01575 338.1008 cm +1 0 0 1 40.01575 141.5008 cm Q q -1 0 0 1 40.01575 320.1008 cm +1 0 0 1 40.01575 123.5008 cm q 0 0 0 rg BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (If a new platform needs to be added:) Tj T* ET Q Q q -1 0 0 1 40.01575 314.1008 cm +1 0 0 1 40.01575 117.5008 cm Q q -1 0 0 1 40.01575 314.1008 cm +1 0 0 1 40.01575 117.5008 cm Q q -1 0 0 1 40.01575 266.1008 cm +1 0 0 1 40.01575 69.50079 cm q 0 0 0 rg BT /F1 10 Tf 12 TL ET @@ -54520,13 +54420,35 @@ Q Q Q q -1 0 0 1 40.01575 266.1008 cm +1 0 0 1 40.01575 69.50079 cm Q q -1 0 0 1 40.01575 254.1008 cm +1 0 0 1 40.01575 66.18898 cm Q q -1 0 0 1 40.01575 197.3008 cm +1 0 0 1 34.01575 795.874 cm +q +BT 1 0 0 1 0 2 Tm 12 TL /F1 10 Tf 0 0 0 rg (Module & Command Development) Tj T* ET +Q +Q +q +1 0 0 1 34.01575 34.01575 cm +q +0 0 0 rg +BT 1 0 0 1 0 2 Tm /F1 10 Tf 12 TL (136) Tj T* ET +Q +Q + +endstream +endobj +1338 0 obj +<< +/Length 768 +>> +stream +1 0 0 1 0 0 cm BT /F1 12 Tf 14.4 TL ET +q +1 0 0 1 40.01575 718.9008 cm q 1 1 .8 rg n 0 56.8 515.2441 -56.8 re f* @@ -54559,7 +54481,7 @@ Q Q Q q -1 0 0 1 40.01575 191.3008 cm +1 0 0 1 40.01575 712.9008 cm Q q 1 0 0 1 34.01575 795.874 cm @@ -54577,766 +54499,766 @@ Q endstream endobj -1342 0 obj +1339 0 obj << -/Nums [ 0 1343 0 R 1 1344 0 R 2 1345 0 R 3 1346 0 R 4 1347 0 R - 5 1348 0 R 6 1349 0 R 7 1350 0 R 8 1351 0 R 9 1352 0 R - 10 1353 0 R 11 1354 0 R 12 1355 0 R 13 1356 0 R 14 1357 0 R - 15 1358 0 R 16 1359 0 R 17 1360 0 R 18 1361 0 R 19 1362 0 R - 20 1363 0 R 21 1364 0 R 22 1365 0 R 23 1366 0 R 24 1367 0 R - 25 1368 0 R 26 1369 0 R 27 1370 0 R 28 1371 0 R 29 1372 0 R - 30 1373 0 R 31 1374 0 R 32 1375 0 R 33 1376 0 R 34 1377 0 R - 35 1378 0 R 36 1379 0 R 37 1380 0 R 38 1381 0 R 39 1382 0 R - 40 1383 0 R 41 1384 0 R 42 1385 0 R 43 1386 0 R 44 1387 0 R - 45 1388 0 R 46 1389 0 R 47 1390 0 R 48 1391 0 R 49 1392 0 R - 50 1393 0 R 51 1394 0 R 52 1395 0 R 53 1396 0 R 54 1397 0 R - 55 1398 0 R 56 1399 0 R 57 1400 0 R 58 1401 0 R 59 1402 0 R - 60 1403 0 R 61 1404 0 R 62 1405 0 R 63 1406 0 R 64 1407 0 R - 65 1408 0 R 66 1409 0 R 67 1410 0 R 68 1411 0 R 69 1412 0 R - 70 1413 0 R 71 1414 0 R 72 1415 0 R 73 1416 0 R 74 1417 0 R - 75 1418 0 R 76 1419 0 R 77 1420 0 R 78 1421 0 R 79 1422 0 R - 80 1423 0 R 81 1424 0 R 82 1425 0 R 83 1426 0 R 84 1427 0 R - 85 1428 0 R 86 1429 0 R 87 1430 0 R 88 1431 0 R 89 1432 0 R - 90 1433 0 R 91 1434 0 R 92 1435 0 R 93 1436 0 R 94 1437 0 R - 95 1438 0 R 96 1439 0 R 97 1440 0 R 98 1441 0 R 99 1442 0 R - 100 1443 0 R 101 1444 0 R 102 1445 0 R 103 1446 0 R 104 1447 0 R - 105 1448 0 R 106 1449 0 R 107 1450 0 R 108 1451 0 R 109 1452 0 R - 110 1453 0 R 111 1454 0 R 112 1455 0 R 113 1456 0 R 114 1457 0 R - 115 1458 0 R 116 1459 0 R 117 1460 0 R 118 1461 0 R 119 1462 0 R - 120 1463 0 R 121 1464 0 R 122 1465 0 R 123 1466 0 R 124 1467 0 R - 125 1468 0 R 126 1469 0 R 127 1470 0 R 128 1471 0 R 129 1472 0 R - 130 1473 0 R 131 1474 0 R 132 1475 0 R 133 1476 0 R 134 1477 0 R - 135 1478 0 R 136 1479 0 R 137 1480 0 R 138 1481 0 R 139 1482 0 R - 140 1483 0 R 141 1484 0 R 142 1485 0 R 143 1486 0 R 144 1487 0 R ] +/Nums [ 0 1340 0 R 1 1341 0 R 2 1342 0 R 3 1343 0 R 4 1344 0 R + 5 1345 0 R 6 1346 0 R 7 1347 0 R 8 1348 0 R 9 1349 0 R + 10 1350 0 R 11 1351 0 R 12 1352 0 R 13 1353 0 R 14 1354 0 R + 15 1355 0 R 16 1356 0 R 17 1357 0 R 18 1358 0 R 19 1359 0 R + 20 1360 0 R 21 1361 0 R 22 1362 0 R 23 1363 0 R 24 1364 0 R + 25 1365 0 R 26 1366 0 R 27 1367 0 R 28 1368 0 R 29 1369 0 R + 30 1370 0 R 31 1371 0 R 32 1372 0 R 33 1373 0 R 34 1374 0 R + 35 1375 0 R 36 1376 0 R 37 1377 0 R 38 1378 0 R 39 1379 0 R + 40 1380 0 R 41 1381 0 R 42 1382 0 R 43 1383 0 R 44 1384 0 R + 45 1385 0 R 46 1386 0 R 47 1387 0 R 48 1388 0 R 49 1389 0 R + 50 1390 0 R 51 1391 0 R 52 1392 0 R 53 1393 0 R 54 1394 0 R + 55 1395 0 R 56 1396 0 R 57 1397 0 R 58 1398 0 R 59 1399 0 R + 60 1400 0 R 61 1401 0 R 62 1402 0 R 63 1403 0 R 64 1404 0 R + 65 1405 0 R 66 1406 0 R 67 1407 0 R 68 1408 0 R 69 1409 0 R + 70 1410 0 R 71 1411 0 R 72 1412 0 R 73 1413 0 R 74 1414 0 R + 75 1415 0 R 76 1416 0 R 77 1417 0 R 78 1418 0 R 79 1419 0 R + 80 1420 0 R 81 1421 0 R 82 1422 0 R 83 1423 0 R 84 1424 0 R + 85 1425 0 R 86 1426 0 R 87 1427 0 R 88 1428 0 R 89 1429 0 R + 90 1430 0 R 91 1431 0 R 92 1432 0 R 93 1433 0 R 94 1434 0 R + 95 1435 0 R 96 1436 0 R 97 1437 0 R 98 1438 0 R 99 1439 0 R + 100 1440 0 R 101 1441 0 R 102 1442 0 R 103 1443 0 R 104 1444 0 R + 105 1445 0 R 106 1446 0 R 107 1447 0 R 108 1448 0 R 109 1449 0 R + 110 1450 0 R 111 1451 0 R 112 1452 0 R 113 1453 0 R 114 1454 0 R + 115 1455 0 R 116 1456 0 R 117 1457 0 R 118 1458 0 R 119 1459 0 R + 120 1460 0 R 121 1461 0 R 122 1462 0 R 123 1463 0 R 124 1464 0 R + 125 1465 0 R 126 1466 0 R 127 1467 0 R 128 1468 0 R 129 1469 0 R + 130 1470 0 R 131 1471 0 R 132 1472 0 R 133 1473 0 R 134 1474 0 R + 135 1475 0 R 136 1476 0 R 137 1477 0 R 138 1478 0 R 139 1479 0 R + 140 1480 0 R 141 1481 0 R 142 1482 0 R 143 1483 0 R 144 1484 0 R ] >> endobj -1343 0 obj +1340 0 obj << /S /D /St 1 >> endobj -1344 0 obj +1341 0 obj << /S /r /St 1 >> endobj -1345 0 obj +1342 0 obj << /S /r /St 2 >> endobj -1346 0 obj +1343 0 obj << /S /r /St 3 >> endobj -1347 0 obj +1344 0 obj << /S /r /St 4 >> endobj -1348 0 obj +1345 0 obj << /S /r /St 5 >> endobj -1349 0 obj +1346 0 obj << /S /r /St 6 >> endobj -1350 0 obj +1347 0 obj << /S /r /St 7 >> endobj -1351 0 obj +1348 0 obj << /S /D /St 1 >> endobj -1352 0 obj +1349 0 obj << /S /D /St 2 >> endobj -1353 0 obj +1350 0 obj << /S /D /St 3 >> endobj -1354 0 obj +1351 0 obj << /S /D /St 4 >> endobj -1355 0 obj +1352 0 obj << /S /D /St 5 >> endobj -1356 0 obj +1353 0 obj << /S /D /St 6 >> endobj -1357 0 obj +1354 0 obj << /S /D /St 7 >> endobj -1358 0 obj +1355 0 obj << /S /D /St 8 >> endobj -1359 0 obj +1356 0 obj << /S /D /St 9 >> endobj -1360 0 obj +1357 0 obj << /S /D /St 10 >> endobj -1361 0 obj +1358 0 obj << /S /D /St 11 >> endobj -1362 0 obj +1359 0 obj << /S /D /St 12 >> endobj -1363 0 obj +1360 0 obj << /S /D /St 13 >> endobj -1364 0 obj +1361 0 obj << /S /D /St 14 >> endobj -1365 0 obj +1362 0 obj << /S /D /St 15 >> endobj -1366 0 obj +1363 0 obj << /S /D /St 16 >> endobj -1367 0 obj +1364 0 obj << /S /D /St 17 >> endobj -1368 0 obj +1365 0 obj << /S /D /St 18 >> endobj -1369 0 obj +1366 0 obj << /S /D /St 19 >> endobj -1370 0 obj +1367 0 obj << /S /D /St 20 >> endobj -1371 0 obj +1368 0 obj << /S /D /St 21 >> endobj -1372 0 obj +1369 0 obj << /S /D /St 22 >> endobj -1373 0 obj +1370 0 obj << /S /D /St 23 >> endobj -1374 0 obj +1371 0 obj << /S /D /St 24 >> endobj -1375 0 obj +1372 0 obj << /S /D /St 25 >> endobj -1376 0 obj +1373 0 obj << /S /D /St 26 >> endobj -1377 0 obj +1374 0 obj << /S /D /St 27 >> endobj -1378 0 obj +1375 0 obj << /S /D /St 28 >> endobj -1379 0 obj +1376 0 obj << /S /D /St 29 >> endobj -1380 0 obj +1377 0 obj << /S /D /St 30 >> endobj -1381 0 obj +1378 0 obj << /S /D /St 31 >> endobj -1382 0 obj +1379 0 obj << /S /D /St 32 >> endobj -1383 0 obj +1380 0 obj << /S /D /St 33 >> endobj -1384 0 obj +1381 0 obj << /S /D /St 34 >> endobj -1385 0 obj +1382 0 obj << /S /D /St 35 >> endobj -1386 0 obj +1383 0 obj << /S /D /St 36 >> endobj -1387 0 obj +1384 0 obj << /S /D /St 37 >> endobj -1388 0 obj +1385 0 obj << /S /D /St 38 >> endobj -1389 0 obj +1386 0 obj << /S /D /St 39 >> endobj -1390 0 obj +1387 0 obj << /S /D /St 40 >> endobj -1391 0 obj +1388 0 obj << /S /D /St 41 >> endobj -1392 0 obj +1389 0 obj << /S /D /St 42 >> endobj -1393 0 obj +1390 0 obj << /S /D /St 43 >> endobj -1394 0 obj +1391 0 obj << /S /D /St 44 >> endobj -1395 0 obj +1392 0 obj << /S /D /St 45 >> endobj -1396 0 obj +1393 0 obj << /S /D /St 46 >> endobj -1397 0 obj +1394 0 obj << /S /D /St 47 >> endobj -1398 0 obj +1395 0 obj << /S /D /St 48 >> endobj -1399 0 obj +1396 0 obj << /S /D /St 49 >> endobj -1400 0 obj +1397 0 obj << /S /D /St 50 >> endobj -1401 0 obj +1398 0 obj << /S /D /St 51 >> endobj -1402 0 obj +1399 0 obj << /S /D /St 52 >> endobj -1403 0 obj +1400 0 obj << /S /D /St 53 >> endobj -1404 0 obj +1401 0 obj << /S /D /St 54 >> endobj -1405 0 obj +1402 0 obj << /S /D /St 55 >> endobj -1406 0 obj +1403 0 obj << /S /D /St 56 >> endobj -1407 0 obj +1404 0 obj << /S /D /St 57 >> endobj -1408 0 obj +1405 0 obj << /S /D /St 58 >> endobj -1409 0 obj +1406 0 obj << /S /D /St 59 >> endobj -1410 0 obj +1407 0 obj << /S /D /St 60 >> endobj -1411 0 obj +1408 0 obj << /S /D /St 61 >> endobj -1412 0 obj +1409 0 obj << /S /D /St 62 >> endobj -1413 0 obj +1410 0 obj << /S /D /St 63 >> endobj -1414 0 obj +1411 0 obj << /S /D /St 64 >> endobj -1415 0 obj +1412 0 obj << /S /D /St 65 >> endobj -1416 0 obj +1413 0 obj << /S /D /St 66 >> endobj -1417 0 obj +1414 0 obj << /S /D /St 67 >> endobj -1418 0 obj +1415 0 obj << /S /D /St 68 >> endobj -1419 0 obj +1416 0 obj << /S /D /St 69 >> endobj -1420 0 obj +1417 0 obj << /S /D /St 70 >> endobj -1421 0 obj +1418 0 obj << /S /D /St 71 >> endobj -1422 0 obj +1419 0 obj << /S /D /St 72 >> endobj -1423 0 obj +1420 0 obj << /S /D /St 73 >> endobj -1424 0 obj +1421 0 obj << /S /D /St 74 >> endobj -1425 0 obj +1422 0 obj << /S /D /St 75 >> endobj -1426 0 obj +1423 0 obj << /S /D /St 76 >> endobj -1427 0 obj +1424 0 obj << /S /D /St 77 >> endobj -1428 0 obj +1425 0 obj << /S /D /St 78 >> endobj -1429 0 obj +1426 0 obj << /S /D /St 79 >> endobj -1430 0 obj +1427 0 obj << /S /D /St 80 >> endobj -1431 0 obj +1428 0 obj << /S /D /St 81 >> endobj -1432 0 obj +1429 0 obj << /S /D /St 82 >> endobj -1433 0 obj +1430 0 obj << /S /D /St 83 >> endobj -1434 0 obj +1431 0 obj << /S /D /St 84 >> endobj -1435 0 obj +1432 0 obj << /S /D /St 85 >> endobj -1436 0 obj +1433 0 obj << /S /D /St 86 >> endobj -1437 0 obj +1434 0 obj << /S /D /St 87 >> endobj -1438 0 obj +1435 0 obj << /S /D /St 88 >> endobj -1439 0 obj +1436 0 obj << /S /D /St 89 >> endobj -1440 0 obj +1437 0 obj << /S /D /St 90 >> endobj -1441 0 obj +1438 0 obj << /S /D /St 91 >> endobj -1442 0 obj +1439 0 obj << /S /D /St 92 >> endobj -1443 0 obj +1440 0 obj << /S /D /St 93 >> endobj -1444 0 obj +1441 0 obj << /S /D /St 94 >> endobj -1445 0 obj +1442 0 obj << /S /D /St 95 >> endobj -1446 0 obj +1443 0 obj << /S /D /St 96 >> endobj -1447 0 obj +1444 0 obj << /S /D /St 97 >> endobj -1448 0 obj +1445 0 obj << /S /D /St 98 >> endobj -1449 0 obj +1446 0 obj << /S /D /St 99 >> endobj -1450 0 obj +1447 0 obj << /S /D /St 100 >> endobj -1451 0 obj +1448 0 obj << /S /D /St 101 >> endobj -1452 0 obj +1449 0 obj << /S /D /St 102 >> endobj -1453 0 obj +1450 0 obj << /S /D /St 103 >> endobj -1454 0 obj +1451 0 obj << /S /D /St 104 >> endobj -1455 0 obj +1452 0 obj << /S /D /St 105 >> endobj -1456 0 obj +1453 0 obj << /S /D /St 106 >> endobj -1457 0 obj +1454 0 obj << /S /D /St 107 >> endobj -1458 0 obj +1455 0 obj << /S /D /St 108 >> endobj -1459 0 obj +1456 0 obj << /S /D /St 109 >> endobj -1460 0 obj +1457 0 obj << /S /D /St 110 >> endobj -1461 0 obj +1458 0 obj << /S /D /St 111 >> endobj -1462 0 obj +1459 0 obj << /S /D /St 112 >> endobj -1463 0 obj +1460 0 obj << /S /D /St 113 >> endobj -1464 0 obj +1461 0 obj << /S /D /St 114 >> endobj -1465 0 obj +1462 0 obj << /S /D /St 115 >> endobj -1466 0 obj +1463 0 obj << /S /D /St 116 >> endobj -1467 0 obj +1464 0 obj << /S /D /St 117 >> endobj -1468 0 obj +1465 0 obj << /S /D /St 118 >> endobj -1469 0 obj +1466 0 obj << /S /D /St 119 >> endobj -1470 0 obj +1467 0 obj << /S /D /St 120 >> endobj -1471 0 obj +1468 0 obj << /S /D /St 121 >> endobj -1472 0 obj +1469 0 obj << /S /D /St 122 >> endobj -1473 0 obj +1470 0 obj << /S /D /St 123 >> endobj -1474 0 obj +1471 0 obj << /S /D /St 124 >> endobj -1475 0 obj +1472 0 obj << /S /D /St 125 >> endobj -1476 0 obj +1473 0 obj << /S /D /St 126 >> endobj -1477 0 obj +1474 0 obj << /S /D /St 127 >> endobj -1478 0 obj +1475 0 obj << /S /D /St 128 >> endobj -1479 0 obj +1476 0 obj << /S /D /St 129 >> endobj -1480 0 obj +1477 0 obj << /S /D /St 130 >> endobj -1481 0 obj +1478 0 obj << /S /D /St 131 >> endobj -1482 0 obj +1479 0 obj << /S /D /St 132 >> endobj -1483 0 obj +1480 0 obj << /S /D /St 133 >> endobj -1484 0 obj +1481 0 obj << /S /D /St 134 >> endobj -1485 0 obj +1482 0 obj << /S /D /St 135 >> endobj -1486 0 obj +1483 0 obj << /S /D /St 136 >> endobj -1487 0 obj +1484 0 obj << /S /D /St 137 >> endobj xref -0 1488 +0 1485 0000000000 65535 f 0000000073 00000 n 0000000177 00000 n @@ -55953,25 +55875,25 @@ xref 0000208329 00000 n 0000208500 00000 n 0000208671 00000 n -0000208934 00000 n -0000209105 00000 n -0000209276 00000 n -0000209447 00000 n -0000209618 00000 n -0000209789 00000 n -0000209960 00000 n -0000210131 00000 n -0000210302 00000 n -0000210473 00000 n -0000210644 00000 n -0000210815 00000 n -0000210986 00000 n -0000211157 00000 n -0000211328 00000 n -0000211499 00000 n -0000211670 00000 n -0000211841 00000 n -0000212012 00000 n +0000208842 00000 n +0000209113 00000 n +0000209284 00000 n +0000209455 00000 n +0000209626 00000 n +0000209797 00000 n +0000209968 00000 n +0000210139 00000 n +0000210310 00000 n +0000210481 00000 n +0000210652 00000 n +0000210823 00000 n +0000210994 00000 n +0000211165 00000 n +0000211336 00000 n +0000211507 00000 n +0000211678 00000 n +0000211849 00000 n +0000212020 00000 n 0000212382 00000 n 0000212553 00000 n 0000212724 00000 n @@ -55979,18 +55901,18 @@ xref 0000213066 00000 n 0000213237 00000 n 0000213408 00000 n -0000213679 00000 n -0000213850 00000 n -0000214021 00000 n -0000214192 00000 n -0000214363 00000 n -0000214618 00000 n -0000214789 00000 n -0000214960 00000 n -0000215131 00000 n -0000215302 00000 n -0000215473 00000 n -0000215644 00000 n +0000213579 00000 n +0000213858 00000 n +0000214029 00000 n +0000214200 00000 n +0000214371 00000 n +0000214542 00000 n +0000214797 00000 n +0000214968 00000 n +0000215139 00000 n +0000215310 00000 n +0000215481 00000 n +0000215652 00000 n 0000215915 00000 n 0000216086 00000 n 0000216317 00000 n @@ -55998,11 +55920,11 @@ xref 0000216659 00000 n 0000216898 00000 n 0000217069 00000 n -0000217300 00000 n -0000217471 00000 n -0000217702 00000 n -0000217873 00000 n -0000218044 00000 n +0000217240 00000 n +0000217479 00000 n +0000217650 00000 n +0000217881 00000 n +0000218052 00000 n 0000218283 00000 n 0000218454 00000 n 0000218685 00000 n @@ -56010,831 +55932,828 @@ xref 0000219153 00000 n 0000219324 00000 n 0000219555 00000 n -0000219766 00000 n -0000219937 00000 n -0000220108 00000 n -0000220279 00000 n -0000220450 00000 n -0000220621 00000 n -0000220792 00000 n -0000221063 00000 n -0000221234 00000 n -0000221405 00000 n -0000221644 00000 n -0000221815 00000 n -0000221986 00000 n -0000222225 00000 n -0000222396 00000 n -0000222584 00000 n -0000222755 00000 n -0000223002 00000 n -0000223173 00000 n -0000223344 00000 n -0000223583 00000 n -0000223754 00000 n -0000223925 00000 n -0000224096 00000 n -0000224310 00000 n -0000224527 00000 n -0000224744 00000 n -0000224962 00000 n -0000225241 00000 n -0000225449 00000 n -0000225657 00000 n -0000225865 00000 n -0000226070 00000 n -0000226241 00000 n -0000226412 00000 n -0000226583 00000 n -0000226754 00000 n -0000227041 00000 n -0000227212 00000 n -0000227443 00000 n -0000227654 00000 n -0000227865 00000 n -0000228052 00000 n -0000228223 00000 n -0000228394 00000 n -0000228641 00000 n -0000228848 00000 n -0000229095 00000 n -0000229350 00000 n -0000229619 00000 n -0000229888 00000 n -0000230059 00000 n -0000230230 00000 n -0000230509 00000 n -0000230680 00000 n -0000230851 00000 n -0000231090 00000 n -0000231261 00000 n -0000231492 00000 n -0000231663 00000 n -0000231834 00000 n -0000232005 00000 n -0000232176 00000 n -0000232347 00000 n -0000232610 00000 n -0000232781 00000 n -0000232952 00000 n -0000233191 00000 n -0000233402 00000 n -0000233613 00000 n -0000233784 00000 n -0000233955 00000 n -0000234126 00000 n -0000234373 00000 n -0000234544 00000 n -0000234715 00000 n -0000234886 00000 n -0000235057 00000 n -0000235312 00000 n -0000235483 00000 n -0000235654 00000 n -0000235825 00000 n -0000236072 00000 n -0000236283 00000 n -0000236454 00000 n -0000236685 00000 n -0000236896 00000 n -0000237067 00000 n -0000237298 00000 n -0000237509 00000 n -0000237680 00000 n -0000237911 00000 n -0000238122 00000 n -0000238293 00000 n -0000238524 00000 n -0000238735 00000 n -0000238906 00000 n -0000239137 00000 n -0000239348 00000 n -0000239559 00000 n -0000239770 00000 n -0000239941 00000 n -0000240172 00000 n -0000240383 00000 n -0000240594 00000 n -0000240805 00000 n -0000240976 00000 n -0000241207 00000 n -0000241418 00000 n -0000241589 00000 n -0000241760 00000 n -0000241999 00000 n -0000242170 00000 n -0000242341 00000 n -0000242512 00000 n -0000242683 00000 n -0000242854 00000 n -0000243025 00000 n -0000243196 00000 n -0000243475 00000 n -0000243646 00000 n -0000243817 00000 n -0000243988 00000 n -0000244159 00000 n -0000244330 00000 n -0000244501 00000 n -0000244772 00000 n -0000244943 00000 n -0000245114 00000 n -0000245285 00000 n -0000245532 00000 n -0000245743 00000 n -0000245954 00000 n -0000246165 00000 n -0000246376 00000 n -0000246587 00000 n -0000246798 00000 n -0000247039 00000 n -0000247230 00000 n -0000247423 00000 n -0000247694 00000 n -0000247894 00000 n -0000248064 00000 n -0000248335 00000 n -0000248505 00000 n -0000248697 00000 n -0000248943 00000 n -0000249199 00000 n -0000249423 00000 n -0000249642 00000 n -0000249913 00000 n -0000250160 00000 n -0000250453 00000 n -0000250790 00000 n -0000251127 00000 n -0000251464 00000 n -0000251727 00000 n -0000251928 00000 n -0000252167 00000 n -0000252395 00000 n -0000252642 00000 n -0000252872 00000 n -0000253113 00000 n -0000253346 00000 n -0000253593 00000 n -0000253825 00000 n -0000254056 00000 n -0000254294 00000 n -0000254541 00000 n -0000254780 00000 n -0000255024 00000 n -0000255241 00000 n -0000255488 00000 n -0000255723 00000 n -0000255930 00000 n -0000256118 00000 n -0000256365 00000 n -0000256603 00000 n -0000256821 00000 n -0000257039 00000 n -0000257376 00000 n -0000257713 00000 n -0000257935 00000 n -0000258157 00000 n -0000258355 00000 n -0000258642 00000 n -0000258853 00000 n -0000259031 00000 n -0000259303 00000 n -0000259575 00000 n -0000259818 00000 n -0000260073 00000 n -0000260378 00000 n -0000260683 00000 n -0000260991 00000 n -0000261299 00000 n -0000261607 00000 n -0000261870 00000 n -0000262092 00000 n -0000262314 00000 n -0000262553 00000 n -0000262813 00000 n -0000263063 00000 n -0000263302 00000 n -0000263513 00000 n -0000263705 00000 n -0000263936 00000 n -0000264147 00000 n -0000264358 00000 n -0000264569 00000 n -0000264780 00000 n -0000264951 00000 n -0000265030 00000 n -0000265261 00000 n -0000265432 00000 n -0000265603 00000 n -0000265842 00000 n -0000266013 00000 n -0000266184 00000 n -0000266355 00000 n -0000266602 00000 n -0000266773 00000 n -0000267004 00000 n -0000267175 00000 n -0000267402 00000 n -0000267641 00000 n -0000267812 00000 n -0000268043 00000 n -0000268242 00000 n -0000268473 00000 n -0000268644 00000 n -0000268815 00000 n -0000269054 00000 n -0000269225 00000 n -0000269456 00000 n -0000269667 00000 n -0000269876 00000 n -0000270107 00000 n -0000270346 00000 n -0000270577 00000 n -0000270689 00000 n -0000270948 00000 n -0000271027 00000 n -0000271166 00000 n -0000271329 00000 n -0000271452 00000 n -0000271566 00000 n -0000271693 00000 n -0000271867 00000 n -0000272034 00000 n -0000272168 00000 n -0000272296 00000 n -0000272455 00000 n -0000272584 00000 n -0000272769 00000 n -0000272888 00000 n -0000273002 00000 n -0000273181 00000 n -0000273300 00000 n -0000273428 00000 n -0000273561 00000 n -0000273740 00000 n -0000273874 00000 n -0000274010 00000 n -0000274141 00000 n -0000274276 00000 n -0000274394 00000 n -0000274608 00000 n -0000274732 00000 n -0000274863 00000 n -0000275042 00000 n -0000275166 00000 n -0000275283 00000 n -0000275457 00000 n -0000275619 00000 n -0000275741 00000 n -0000275886 00000 n -0000276026 00000 n -0000276152 00000 n -0000276319 00000 n -0000276432 00000 n -0000276567 00000 n -0000276678 00000 n -0000276856 00000 n -0000277028 00000 n -0000277149 00000 n -0000277329 00000 n -0000277494 00000 n -0000277654 00000 n -0000277808 00000 n -0000277974 00000 n -0000278110 00000 n -0000278293 00000 n -0000278459 00000 n -0000278577 00000 n -0000278700 00000 n -0000278824 00000 n -0000278953 00000 n -0000279076 00000 n -0000279199 00000 n -0000279322 00000 n -0000279449 00000 n -0000279572 00000 n -0000279695 00000 n -0000279823 00000 n -0000279946 00000 n -0000280071 00000 n -0000280194 00000 n -0000280321 00000 n -0000280444 00000 n -0000280571 00000 n -0000280700 00000 n -0000280829 00000 n -0000280952 00000 n -0000281075 00000 n -0000281198 00000 n -0000281322 00000 n -0000281445 00000 n -0000281568 00000 n -0000281695 00000 n -0000281821 00000 n -0000281944 00000 n -0000282073 00000 n -0000282196 00000 n -0000282319 00000 n -0000282442 00000 n -0000282565 00000 n -0000282694 00000 n -0000282819 00000 n -0000282945 00000 n -0000283076 00000 n -0000283202 00000 n -0000283330 00000 n -0000283456 00000 n -0000283587 00000 n -0000283717 00000 n -0000283843 00000 n -0000283959 00000 n -0000284133 00000 n -0000284283 00000 n -0000284407 00000 n -0000284549 00000 n -0000284688 00000 n -0000284829 00000 n -0000284967 00000 n -0000285108 00000 n -0000285249 00000 n -0000285388 00000 n -0000285525 00000 n -0000285663 00000 n -0000285808 00000 n -0000285945 00000 n -0000286085 00000 n -0000286223 00000 n -0000286368 00000 n -0000286508 00000 n -0000286647 00000 n -0000286788 00000 n -0000286926 00000 n -0000287064 00000 n -0000287202 00000 n -0000287343 00000 n -0000287483 00000 n -0000287621 00000 n -0000287759 00000 n -0000287901 00000 n -0000288039 00000 n -0000288179 00000 n -0000288318 00000 n -0000288457 00000 n -0000288580 00000 n -0000288781 00000 n +0000219726 00000 n +0000219897 00000 n +0000220068 00000 n +0000220315 00000 n +0000220486 00000 n +0000220657 00000 n +0000220828 00000 n +0000220999 00000 n +0000221254 00000 n +0000221425 00000 n +0000221596 00000 n +0000221767 00000 n +0000222014 00000 n +0000222185 00000 n +0000222373 00000 n +0000222612 00000 n +0000222783 00000 n +0000222954 00000 n +0000223193 00000 n +0000223364 00000 n +0000223535 00000 n +0000223706 00000 n +0000223877 00000 n +0000224132 00000 n +0000224346 00000 n +0000224563 00000 n +0000224780 00000 n +0000224998 00000 n +0000225206 00000 n +0000225414 00000 n +0000225622 00000 n +0000225827 00000 n +0000225998 00000 n +0000226169 00000 n +0000226340 00000 n +0000226511 00000 n +0000226833 00000 n +0000227004 00000 n +0000227235 00000 n +0000227446 00000 n +0000227657 00000 n +0000227844 00000 n +0000228015 00000 n +0000228186 00000 n +0000228433 00000 n +0000228640 00000 n +0000228887 00000 n +0000229142 00000 n +0000229411 00000 n +0000229680 00000 n +0000229851 00000 n +0000230022 00000 n +0000230301 00000 n +0000230472 00000 n +0000230643 00000 n +0000230882 00000 n +0000231053 00000 n +0000231284 00000 n +0000231455 00000 n +0000231626 00000 n +0000231797 00000 n +0000231968 00000 n +0000232139 00000 n +0000232310 00000 n +0000232581 00000 n +0000232752 00000 n +0000232983 00000 n +0000233194 00000 n +0000233405 00000 n +0000233576 00000 n +0000233747 00000 n +0000233918 00000 n +0000234165 00000 n +0000234336 00000 n +0000234507 00000 n +0000234678 00000 n +0000234849 00000 n +0000235104 00000 n +0000235275 00000 n +0000235446 00000 n +0000235617 00000 n +0000235864 00000 n +0000236075 00000 n +0000236246 00000 n +0000236477 00000 n +0000236688 00000 n +0000236859 00000 n +0000237090 00000 n +0000237301 00000 n +0000237472 00000 n +0000237703 00000 n +0000237874 00000 n +0000238105 00000 n +0000238316 00000 n +0000238527 00000 n +0000238698 00000 n +0000238929 00000 n +0000239140 00000 n +0000239351 00000 n +0000239562 00000 n +0000239733 00000 n +0000239964 00000 n +0000240175 00000 n +0000240386 00000 n +0000240597 00000 n +0000240808 00000 n +0000241019 00000 n +0000241190 00000 n +0000241421 00000 n +0000241592 00000 n +0000241763 00000 n +0000241934 00000 n +0000242105 00000 n +0000242276 00000 n +0000242447 00000 n +0000242618 00000 n +0000242789 00000 n +0000243076 00000 n +0000243247 00000 n +0000243418 00000 n +0000243589 00000 n +0000243760 00000 n +0000243931 00000 n +0000244102 00000 n +0000244273 00000 n +0000244552 00000 n +0000244763 00000 n +0000244974 00000 n +0000245185 00000 n +0000245396 00000 n +0000245607 00000 n +0000245818 00000 n +0000246059 00000 n +0000246250 00000 n +0000246443 00000 n +0000246714 00000 n +0000246914 00000 n +0000247177 00000 n +0000247347 00000 n +0000247517 00000 n +0000247756 00000 n +0000247948 00000 n +0000248194 00000 n +0000248450 00000 n +0000248674 00000 n +0000248893 00000 n +0000249156 00000 n +0000249403 00000 n +0000249696 00000 n +0000250033 00000 n +0000250370 00000 n +0000250707 00000 n +0000250908 00000 n +0000251179 00000 n +0000251418 00000 n +0000251646 00000 n +0000251885 00000 n +0000252115 00000 n +0000252356 00000 n +0000252589 00000 n +0000252821 00000 n +0000253052 00000 n +0000253315 00000 n +0000253553 00000 n +0000253792 00000 n +0000254036 00000 n +0000254283 00000 n +0000254500 00000 n +0000254731 00000 n +0000254966 00000 n +0000255173 00000 n +0000255361 00000 n +0000255608 00000 n +0000255846 00000 n +0000256064 00000 n +0000256282 00000 n +0000256619 00000 n +0000256956 00000 n +0000257219 00000 n +0000257441 00000 n +0000257663 00000 n +0000257861 00000 n +0000258108 00000 n +0000258286 00000 n +0000258558 00000 n +0000258830 00000 n +0000259077 00000 n +0000259320 00000 n +0000259551 00000 n +0000259856 00000 n +0000260161 00000 n +0000260469 00000 n +0000260777 00000 n +0000261085 00000 n +0000261307 00000 n +0000261529 00000 n +0000261808 00000 n +0000262068 00000 n +0000262299 00000 n +0000262549 00000 n +0000262780 00000 n +0000262972 00000 n +0000263203 00000 n +0000263414 00000 n +0000263625 00000 n +0000263836 00000 n +0000264047 00000 n +0000264218 00000 n +0000264449 00000 n +0000264528 00000 n +0000264699 00000 n +0000264930 00000 n +0000265101 00000 n +0000265272 00000 n +0000265443 00000 n +0000265690 00000 n +0000265861 00000 n +0000266092 00000 n +0000266263 00000 n +0000266434 00000 n +0000266673 00000 n +0000266900 00000 n +0000267071 00000 n +0000267310 00000 n +0000267509 00000 n +0000267740 00000 n +0000267911 00000 n +0000268082 00000 n +0000268321 00000 n +0000268492 00000 n +0000268723 00000 n +0000268934 00000 n +0000269145 00000 n +0000269354 00000 n +0000269585 00000 n +0000269824 00000 n +0000270055 00000 n +0000270167 00000 n +0000270426 00000 n +0000270505 00000 n +0000270644 00000 n +0000270807 00000 n +0000270930 00000 n +0000271044 00000 n +0000271171 00000 n +0000271345 00000 n +0000271512 00000 n +0000271646 00000 n +0000271774 00000 n +0000271933 00000 n +0000272062 00000 n +0000272247 00000 n +0000272366 00000 n +0000272480 00000 n +0000272659 00000 n +0000272778 00000 n +0000272906 00000 n +0000273039 00000 n +0000273218 00000 n +0000273352 00000 n +0000273488 00000 n +0000273619 00000 n +0000273754 00000 n +0000273872 00000 n +0000274086 00000 n +0000274210 00000 n +0000274341 00000 n +0000274520 00000 n +0000274644 00000 n +0000274761 00000 n +0000274935 00000 n +0000275097 00000 n +0000275219 00000 n +0000275364 00000 n +0000275504 00000 n +0000275630 00000 n +0000275797 00000 n +0000275910 00000 n +0000276045 00000 n +0000276156 00000 n +0000276334 00000 n +0000276506 00000 n +0000276627 00000 n +0000276807 00000 n +0000276972 00000 n +0000277132 00000 n +0000277286 00000 n +0000277452 00000 n +0000277588 00000 n +0000277771 00000 n +0000277937 00000 n +0000278055 00000 n +0000278178 00000 n +0000278302 00000 n +0000278431 00000 n +0000278554 00000 n +0000278677 00000 n +0000278800 00000 n +0000278927 00000 n +0000279050 00000 n +0000279173 00000 n +0000279301 00000 n +0000279424 00000 n +0000279549 00000 n +0000279672 00000 n +0000279799 00000 n +0000279922 00000 n +0000280049 00000 n +0000280178 00000 n +0000280307 00000 n +0000280430 00000 n +0000280553 00000 n +0000280676 00000 n +0000280800 00000 n +0000280923 00000 n +0000281046 00000 n +0000281173 00000 n +0000281299 00000 n +0000281422 00000 n +0000281551 00000 n +0000281674 00000 n +0000281797 00000 n +0000281920 00000 n +0000282043 00000 n +0000282171 00000 n +0000282294 00000 n +0000282417 00000 n +0000282546 00000 n +0000282671 00000 n +0000282799 00000 n +0000282925 00000 n +0000283056 00000 n +0000283186 00000 n +0000283312 00000 n +0000283428 00000 n +0000283602 00000 n +0000283752 00000 n +0000283876 00000 n +0000284018 00000 n +0000284157 00000 n +0000284298 00000 n +0000284436 00000 n +0000284577 00000 n +0000284718 00000 n +0000284857 00000 n +0000284994 00000 n +0000285132 00000 n +0000285277 00000 n +0000285414 00000 n +0000285554 00000 n +0000285692 00000 n +0000285837 00000 n +0000285977 00000 n +0000286116 00000 n +0000286257 00000 n +0000286395 00000 n +0000286533 00000 n +0000286671 00000 n +0000286812 00000 n +0000286952 00000 n +0000287090 00000 n +0000287228 00000 n +0000287370 00000 n +0000287508 00000 n +0000287648 00000 n +0000287787 00000 n +0000287926 00000 n +0000288049 00000 n +0000288250 00000 n +0000288396 00000 n +0000288516 00000 n +0000288658 00000 n +0000288793 00000 n 0000288927 00000 n -0000289047 00000 n -0000289189 00000 n -0000289324 00000 n -0000289458 00000 n -0000289594 00000 n -0000289727 00000 n -0000289866 00000 n -0000290000 00000 n -0000290141 00000 n -0000290274 00000 n -0000290410 00000 n -0000290546 00000 n -0000290681 00000 n -0000290818 00000 n -0000290952 00000 n -0000291089 00000 n -0000291223 00000 n -0000291359 00000 n -0000291497 00000 n -0000291634 00000 n -0000291770 00000 n -0000291904 00000 n -0000292038 00000 n -0000292183 00000 n -0000292327 00000 n -0000292466 00000 n -0000292600 00000 n -0000292745 00000 n -0000292888 00000 n -0000293024 00000 n -0000293159 00000 n -0000293301 00000 n -0000293439 00000 n -0000293583 00000 n -0000293725 00000 n -0000293863 00000 n -0000293982 00000 n -0000294169 00000 n -0000294343 00000 n -0000294481 00000 n -0000294635 00000 n -0000294806 00000 n -0000294907 00000 n -0000295074 00000 n -0000295237 00000 n -0000295347 00000 n -0000295525 00000 n -0000295635 00000 n -0000295814 00000 n -0000295925 00000 n -0000296105 00000 n -0000296226 00000 n -0000296367 00000 n -0000296494 00000 n -0000296672 00000 n -0000296782 00000 n -0000296960 00000 n -0000297070 00000 n -0000297248 00000 n -0000297360 00000 n -0000297501 00000 n -0000297639 00000 n -0000297763 00000 n -0000297921 00000 n -0000298070 00000 n -0000298181 00000 n -0000298328 00000 n -0000298476 00000 n -0000298619 00000 n -0000298751 00000 n -0000298932 00000 n -0000299053 00000 n -0000299213 00000 n -0000299363 00000 n -0000299483 00000 n -0000299618 00000 n -0000299800 00000 n -0000299963 00000 n -0000300087 00000 n -0000300230 00000 n -0000300356 00000 n -0000300541 00000 n -0000300651 00000 n -0000300830 00000 n -0000300961 00000 n -0000301089 00000 n -0000301236 00000 n -0000301375 00000 n -0000301513 00000 n -0000301651 00000 n -0000301794 00000 n -0000301932 00000 n -0000302074 00000 n -0000302214 00000 n -0000302352 00000 n -0000302488 00000 n -0000302626 00000 n -0000302766 00000 n -0000302900 00000 n -0000303043 00000 n -0000303181 00000 n -0000303316 00000 n -0000303453 00000 n -0000303594 00000 n -0000303733 00000 n -0000303874 00000 n -0000304013 00000 n -0000304133 00000 n -0000304268 00000 n -0000304403 00000 n -0000304538 00000 n -0000304704 00000 n -0000304867 00000 n -0000304976 00000 n -0000305161 00000 n -0000305264 00000 n -0000305442 00000 n -0000305572 00000 n -0000305695 00000 n -0000305874 00000 n -0000306000 00000 n -0000306146 00000 n -0000306289 00000 n -0000306430 00000 n -0000306558 00000 n -0000306722 00000 n -0000306884 00000 n -0000307006 00000 n -0000307146 00000 n -0000307290 00000 n -0000307430 00000 n -0000307570 00000 n -0000307706 00000 n -0000307831 00000 n -0000308010 00000 n -0000308130 00000 n -0000308308 00000 n -0000308430 00000 n -0000308570 00000 n -0000308714 00000 n -0000308836 00000 n -0000308973 00000 n -0000309114 00000 n -0000309255 00000 n -0000309399 00000 n -0000309536 00000 n -0000309675 00000 n -0000309815 00000 n -0000309963 00000 n -0000310084 00000 n -0000310216 00000 n -0000311473 00000 n -0000312416 00000 n -0000321062 00000 n -0000330071 00000 n -0000338895 00000 n -0000347787 00000 n -0000356703 00000 n -0000365609 00000 n -0000367236 00000 n -0000371803 00000 n -0000377930 00000 n -0000385914 00000 n -0000396657 00000 n -0000402894 00000 n -0000409285 00000 n -0000415542 00000 n -0000422172 00000 n -0000428790 00000 n -0000432104 00000 n -0000437227 00000 n -0000445235 00000 n -0000451179 00000 n -0000458359 00000 n -0000462481 00000 n -0000468536 00000 n -0000474435 00000 n -0000479724 00000 n -0000484332 00000 n -0000490555 00000 n -0000495453 00000 n -0000501567 00000 n -0000507302 00000 n -0000512472 00000 n -0000518640 00000 n -0000524827 00000 n -0000530285 00000 n -0000537065 00000 n -0000543092 00000 n -0000549982 00000 n -0000556501 00000 n -0000562879 00000 n -0000569475 00000 n -0000575863 00000 n -0000581296 00000 n -0000587668 00000 n -0000593505 00000 n -0000599589 00000 n -0000606052 00000 n -0000612183 00000 n -0000618034 00000 n -0000627573 00000 n -0000640796 00000 n -0000648147 00000 n -0000656643 00000 n -0000663015 00000 n -0000669254 00000 n -0000675816 00000 n -0000682602 00000 n -0000691303 00000 n -0000698769 00000 n -0000706351 00000 n -0000715437 00000 n -0000722390 00000 n -0000729611 00000 n -0000738638 00000 n -0000747444 00000 n -0000757264 00000 n -0000765583 00000 n -0000774472 00000 n -0000782511 00000 n -0000792797 00000 n -0000799413 00000 n -0000806065 00000 n -0000818035 00000 n -0000825597 00000 n -0000832587 00000 n -0000840369 00000 n -0000851849 00000 n -0000861323 00000 n -0000866926 00000 n -0000872258 00000 n -0000881447 00000 n -0000890305 00000 n -0000900427 00000 n -0000909265 00000 n -0000917182 00000 n -0000927116 00000 n -0000932443 00000 n -0000938262 00000 n -0000950232 00000 n -0000958145 00000 n -0000968112 00000 n -0000977728 00000 n -0000986997 00000 n -0000993678 00000 n -0001001290 00000 n -0001011558 00000 n -0001024138 00000 n -0001031511 00000 n -0001042782 00000 n -0001050428 00000 n -0001061187 00000 n -0001069615 00000 n -0001080651 00000 n -0001088569 00000 n -0001100475 00000 n -0001109705 00000 n -0001117179 00000 n -0001126807 00000 n -0001136575 00000 n -0001144593 00000 n -0001151389 00000 n -0001155580 00000 n -0001163317 00000 n -0001172018 00000 n -0001178661 00000 n -0001184985 00000 n -0001191465 00000 n -0001197412 00000 n -0001203288 00000 n -0001209214 00000 n -0001215427 00000 n -0001221811 00000 n -0001228255 00000 n -0001234479 00000 n -0001239017 00000 n -0001248022 00000 n -0001257246 00000 n -0001268328 00000 n -0001275444 00000 n -0001282937 00000 n -0001290303 00000 n -0001298676 00000 n -0001305690 00000 n -0001314883 00000 n -0001322056 00000 n -0001329300 00000 n -0001336972 00000 n -0001343421 00000 n -0001351045 00000 n -0001359937 00000 n -0001368423 00000 n -0001377471 00000 n -0001384964 00000 n -0001394618 00000 n -0001406326 00000 n -0001408219 00000 n -0001408255 00000 n -0001408291 00000 n -0001408327 00000 n -0001408363 00000 n -0001408399 00000 n -0001408435 00000 n -0001408471 00000 n -0001408507 00000 n -0001408543 00000 n -0001408579 00000 n -0001408615 00000 n -0001408651 00000 n -0001408687 00000 n -0001408723 00000 n -0001408759 00000 n -0001408795 00000 n -0001408831 00000 n -0001408868 00000 n -0001408905 00000 n -0001408942 00000 n -0001408979 00000 n -0001409016 00000 n -0001409053 00000 n -0001409090 00000 n -0001409127 00000 n -0001409164 00000 n -0001409201 00000 n -0001409238 00000 n -0001409275 00000 n -0001409312 00000 n -0001409349 00000 n -0001409386 00000 n -0001409423 00000 n -0001409460 00000 n -0001409497 00000 n -0001409534 00000 n -0001409571 00000 n -0001409608 00000 n -0001409645 00000 n -0001409682 00000 n -0001409719 00000 n -0001409756 00000 n -0001409793 00000 n -0001409830 00000 n -0001409867 00000 n -0001409904 00000 n -0001409941 00000 n -0001409978 00000 n -0001410015 00000 n -0001410052 00000 n -0001410089 00000 n -0001410126 00000 n -0001410163 00000 n -0001410200 00000 n -0001410237 00000 n -0001410274 00000 n -0001410311 00000 n -0001410348 00000 n -0001410385 00000 n -0001410422 00000 n -0001410459 00000 n -0001410496 00000 n -0001410533 00000 n -0001410570 00000 n -0001410607 00000 n -0001410644 00000 n -0001410681 00000 n -0001410718 00000 n -0001410755 00000 n -0001410792 00000 n -0001410829 00000 n -0001410866 00000 n -0001410903 00000 n -0001410940 00000 n -0001410977 00000 n -0001411014 00000 n -0001411051 00000 n -0001411088 00000 n -0001411125 00000 n -0001411162 00000 n -0001411199 00000 n -0001411236 00000 n -0001411273 00000 n -0001411310 00000 n -0001411347 00000 n -0001411384 00000 n -0001411421 00000 n -0001411458 00000 n -0001411495 00000 n -0001411532 00000 n -0001411569 00000 n -0001411606 00000 n -0001411643 00000 n -0001411680 00000 n -0001411717 00000 n -0001411754 00000 n -0001411791 00000 n -0001411828 00000 n -0001411865 00000 n -0001411902 00000 n -0001411939 00000 n -0001411976 00000 n -0001412013 00000 n -0001412050 00000 n -0001412087 00000 n -0001412124 00000 n -0001412161 00000 n -0001412199 00000 n -0001412237 00000 n -0001412275 00000 n -0001412313 00000 n -0001412351 00000 n -0001412389 00000 n -0001412427 00000 n -0001412465 00000 n -0001412503 00000 n -0001412541 00000 n -0001412579 00000 n -0001412617 00000 n -0001412655 00000 n -0001412693 00000 n -0001412731 00000 n -0001412769 00000 n -0001412807 00000 n -0001412845 00000 n -0001412883 00000 n -0001412921 00000 n -0001412959 00000 n -0001412997 00000 n -0001413035 00000 n -0001413073 00000 n -0001413111 00000 n -0001413149 00000 n -0001413187 00000 n -0001413225 00000 n -0001413263 00000 n -0001413301 00000 n -0001413339 00000 n -0001413377 00000 n -0001413415 00000 n -0001413453 00000 n -0001413491 00000 n -0001413529 00000 n -0001413567 00000 n +0000289063 00000 n +0000289196 00000 n +0000289335 00000 n +0000289469 00000 n +0000289610 00000 n +0000289743 00000 n +0000289879 00000 n +0000290015 00000 n +0000290150 00000 n +0000290287 00000 n +0000290421 00000 n +0000290558 00000 n +0000290692 00000 n +0000290828 00000 n +0000290966 00000 n +0000291103 00000 n +0000291239 00000 n +0000291373 00000 n +0000291507 00000 n +0000291652 00000 n +0000291796 00000 n +0000291935 00000 n +0000292069 00000 n +0000292214 00000 n +0000292357 00000 n +0000292493 00000 n +0000292628 00000 n +0000292770 00000 n +0000292908 00000 n +0000293052 00000 n +0000293194 00000 n +0000293332 00000 n +0000293451 00000 n +0000293638 00000 n +0000293812 00000 n +0000293950 00000 n +0000294104 00000 n +0000294275 00000 n +0000294376 00000 n +0000294543 00000 n +0000294706 00000 n +0000294816 00000 n +0000294994 00000 n +0000295104 00000 n +0000295283 00000 n +0000295394 00000 n +0000295574 00000 n +0000295695 00000 n +0000295836 00000 n +0000295963 00000 n +0000296141 00000 n +0000296251 00000 n +0000296429 00000 n +0000296539 00000 n +0000296717 00000 n +0000296829 00000 n +0000296970 00000 n +0000297108 00000 n +0000297232 00000 n +0000297390 00000 n +0000297539 00000 n +0000297650 00000 n +0000297797 00000 n +0000297945 00000 n +0000298088 00000 n +0000298220 00000 n +0000298401 00000 n +0000298522 00000 n +0000298682 00000 n +0000298832 00000 n +0000298952 00000 n +0000299087 00000 n +0000299269 00000 n +0000299432 00000 n +0000299556 00000 n +0000299699 00000 n +0000299825 00000 n +0000300010 00000 n +0000300120 00000 n +0000300299 00000 n +0000300430 00000 n +0000300558 00000 n +0000300705 00000 n +0000300844 00000 n +0000300982 00000 n +0000301120 00000 n +0000301263 00000 n +0000301401 00000 n +0000301543 00000 n +0000301683 00000 n +0000301821 00000 n +0000301957 00000 n +0000302095 00000 n +0000302235 00000 n +0000302369 00000 n +0000302512 00000 n +0000302650 00000 n +0000302785 00000 n +0000302922 00000 n +0000303063 00000 n +0000303202 00000 n +0000303343 00000 n +0000303482 00000 n +0000303602 00000 n +0000303737 00000 n +0000303872 00000 n +0000304007 00000 n +0000304173 00000 n +0000304336 00000 n +0000304445 00000 n +0000304630 00000 n +0000304733 00000 n +0000304911 00000 n +0000305041 00000 n +0000305164 00000 n +0000305343 00000 n +0000305469 00000 n +0000305615 00000 n +0000305758 00000 n +0000305899 00000 n +0000306027 00000 n +0000306191 00000 n +0000306353 00000 n +0000306475 00000 n +0000306615 00000 n +0000306759 00000 n +0000306899 00000 n +0000307039 00000 n +0000307175 00000 n +0000307300 00000 n +0000307479 00000 n +0000307599 00000 n +0000307777 00000 n +0000307899 00000 n +0000308039 00000 n +0000308183 00000 n +0000308305 00000 n +0000308442 00000 n +0000308583 00000 n +0000308724 00000 n +0000308868 00000 n +0000309005 00000 n +0000309144 00000 n +0000309284 00000 n +0000309432 00000 n +0000309553 00000 n +0000309685 00000 n +0000310942 00000 n +0000311887 00000 n +0000320533 00000 n +0000329542 00000 n +0000338366 00000 n +0000347258 00000 n +0000356174 00000 n +0000365080 00000 n +0000366707 00000 n +0000371274 00000 n +0000377401 00000 n +0000385385 00000 n +0000396128 00000 n +0000402365 00000 n +0000408756 00000 n +0000415013 00000 n +0000421643 00000 n +0000428261 00000 n +0000431575 00000 n +0000436698 00000 n +0000444706 00000 n +0000450650 00000 n +0000457830 00000 n +0000461952 00000 n +0000468007 00000 n +0000473906 00000 n +0000479195 00000 n +0000483803 00000 n +0000490026 00000 n +0000494924 00000 n +0000501038 00000 n +0000506773 00000 n +0000511943 00000 n +0000518111 00000 n +0000524298 00000 n +0000529756 00000 n +0000536536 00000 n +0000542563 00000 n +0000549453 00000 n +0000555972 00000 n +0000562350 00000 n +0000568946 00000 n +0000575334 00000 n +0000580767 00000 n +0000587139 00000 n +0000592976 00000 n +0000599060 00000 n +0000605523 00000 n +0000611654 00000 n +0000617505 00000 n +0000627471 00000 n +0000640356 00000 n +0000647625 00000 n +0000656121 00000 n +0000662308 00000 n +0000668472 00000 n +0000674909 00000 n +0000682156 00000 n +0000691152 00000 n +0000697966 00000 n +0000708249 00000 n +0000714044 00000 n +0000722354 00000 n +0000731090 00000 n +0000739855 00000 n +0000748375 00000 n +0000758434 00000 n +0000766628 00000 n +0000775651 00000 n +0000785720 00000 n +0000791860 00000 n +0000798930 00000 n +0000810900 00000 n +0000818562 00000 n +0000825538 00000 n +0000833363 00000 n +0000845308 00000 n +0000854307 00000 n +0000859873 00000 n +0000865174 00000 n +0000874444 00000 n +0000883299 00000 n +0000893358 00000 n +0000902283 00000 n +0000910332 00000 n +0000920531 00000 n +0000924845 00000 n +0000932257 00000 n +0000942948 00000 n +0000950840 00000 n +0000960433 00000 n +0000971769 00000 n +0000979093 00000 n +0000986599 00000 n +0000994654 00000 n +0001006177 00000 n +0001016567 00000 n +0001024225 00000 n +0001035514 00000 n +0001042432 00000 n +0001053928 00000 n +0001062594 00000 n +0001074135 00000 n +0001081552 00000 n +0001092975 00000 n +0001102054 00000 n +0001110261 00000 n +0001119828 00000 n +0001128810 00000 n +0001136447 00000 n +0001142402 00000 n +0001149042 00000 n +0001158547 00000 n +0001165712 00000 n +0001172729 00000 n +0001178890 00000 n +0001185112 00000 n +0001190914 00000 n +0001197059 00000 n +0001203324 00000 n +0001209745 00000 n +0001215566 00000 n +0001221946 00000 n +0001228165 00000 n +0001232982 00000 n +0001241210 00000 n +0001249165 00000 n +0001260050 00000 n +0001269478 00000 n +0001276801 00000 n +0001284363 00000 n +0001292735 00000 n +0001298923 00000 n +0001305986 00000 n +0001314866 00000 n +0001321655 00000 n +0001329720 00000 n +0001336956 00000 n +0001343715 00000 n +0001352928 00000 n +0001361595 00000 n +0001369107 00000 n +0001377582 00000 n +0001387926 00000 n +0001400808 00000 n +0001401629 00000 n +0001403522 00000 n +0001403558 00000 n +0001403594 00000 n +0001403630 00000 n +0001403666 00000 n +0001403702 00000 n +0001403738 00000 n +0001403774 00000 n +0001403810 00000 n +0001403846 00000 n +0001403882 00000 n +0001403918 00000 n +0001403954 00000 n +0001403990 00000 n +0001404026 00000 n +0001404062 00000 n +0001404098 00000 n +0001404134 00000 n +0001404171 00000 n +0001404208 00000 n +0001404245 00000 n +0001404282 00000 n +0001404319 00000 n +0001404356 00000 n +0001404393 00000 n +0001404430 00000 n +0001404467 00000 n +0001404504 00000 n +0001404541 00000 n +0001404578 00000 n +0001404615 00000 n +0001404652 00000 n +0001404689 00000 n +0001404726 00000 n +0001404763 00000 n +0001404800 00000 n +0001404837 00000 n +0001404874 00000 n +0001404911 00000 n +0001404948 00000 n +0001404985 00000 n +0001405022 00000 n +0001405059 00000 n +0001405096 00000 n +0001405133 00000 n +0001405170 00000 n +0001405207 00000 n +0001405244 00000 n +0001405281 00000 n +0001405318 00000 n +0001405355 00000 n +0001405392 00000 n +0001405429 00000 n +0001405466 00000 n +0001405503 00000 n +0001405540 00000 n +0001405577 00000 n +0001405614 00000 n +0001405651 00000 n +0001405688 00000 n +0001405725 00000 n +0001405762 00000 n +0001405799 00000 n +0001405836 00000 n +0001405873 00000 n +0001405910 00000 n +0001405947 00000 n +0001405984 00000 n +0001406021 00000 n +0001406058 00000 n +0001406095 00000 n +0001406132 00000 n +0001406169 00000 n +0001406206 00000 n +0001406243 00000 n +0001406280 00000 n +0001406317 00000 n +0001406354 00000 n +0001406391 00000 n +0001406428 00000 n +0001406465 00000 n +0001406502 00000 n +0001406539 00000 n +0001406576 00000 n +0001406613 00000 n +0001406650 00000 n +0001406687 00000 n +0001406724 00000 n +0001406761 00000 n +0001406798 00000 n +0001406835 00000 n +0001406872 00000 n +0001406909 00000 n +0001406946 00000 n +0001406983 00000 n +0001407020 00000 n +0001407057 00000 n +0001407094 00000 n +0001407131 00000 n +0001407168 00000 n +0001407205 00000 n +0001407242 00000 n +0001407279 00000 n +0001407316 00000 n +0001407353 00000 n +0001407390 00000 n +0001407427 00000 n +0001407464 00000 n +0001407502 00000 n +0001407540 00000 n +0001407578 00000 n +0001407616 00000 n +0001407654 00000 n +0001407692 00000 n +0001407730 00000 n +0001407768 00000 n +0001407806 00000 n +0001407844 00000 n +0001407882 00000 n +0001407920 00000 n +0001407958 00000 n +0001407996 00000 n +0001408034 00000 n +0001408072 00000 n +0001408110 00000 n +0001408148 00000 n +0001408186 00000 n +0001408224 00000 n +0001408262 00000 n +0001408300 00000 n +0001408338 00000 n +0001408376 00000 n +0001408414 00000 n +0001408452 00000 n +0001408490 00000 n +0001408528 00000 n +0001408566 00000 n +0001408604 00000 n +0001408642 00000 n +0001408680 00000 n +0001408718 00000 n +0001408756 00000 n +0001408794 00000 n +0001408832 00000 n +0001408870 00000 n trailer << /ID -[<6cb784011f3ed7682c8eede1b90fae31><6cb784011f3ed7682c8eede1b90fae31>] +[<52567b780ff80d0bf5412129692b4542><52567b780ff80d0bf5412129692b4542>] % ReportLab generated PDF document -- digest (http://www.reportlab.com) -/Info 913 0 R -/Root 912 0 R -/Size 1488 +/Info 910 0 R +/Root 909 0 R +/Size 1485 >> startxref -1413605 +1408908 %%EOF diff --git a/chipsec/VERSION b/chipsec/VERSION index 9dbb0c00..081af9a1 100644 --- a/chipsec/VERSION +++ b/chipsec/VERSION @@ -1 +1 @@ -1.7.0 \ No newline at end of file +1.7.1 \ No newline at end of file diff --git a/drivers/linux/dkms.conf b/drivers/linux/dkms.conf index 6162e415..f2acb200 100644 --- a/drivers/linux/dkms.conf +++ b/drivers/linux/dkms.conf @@ -4,6 +4,6 @@ BUILT_MODULE_NAME=chipsec BUILT_MODULE_LOCATION=. PACKAGE_NAME=chipsec DEST_MODULE_LOCATION="/extra" -PACKAGE_VERSION=1.7.0 +PACKAGE_VERSION=1.7.1 REMAKE_INITRD=no AUTOINSTALL=no