e6743e4ab5
fix: add missing __init__.py to subpackages excluded from wheel installs ( #2741 )
...
* fix: add missing __init__.py to all subpackages lacking one
---------
Co-authored-by: copilot-swe-agent[bot] <198982749+Copilot@users.noreply.github.com >
Co-authored-by: npmitche <40474174+npmitche@users.noreply.github.com >
2026-05-28 15:46:45 -07:00
c35e42a6c0
Extend xml validator script to check for invisible characters ( #2747 )
...
* Extend xml validator script to check for invisible characters
* Extend cfg_checker to walk subdirs
* Fix iommu IRTA register size
2026-05-26 15:15:26 -07:00
cf8f5c9c82
Rework spi_descriptor.py hal to use simple in-mem registers
2026-05-26 11:15:30 -07:00
27c874811b
Fix config errors found by cfg_checker.py
2026-05-26 10:30:06 -07:00
b805e2d30e
Update core_parser logic ( #2733 )
...
* Update core_parser logic
* Add unit tests and remove underscore from resolve_config_include_path function
---------
Signed-off-by: Dan Scott <dan.scott@intel.com >
Co-authored-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-04-30 17:27:04 -07:00
3ca2431d53
Add ARL-H to chipsec
2026-04-30 14:18:24 -07:00
b9dcda62af
Resolve config issues found by extract_registers.py
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-04-16 13:20:34 -07:00
65aeb72182
Add initial lnl config
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-03-31 09:48:57 -07:00
cb76995fd3
Fix bios_wp and update how the platform stores regs and controls
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-03-26 14:24:59 -07:00
4928b27345
Refactor platform>ip/bar classes
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-03-23 16:38:26 -07:00
cf80eaaa88
Add missing functions
...
Classes were missing functions which could be called through recursive
properties
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-03-23 16:38:26 -07:00
477dce4c15
Core parser handle mmio ranges corrections
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-03-23 16:38:26 -07:00
c484301356
Remove print statement
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-03-23 16:38:26 -07:00
88664faf04
Fix class issues
...
This fix uses deepcopy on register objects so that mutating fields do not corrupt
others.
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-03-23 16:38:26 -07:00
79f81bbb7e
fix for flake8 rules related to whitespace
...
This commit fixes whitespace errors from checkers W291,W292,W293,W391. They were found by running "flake8 ." from the root directory. These are errors defined by "pycodestyle", and have no functional impact to the source. This is simply fixing whitespace as defined by CHIPSEC's .flake8 configuration.
background:
https://www.flake8rules.com/rules/W291.html
https://www.flake8rules.com/rules/W292.html
https://www.flake8rules.com/rules/W293.html
https://www.flake8rules.com/rules/W391.html
tool versions: flake8 v7.3.0, python v3.13.11
Signed-off-by: William Leara <william.leara@dell.com >
2026-03-10 14:20:23 -07:00
df16873962
Fix function
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-13 10:48:18 -08:00
552a0e070f
Update configs and files for some external tests
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-13 10:48:18 -08:00
6d27c8b95f
enforce uppercase registernames
...
Fix instances where registers were able to be referenced as lowercase
causing errors
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-02-11 09:58:05 -08:00
5bb516e8e8
Add hst_block_db to enable smbus block_reads
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-06 14:26:17 -08:00
ecf4e5f627
Add functionality to filter devices by enabled status
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-06 14:26:17 -08:00
44370adacb
Add ARL configs
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-06 14:26:17 -08:00
f4091efe39
Add RPL/PCH7xx configs to chipsec 2
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-06 14:26:17 -08:00
bedad6f2ec
Move P2SBC MMIO range definition to TLCs for pch5xx and 6xx
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-06 14:26:17 -08:00
b61a1bf535
Fix reg.get_list_by_name to match entire string
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-01-30 14:13:20 -08:00
752082ced4
Minor cleanup
...
Fixed register definition in hostctl11gen.xml
Removed breakpoint() from platform.py
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-01-29 23:42:19 -08:00
b7df4e5efb
dev/chipsec2 bug fixes
...
These changes were necessary to run chipsec2 on platform
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:42:02 -08:00
9988bc0a6e
Update IOMMU to use DMAR parsing
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:31:48 -08:00
1b869ef10f
minor changes to spibar0.xml (descriptions and control)
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-01-29 11:59:53 -08:00
73d1ebc446
Fix HAL call casing in mmcfg
...
Signed-off-by: Dan Scott <dan.scott@intel.com >
2026-01-28 10:15:36 -08:00
1259e568de
Change all HAL objects in cs.hals to be lowercase
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-12-09 13:49:37 -08:00
ec92093eb8
Fix getting items from the platform tree where they don't match case
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-12-09 10:17:53 -08:00
e2e060d390
Update chipsec so XML names are not case sensitive
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-10-30 14:08:03 -07:00
da378b443a
Update field names to be all caps
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-30 14:48:43 -07:00
6a45198b32
Add 'has_all_fields' function to parent register class and store vid in pci device
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-30 13:45:25 -07:00
5f3c7e541d
Fix issue where the same control was added to CONTRLS dict multiple times
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-22 09:51:50 -07:00
932317c2c5
Update txt xml
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-02 15:45:38 -07:00
c50165a2a4
Add 'is_enabled' to regs and 'filter_enabled' to objlist
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-01 22:45:59 -07:00
d8ce89cab6
Update to make controls work as expected
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-08-28 11:59:33 -07:00
5998f80f08
Update control __str__ to print full name of reg
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-08-28 11:59:33 -07:00
b7e301c6d8
Add 'self.name' to validate errors
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
56c1a0e3f9
Resolve issues with unit tests
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
99f9b9c6f4
Update files
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
c039cb9b4a
Update parsers
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-07-23 15:09:44 -07:00
97aa48963c
Update ip objects
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-07-23 15:09:44 -07:00
da143f80da
Update Register objects
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-07-23 15:09:44 -07:00
513fa89384
dev/chipsec2 hal.cpu hal.spi registers.mm_msgbus fixes ( #2520 )
...
* dev/chipsec2 hal.cpu hal.spi registers.mm_msgbus fixes
Found the following updates needed when using the framework
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
* Fix test_cpu unit test
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
---------
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
Co-authored-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-09 09:18:08 -07:00
7a0afc76c3
Split the hal and util_cmds
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 11:35:52 +08:00
51065bc7a9
Fix locks functionality to work with register objects
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 07:54:21 +08:00
8e6d16c252
Update mmcfg write to use hals
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 07:10:18 +08:00
5ee89e8675
Split mmcfg into separate hal
...
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-05-28 00:06:20 +08:00
Copilot