6 Commits

Author	SHA1	Message	Date
Nathaniel Mitchell	847f02daa1	initial commit of cfg changes ... Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>	2024-12-03 12:50:34 -08:00
coudrant	7247978cfb	Initial submission of AMD common modules (#2343) ... * Initial submission of AMD common modules * Corrected Copyright and Email for AMD modules. Major fixes to spectre module. Timeout added to PSP. Added rom_armor. * Corrected Copyright and Email for AMD modules. Major fixes to spectre module. Timeout added to PSP. Added rom_armor. * Corrected Platform Configuration. Corrected cpu_info for Intel. * Corrected register checks in spectre module * Comestic changes to strix.xml. Code quality improvements to psp and smm_addr. smm_base is redundant and removed * Corrected smm_addr use of SMMMASK. Added PATCH_LEVEL. Added psp to chipset. * Cleaned up results.id smm_addr.py * <sku code> now matches <configuration> in strix.xml	2024-10-30 13:49:20 -07:00
Nathaniel Mitchell	cfcac7fbb6	Fix address of UART_3 in Renoir ... Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>	2023-10-13 16:07:49 -07:00
Gabriel Kerneis	866f15f958	Drop use of register_high in AMD configuration file ... Also fix a few typo and whitespaces in AMD renoir.xml file. Bug: #1317 Signed-off-by: Gabriel Kerneis <gabriel.kerneis@ssi.gouv.fr>	2021-12-08 12:36:44 -08:00
Gabriel Kerneis	e0219412ca	Add mmio and io BAR descriptions for Renoir ... The missing descriptions cause `chipsec_util mmio list` to crash. Bug: #825 Signed-off-by: Gabriel Kerneis <gabriel.kerneis@ssi.gouv.fr>	2021-11-30 16:09:05 -08:00
Gabriel Kerneis	48f1e3b62c	AMD Renoir XML config ... Include an empty common.xml config as well, as a placeholder to move common registers in the future. Automatically generated from AMD public PPR documentation (with moderate amount of manual cleanup). Bug: #825 Signed-off-by: Gabriel Kerneis <gabriel.kerneis@ssi.gouv.fr>	2021-11-22 14:54:42 -08:00