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165 Commits

Author SHA1 Message Date
Nathaniel Mitchell c35e42a6c0 Extend xml validator script to check for invisible characters (#2747) 
* Extend xml validator script to check for invisible characters
* Extend cfg_checker to walk subdirs
* Fix iommu IRTA register size
 2026-05-26 15:15:26 -07:00
Nathaniel Mitchell 27c874811b Fix config errors found by cfg_checker.py 2026-05-26 10:30:06 -07:00
Nathaniel Mitchell 3ca2431d53 Add ARL-H to chipsec 2026-04-30 14:18:24 -07:00
Nathaniel Mitchell b9dcda62af Resolve config issues found by extract_registers.py 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-04-16 13:20:34 -07:00
Nathaniel Mitchell 65aeb72182 Add initial lnl config 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-03-31 09:48:57 -07:00
Nathaniel Mitchell 552a0e070f Update configs and files for some external tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-02-13 10:48:18 -08:00
Nathaniel Mitchell 5bb516e8e8 Add hst_block_db to enable smbus block_reads 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-02-06 14:26:17 -08:00
Nathaniel Mitchell 44370adacb Add ARL configs 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-02-06 14:26:17 -08:00
Nathaniel Mitchell f4091efe39 Add RPL/PCH7xx configs to chipsec 2 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-02-06 14:26:17 -08:00
Nathaniel Mitchell bedad6f2ec Move P2SBC MMIO range definition to TLCs for pch5xx and 6xx 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-02-06 14:26:17 -08:00
Nathaniel Mitchell 752082ced4 Minor cleanup 
Fixed register definition in hostctl11gen.xml
Removed breakpoint() from platform.py

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-01-29 23:42:19 -08:00
Nathaniel Mitchell 1b869ef10f minor changes to spibar0.xml (descriptions and control) 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-01-29 11:59:53 -08:00
Nathaniel Mitchell da378b443a Update field names to be all caps 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-09-30 14:48:43 -07:00
Nathaniel Mitchell 932317c2c5 Update txt xml 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-09-02 15:45:38 -07:00
Nathaniel Mitchell 14bda6657d Update iommu unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell 5aaf69f6d0 Get iommu working 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell e2139e954d Fixup framework with platform object 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell b8d11ca5d9 Initial commit for new Cfg.platform object and register structure 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-02 09:06:31 -07:00
Nathaniel Mitchell de6ffa0409 Update smbus hal, cmd and unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-17 09:07:19 -07:00
Nathaniel Mitchell 088a2ca69c Fixup spi HAL and additional unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-11 20:45:54 -07:00
Nathaniel Mitchell 4b65243d9c Fix more unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-10 09:06:35 -07:00
Nathaniel Mitchell 74818ec960 Fix up more modules. Adl now matching legacy run 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-07 21:08:24 -08:00
Nathaniel Mitchell 9d3e2842f0 fix iobar, and a few modules 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-05 07:59:36 -08:00
Nathaniel Mitchell d5345ad8c1 mmio update, unit tests, additional fixes 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-04 22:15:21 -08:00
Nathaniel Mitchell 4855f40a60 Move from size to limit for kbl and mtl tpm configs 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-04 22:15:21 -08:00
brentholtsclaw 642c9c6470 Update tpm for dev/chipsec2 
Move tpm12_commands and tpm_events to library
Change logic to remove bare except
Use hals functionality
Add read, write functions to normalize functionality

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-25 17:03:50 -08:00
Nathaniel Mitchell 7c65964361 Add pch_6xxP.xml and child cfgs 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-25 11:02:42 -08:00
Nathaniel Mitchell 6164ca86db Update to enable mmio 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-18 13:19:38 -08:00
Nathaniel Mitchell 4487649f76 initial commit of cfg changes 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-18 10:51:49 -08:00
Sara Batllori a9091b764b Add PCH C621A to pch_c260 config file 
Signed-off-by: Sara Batllori <sara.batllori@intel.com>
 2025-02-18 10:37:34 -08:00
Nathaniel Mitchell 600f203347 Add pch 700 series DIDs into pch 600s config 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-18 10:36:29 -08:00
Nathaniel Mitchell ec3b1c4196 Expands instances of pci registers per bus 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-12 14:25:03 -08:00
Nathaniel Mitchell bf5157435a Add adl.xml 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:38 -08:00
Nathaniel Mitchell 6aecea8c43 Post platformdetect updates 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:35 -08:00
Nathaniel Mitchell 847f02daa1 initial commit of cfg changes 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:34 -08:00
David Milosevic 68c7d1c57f 8086/meteorlake: fix issue #2276 
This patch resolves three exceptions on meteorlake. See issue #2276

Exception #1:
 Description: common.rtclock throws an exception when trying to read
 the RC register.
 Changes made to resolve this issue:
  - override the RC register inherited from 8086/common.xml
    so that we don't rely on RCBA anymore
  - define the SBREGBAR

Exception #2:
 Description: common.spd_wd throws an exception when trying
 to access the SMBUS_BASE. It also tried to read the SMBus HCFG from
 00:31.3 + 0x40 instead of 00:31.4 + 0x40.
 Changes made to resolve this issue:
  - define the SMBUS_BASE
  - extend the definition for the SMBus PCI configuration space

Exception #3:
 Description: common.bios_smi throws an exception when trying
 to access ABASE.
 Changes made to resolve this issue:
  - add PMC device definition at 00:31.2
  - add PWRMBASE and ABASE register definitions
  - add SMILock control

Signed-off-by: David Milosevic <David.Milosevic@9elements.com>
 2024-09-25 08:59:12 -07:00
Dan Scott b203f27ab4 Change MSR_SMM field to all caps 
Signed-off-by: Dan Scott <dan.scott@intel.com>
 2024-08-28 09:45:12 -07:00
Nicolò Boatto c646ee4550 Add Meteor Lake SPI support. 2024-07-29 16:39:06 -07:00
Dan Scott e1a25f65d6 Update req_pch field in mtl configuration 
Signed-off-by: Dan Scott <dan.scott@intel.com>
 2024-07-16 16:37:10 -07:00
Nathaniel Mitchell 016b3b50e4 Fix case of SMM_CODE_CHK_EN field 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-06-24 16:37:00 -07:00
Sae86 c57dd57612 Update GTTMMADR in mtl.xml 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-06-17 16:35:01 -07:00
Dan Scott a4d6e075e4 Add Meteor Lake Support 2024-05-29 10:50:59 -07:00
Dan Scott 1206ebffc1 Remove vcl field from LVSCC register in common.xml 2024-04-25 14:12:15 -07:00
Sae86 ff7acc620a Update MMCFG for Avoton to be consistent with other Atoms' 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-04-22 16:36:42 -07:00
BrentHoltsclaw 8d45174e17 Add CET module (#2033) 
* Add CET module

Reports CET settings if supported on the platform
```
[*] Running module: chipsec.modules.common.cet
[x][ =======================================================================
[x][ Module: Checking CET Settings
[x][ =======================================================================
CET Shadow Stack is supported
CET Indirect Branch Tracking is unsupported
IA32_U_CET Settings:
  SH_STK_EN: Enable shadow stacks at CPL3 is NOT ENABLED
  WR_SHSTK_EN: Enables the WRSSD/WRSSQ instructions is NOT ENABLED
  ENDBR_EN: Enable indirect branch tracking is NOT ENABLED
  LEG_IW_EN: Enable legacy compatibility treatment for indirect branch tracking is NOT ENABLED
  NO_TRACK_EN: Enables use of no track prefix for indirect branch tracking is NOT ENABLED
  SUPPRESS_DIS: Disables suppression of CET indirect branch tracking on legacy compatibility is NOT ENABLED
  SUPPRESS: Indirect branch tracking is suppressed is NOT ENABLED
IA32_S_CET Settings:
  SH_STK_EN: Enable shadow stacks at CPL3 is NOT ENABLED
  WR_SHSTK_EN: Enables the WRSSD/WRSSQ instructions is NOT ENABLED
  ENDBR_EN: Enable indirect branch tracking is NOT ENABLED
  LEG_IW_EN: Enable legacy compatibility treatment for indirect branch tracking is NOT ENABLED
  NO_TRACK_EN: Enables use of no track prefix for indirect branch tracking is NOT ENABLED
  SUPPRESS_DIS: Disables suppression of CET indirect branch tracking on legacy compatibility is NOT ENABLED
  SUPPRESS: Indirect branch tracking is suppressed is NOT ENABLED```

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2024-01-16 16:42:28 -08:00
Nathaniel Mitchell eea283a42f Update PCH 6xx* DIDs 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2023-09-18 16:38:04 -07:00
Nathaniel Mitchell 84424165c9 Refix glk detection value (#1735) 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2023-08-09 16:36:23 -07:00
Nathaniel Mitchell 8bde1bd648 Fix missing 0x in pch_5xxh config 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2023-08-02 16:33:15 -07:00
Dan Scott 395d713cca Update configs to match config parsing update 
Signed-off-by: Dan Scott <dan.scott@intel.com>
 2023-07-28 09:34:00 -07:00
Nicolas Iooss 54f7348d6a Intel TXT: add field definitions from project Slim Bootloader 
Project Slim Bootloader
(https://github.com/slimbootloader/slimbootloader) defines the content
of the ACM Policy Status at `0xFED30000+0x378` in
https://github.com/slimbootloader/slimbootloader/blob/c9d70e74dcfe5308ca1cf31279ee2a3e4b9bb7bb/Silicon/CommonSocPkg/Library/BootGuardLibCBnT/BootGuardTpmEventLogLib.c#L442-L470

    typedef union {
      struct {
        UINT64 KmId               : 4;      // 0-3   Key Manifest ID used for verified Key Manifest
        UINT64 MeasuredBoot       : 1;      // 4     perform measured boot
    ...
        UINT64 TpmStartupLocality : 1;      // 36    TPM startup locality.
        UINT64 Reserved           :27;      // 37-63
      } Bits;
      UINT64 Data;
    } ACM_BIOS_POLICY;

A previous version of this structure (before Pull Request
https://github.com/slimbootloader/slimbootloader/pull/1859 , commit
https://github.com/slimbootloader/slimbootloader/commit/ba9da25442b1d4fefd2675f7e21382a55b05684a)
also defined bits `KmArbEn` and `BpmArbEn`.

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
 2023-06-13 16:40:24 -07:00