19b3837432
Fix error handling in spihal and debugenabled/mmconfig modules
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-02-05 20:13:18 -08:00
d57670af35
Fix call to mmio hal caseing
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-01-31 10:40:49 -08:00
ad7e148041
Requested Fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:43:54 -08:00
e5f5668159
dev/chipsec2 Add basic acpi aml parser
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Add basic parser for dsdt and sdst tables to find memory regions. Still
recommend using acpi and iasl for full results.
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:43:54 -08:00
4eb3f91cc2
Requested changes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:42:02 -08:00
b7df4e5efb
dev/chipsec2 bug fixes
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These changes were necessary to run chipsec2 on platform
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:42:02 -08:00
6c19755952
Requested Fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:31:48 -08:00
9988bc0a6e
Update IOMMU to use DMAR parsing
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:31:48 -08:00
93c2a23d7c
Enable MMIO BAR Address cacheing (resolves unit test failure)
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Original commit for chipsec v1: 60ab31da9dnathaniel.p.mitchell@intel.com >
2026-01-29 11:59:38 -08:00
e6a67f3be0
remove unused imports from ec.py
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These imports are not used within this module.
Signed-off-by: William Leara <william.leara@dell.com >
2026-01-29 11:59:38 -08:00
98fc5c3b35
Minor module updates
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2026-01-29 11:59:24 -08:00
3dfc3c27b0
Minor bug fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-12-09 13:50:59 -08:00
1259e568de
Change all HAL objects in cs.hals to be lowercase
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-12-09 13:49:37 -08:00
e2e060d390
Update chipsec so XML names are not case sensitive
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-10-30 14:08:03 -07:00
874e550090
Undo intel/cpu changes.
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-02 10:20:38 -07:00
37829d0122
Clean up based on comments
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-02 10:20:38 -07:00
92cfae82fb
dev/chipsec2 fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-09-02 10:20:38 -07:00
c50165a2a4
Add 'is_enabled' to regs and 'filter_enabled' to objlist
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-01 22:45:59 -07:00
56c1a0e3f9
Resolve issues with unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
99f9b9c6f4
Update files
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
513fa89384
dev/chipsec2 hal.cpu hal.spi registers.mm_msgbus fixes ( #2520 )
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* dev/chipsec2 hal.cpu hal.spi registers.mm_msgbus fixes
Found the following updates needed when using the framework
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
* Fix test_cpu unit test
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
---------
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
Co-authored-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-09 09:18:08 -07:00
f0fa02312d
Refactor hide_p2sb and update docstring
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-06-05 11:58:33 +08:00
7a0afc76c3
Split the hal and util_cmds
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 11:35:52 +08:00
77bb71e895
Splitting msgbus and mm_msgbus
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 11:35:52 +08:00
51065bc7a9
Fix locks functionality to work with register objects
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 07:54:21 +08:00
8e6d16c252
Update mmcfg write to use hals
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 07:10:18 +08:00
5ee89e8675
Split mmcfg into separate hal
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-05-28 00:06:20 +08:00
f7f5f2c610
Add pci write function for hal
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-05-15 09:07:28 -07:00
e918c17494
Clean up debug and commented out code
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
14bda6657d
Update iommu unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
5aaf69f6d0
Get iommu working
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
e2139e954d
Fixup framework with platform object
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
7f669cfd2d
Add register specific functions to platform.py
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
b8d11ca5d9
Initial commit for new Cfg.platform object and register structure
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-02 09:06:31 -07:00
439c1a4d09
General update to chipsec2
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-04-18 12:00:31 -07:00
bea2860e8e
Update device functions and port register.read*/write* functions
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Updated the device.get_obj/objlist functions to match the other types e.g. "get_list_by_name" and "get_instance_by_name".
Updated register.read/read_field/write/write_field functions to first get the register objects, then read*/write* from there.
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-18 16:29:21 -07:00
de6ffa0409
Update smbus hal, cmd and unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-17 09:07:19 -07:00
f5c1fe5c62
Wrap spi_descriptor as a hal object, fix hal loading issue
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-12 09:07:23 -07:00
c8cfacd732
Move paging from hal to library
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-12 09:07:23 -07:00
088a2ca69c
Fixup spi HAL and additional unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-11 20:45:54 -07:00
947f67a6e1
Fix acpi tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-11 20:45:54 -07:00
4b65243d9c
Fix more unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-10 09:06:35 -07:00
74818ec960
Fix up more modules. Adl now matching legacy run
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-07 21:08:24 -08:00
9d3e2842f0
fix iobar, and a few modules
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
b59f5a5525
Fix second level mmio ranages
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
b9c9b0afac
Few fixes, mostly WRT mmio
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
443b019f32
Few fixes, mostly WRT mmio
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
f0fb769d70
Move acpi_tables to library from hal
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
7e1a53149e
Add fix to interrupts_cmd
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
29d1a2a364
Update to hals
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
Nathaniel Mitchell