ad7e148041
Requested Fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:43:54 -08:00
e5f5668159
dev/chipsec2 Add basic acpi aml parser
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Add basic parser for dsdt and sdst tables to find memory regions. Still
recommend using acpi and iasl for full results.
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:43:54 -08:00
6c19755952
Requested Fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:31:48 -08:00
9988bc0a6e
Update IOMMU to use DMAR parsing
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2026-01-29 13:31:48 -08:00
93c2a23d7c
Enable MMIO BAR Address cacheing (resolves unit test failure)
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Original commit for chipsec v1: 60ab31da9dnathaniel.p.mitchell@intel.com >
2026-01-29 11:59:38 -08:00
e6a67f3be0
remove unused imports from ec.py
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These imports are not used within this module.
Signed-off-by: William Leara <william.leara@dell.com >
2026-01-29 11:59:38 -08:00
3dfc3c27b0
Minor bug fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-12-09 13:50:59 -08:00
1259e568de
Change all HAL objects in cs.hals to be lowercase
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-12-09 13:49:37 -08:00
92cfae82fb
dev/chipsec2 fixes
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-09-02 10:20:38 -07:00
c50165a2a4
Add 'is_enabled' to regs and 'filter_enabled' to objlist
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-09-01 22:45:59 -07:00
99f9b9c6f4
Update files
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-07-23 15:09:44 -07:00
77bb71e895
Splitting msgbus and mm_msgbus
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 11:35:52 +08:00
51065bc7a9
Fix locks functionality to work with register objects
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-06-05 07:54:21 +08:00
5ee89e8675
Split mmcfg into separate hal
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-05-28 00:06:20 +08:00
f7f5f2c610
Add pci write function for hal
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-05-15 09:07:28 -07:00
e918c17494
Clean up debug and commented out code
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
14bda6657d
Update iommu unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
5aaf69f6d0
Get iommu working
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
7f669cfd2d
Add register specific functions to platform.py
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-08 01:07:54 +08:00
b8d11ca5d9
Initial commit for new Cfg.platform object and register structure
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-05-02 09:06:31 -07:00
439c1a4d09
General update to chipsec2
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-04-18 12:00:31 -07:00
bea2860e8e
Update device functions and port register.read*/write* functions
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Updated the device.get_obj/objlist functions to match the other types e.g. "get_list_by_name" and "get_instance_by_name".
Updated register.read/read_field/write/write_field functions to first get the register objects, then read*/write* from there.
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-18 16:29:21 -07:00
de6ffa0409
Update smbus hal, cmd and unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-17 09:07:19 -07:00
c8cfacd732
Move paging from hal to library
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-12 09:07:23 -07:00
088a2ca69c
Fixup spi HAL and additional unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-11 20:45:54 -07:00
947f67a6e1
Fix acpi tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-11 20:45:54 -07:00
4b65243d9c
Fix more unit tests
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-10 09:06:35 -07:00
9d3e2842f0
fix iobar, and a few modules
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
b59f5a5525
Fix second level mmio ranages
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
b9c9b0afac
Few fixes, mostly WRT mmio
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
443b019f32
Few fixes, mostly WRT mmio
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-05 07:59:36 -08:00
f0fb769d70
Move acpi_tables to library from hal
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
7e1a53149e
Add fix to interrupts_cmd
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
29d1a2a364
Update to hals
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-04 22:15:21 -08:00
51b088ffae
Normalize spi and spi descriptor
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SPI descriptor still needs changes but this should help get it working
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-03-04 22:15:04 -08:00
f9021e8ea8
dev/chipsec2 - spi_jedec_ids
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Moving to library
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-03-04 22:15:04 -08:00
b5a34ffd49
Update rtclock module
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-03-03 09:04:08 -08:00
4877f96d0e
Fixing comments
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-25 17:03:50 -08:00
642c9c6470
Update tpm for dev/chipsec2
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Move tpm12_commands and tpm_events to library
Change logic to remove bare except
Use hals functionality
Add read, write functions to normalize functionality
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-25 17:03:50 -08:00
655014a50f
Update igd hal
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-02-25 10:57:24 -08:00
1f5ab18ae0
Updating to satisfy comments
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-25 10:22:47 -08:00
07f123c96c
/dev/chipsec2 ucode hal update
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-25 10:22:47 -08:00
21e45ae281
dev/chipsec2 fix rebase issue
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hal/spi_uefi was moved to library/uefi/spi. It appears to have returned
due to a separate PR
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-20 12:31:34 -08:00
7725ebe841
Enable bios_wp module to run successfully on ADL
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-02-18 13:19:38 -08:00
6164ca86db
Update to enable mmio
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-02-18 13:19:38 -08:00
a032f04630
Update haldata and msr hal/cmd/tests
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Change haldata to use cpuid mfgstr
Update MSR hal/cmd/tests
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-02-18 12:53:25 -08:00
8a0b58e72d
HAL Update - Enable multitenant HALs
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2025-02-18 11:34:35 -08:00
ac1966ec85
Add hal/smbus.py unit tests
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2025-02-18 10:37:41 -08:00
0165a61fec
Dev/uefi hal ( #2377 )
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* Add Win Cert types to uefi_fv and spi_uefi
* Move uefi search to library.uefi folder
* Move uefi_fv to library.uefi
* Move uefi_compression to library.uefi>
* Move uefi_common to library.uefi
* Move uefi_platform to library.uefi
* Move spi_uefi to library.uefi
* Add library.uefi.sleep_scripts file
* Move S3 functionality into sleep_state file
* Add varstore and variable files to library.uefi
* Fixup Flake8 suggestions
* Rename library uefi files to remove uefi_
* This change changes the filename of any file under the library.uefi to remove the uefi as part of the name.
* Fix Errors when testing changes
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2025-02-12 09:13:50 -08:00
b53f1d86b0
Update portio HAL to import halbase and simplify api
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2024-12-16 14:40:15 -08:00
brentholtsclaw