admin/chipsec-chipsec
1
0
Fork 0
mirror of https://github.com/chipsec/chipsec synced 2026-06-08 13:31:00 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,548 Commits 16 Branches 107 Tags
npmitche/handlefwinfoerrors
Commit Graph

15 Commits

Author SHA1 Message Date
Nathaniel Mitchell 1259e568de Change all HAL objects in cs.hals to be lowercase 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-12-09 13:49:37 -08:00
Nathaniel Mitchell e2139e954d Fixup framework with platform object 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Sara Batllori d9a8265fc5 Remove MTAG prefix from module tags and add metadata tags 
Signed-off-by: Sara Batllori <sara.batllori@intel.com>
 2025-03-18 16:46:35 -07:00
Nathaniel Mitchell f7409804b4 HAL Update - Enable multitenant HALs 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:36 -08:00
Nathaniel Mitchell 6aecea8c43 Post platformdetect updates 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:35 -08:00
Nathaniel Mitchell 847f02daa1 initial commit of cfg changes 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2024-12-03 12:50:34 -08:00
Frinzell, Aaron da8ff136bf Clean up common modules 
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
 2024-08-26 16:39:27 -07:00
Sae86 efccddd739 WIP: Add feature to automatically generate url for return codes 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-05-29 10:44:04 -07:00
Sae86 2bc5b22216 Add feature to auto-generate/save return code IDs 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-04-22 16:36:02 -07:00
Sae86 47773a2559 Remove lines to set test result in is_supported 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-04-01 16:39:41 -07:00
Sae86 e52f0532b1 Add csv log option and fix value returned after running only one test 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-03-27 17:07:26 -07:00
Dan Scott 0e8192cfd0 Move files to library folder 2024-03-22 14:26:59 -07:00
Dan Scott a933b1337d Update references to functions in new library files 2024-03-22 14:26:59 -07:00
Sae86 cabe83d87f Return code updates to cet, reputation, s3script_modify and cpuid_fuzz 
Signed-off-by: Sae86 <sara.batllori@intel.com>
 2024-02-12 16:37:53 -08:00
BrentHoltsclaw 8d45174e17 Add CET module (#2033) 
* Add CET module

Reports CET settings if supported on the platform
```
[*] Running module: chipsec.modules.common.cet
[x][ =======================================================================
[x][ Module: Checking CET Settings
[x][ =======================================================================
CET Shadow Stack is supported
CET Indirect Branch Tracking is unsupported
IA32_U_CET Settings:
  SH_STK_EN: Enable shadow stacks at CPL3 is NOT ENABLED
  WR_SHSTK_EN: Enables the WRSSD/WRSSQ instructions is NOT ENABLED
  ENDBR_EN: Enable indirect branch tracking is NOT ENABLED
  LEG_IW_EN: Enable legacy compatibility treatment for indirect branch tracking is NOT ENABLED
  NO_TRACK_EN: Enables use of no track prefix for indirect branch tracking is NOT ENABLED
  SUPPRESS_DIS: Disables suppression of CET indirect branch tracking on legacy compatibility is NOT ENABLED
  SUPPRESS: Indirect branch tracking is suppressed is NOT ENABLED
IA32_S_CET Settings:
  SH_STK_EN: Enable shadow stacks at CPL3 is NOT ENABLED
  WR_SHSTK_EN: Enables the WRSSD/WRSSQ instructions is NOT ENABLED
  ENDBR_EN: Enable indirect branch tracking is NOT ENABLED
  LEG_IW_EN: Enable legacy compatibility treatment for indirect branch tracking is NOT ENABLED
  NO_TRACK_EN: Enables use of no track prefix for indirect branch tracking is NOT ENABLED
  SUPPRESS_DIS: Disables suppression of CET indirect branch tracking on legacy compatibility is NOT ENABLED
  SUPPRESS: Indirect branch tracking is suppressed is NOT ENABLED```

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2024-01-16 16:42:28 -08:00