2e38de930a
spaces
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:49 -05:00
6ac4044181
scan_image.py code cleanup
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:49 -05:00
dae71c282d
remove comment section
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:36 -05:00
02406ef032
spectre_v2.py code cleanup
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:36 -05:00
d495371d63
Update usage documentation to vbox_crash_acpibase.py
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:26 -05:00
1692fc71b0
s3script_modify.py code cleanup
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:15 -05:00
370f1aba0b
logic
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:06 -05:00
5e1882ac8a
Add usage documentation to cpu_info.py
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:02:06 -05:00
62b3d63d03
End spaces
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:00:20 -05:00
0ba38fbcb1
uefivar_fuzz.py minor code cleanup
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:00:20 -05:00
e06aa2745e
Lower case i
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:00:09 -05:00
ae8349363b
Add usage documentation to me_mfg_mode.py
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 17:00:09 -05:00
2be646a63d
Add usage documentation to spi_fdopss.py
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:59:58 -05:00
e66b1107f7
Add usage documentation to spi_lock.py
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:59:26 -05:00
07fdea7d05
update flag
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:52 -05:00
d63c16caae
Update SoC based configs
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:52 -05:00
10b7ed86dd
spaces
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:37 -05:00
243d4b38ec
use tri-state
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:37 -05:00
5d185f53b0
Test error
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:37 -05:00
6080321953
Don't check for PCH on SoC
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-04-25 16:58:37 -05:00
5b70d7dc4f
Updating to 1.8.3
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-30 18:22:15 -05:00
33b34673b9
Disable colorized output when piping the output or when NO_COLOR is set ( #1395 )
...
The former case is useful if the user runs some variant of:
chipsec_main.py > chipsec.log
The latter case is defined in https://no-color.org/ and simple enough to
implement while we are improving color handling.
Signed-off-by: Gabriel Kerneis <gabriel.kerneis@ssi.gouv.fr >
2022-03-29 17:36:55 -05:00
2a67e1a24c
Correct minor typo in sgx_check.py ( #1414 )
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:21:24 -07:00
e877ec9073
Fix list-modify-while-iterate bug in bios_wp.py ( #1413 )
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:18:08 -07:00
b90be4c48d
Cleanup and add docstring to pcie_fuzz.py ( #1411 )
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:16:55 -07:00
463b09eaac
Cleanup and add docstring to wsmt.py ( #1410 )
...
* Cleanup and add docstring to wsmt.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
* TypeError
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:13:09 -07:00
a7503a4fda
Clarify results and clean-up memlock.py ( #1409 )
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:06:39 -07:00
12a8c919f1
Add usage documentation to debugenabled.py ( #1408 )
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 14:06:00 -07:00
5476629a4c
Add follow on steps to uefivar_fuzz.py ( #1407 )
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-28 13:46:48 -07:00
9817c5e627
Add TGLH support ( #1404 )
2022-03-28 12:55:06 -07:00
8229a17ddd
Add usage documentation to bios_kbrd_buffer.py ( #1403 )
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-03-25 13:23:32 -05:00
de749c01de
Fix PMBASE definition in pch_c620
2022-03-21 11:03:57 -07:00
1d6a2668d5
Update to 1.8.2
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2022-03-01 13:44:21 -08:00
88d185e33f
Add a command to dump Intel TXT public registers
...
Provide a way to dump the content of all TXT registers.
Here is an example of output:
$ ./chipsec_util.py txt state
################################################################
## ##
## CHIPSEC: Platform Hardware Security Assessment Framework ##
## ##
################################################################
[CHIPSEC] Version : 1.8.1
[CHIPSEC] OS : Linux 5.16.5-arch1-1 #1 SMP PREEMPT Tue, 01 Feb 2022 21:42:50 +0000 x86_64
[CHIPSEC] Python : 3.10.2 (64-bit)
****** Chipsec Linux Kernel module is licensed under GPL 2.0
[CHIPSEC] API mode: using CHIPSEC kernel module API
[CHIPSEC] Helper : LinuxHelper (/mnt/data/to-be-backed-up/projects/chipsec/drivers/linux/chipsec.ko)
[CHIPSEC] Platform: Desktop 6th Generation Core Processor Quad Core (Skylake CPU / Sunrise Point PCH)
[CHIPSEC] VID: 8086
[CHIPSEC] DID: 191F
[CHIPSEC] RID: 07
[CHIPSEC] PCH : Intel H170 (100 series) PCH
[CHIPSEC] VID: 8086
[CHIPSEC] DID: A144
[CHIPSEC] RID: 31
[CHIPSEC] Executing command 'txt' with args ['state']
[CHIPSEC] CPUID.01H.ECX[Bit 6] = 1 << Safer Mode Extensions (SMX)
[CHIPSEC] CPUID.01H.ECX[Bit 5] = 1 << Virtual Machine Extensions (VMX)
[CHIPSEC] CR4.SMXE[Bit 14] = 0 << Safer Mode Extensions Enable
[CHIPSEC] CR4.VMXE[Bit 13] = 0 << Virtual Machine Extensions Enable
[CHIPSEC] IA32_FEATURE_CONTROL = 0x00000005 (Processor Feature Control)
[CHIPSEC] [00] LOCK = 1 << Lock
[CHIPSEC] [01] EN_VMX_INSIDE_SMX = 0 << Enable VMX inside SMX operation
[CHIPSEC] [02] EN_VMX_OUTSIDE_SMX = 1 << Enable VMX outside SMX operation
[CHIPSEC] [03] Reserved0 = 0 << Reserved
[CHIPSEC] [08] SENTER_LOCAL_EN = 0 << SENTER Local Functions Enable
[CHIPSEC] [15] SENTER_GLOBAL_EN = 0 << SENTER Global Enable
[CHIPSEC] [16] Reserved1 = 0 << Reserved
[CHIPSEC] [17] SGX_LAUNCH_CTRL_EN = 0 << SGX Launch Control Enable
[CHIPSEC] [18] SGX_GLOBAL_EN = 0 << SGX Global Enable
[CHIPSEC] [19] Reserved2 = 0 << Reserved
[CHIPSEC] [20] LMCE_ON = 0 << Turn Local Machine Check On
[CHIPSEC]
[CHIPSEC] TXT_DIDVID = 0x00000001B0068086 (TXT Device ID, at FED30110)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = B006 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] [48] EXTID = 0 << Extended ID
[CHIPSEC]
[CHIPSEC] TXT Public Key Hash: 2d67ddd75ef9339266a56f27189555ae77a2b0de774222e5de248dbeb8e33dd7
[CHIPSEC] Public Key Hash in MSR[0x20...0x23]: c14a4b4be9b8aa001b65377fe689d252e6c68dcd66d37bce1da9769867d10cfd
[CHIPSEC]
[CHIPSEC] TXT_STS = 0x0000000000000002 (TXT Status, at FED30000)
[CHIPSEC] [00] SENTER_DONE_STS = 0 << SENTER Done
[CHIPSEC] [01] SEXIT_DONE_STS = 1 << SEXIT Done
[CHIPSEC] [04] MEM_UNLOCK_STS = 0 << Memory Unlocked
[CHIPSEC] [06] MEM_CONFIG_LOCK_STS = 0 << Memory Configuration Locked
[CHIPSEC] [07] PRIVATE_OPEN_STS = 0 << Open-Private Command Performed
[CHIPSEC] [10] NTP_ENABLE_STS = 0 << NTP Enabled
[CHIPSEC] [11] MEM_CONFIG_OK_STS = 0 << Mem CFG OK
[CHIPSEC] [12] PMRC_LOCK_STS = 0 << PMRC Locked
[CHIPSEC] [13] SMM_OPEN_STS = 0 << SMM Opened
[CHIPSEC] [14] TXT_LOCALITY3_OPEN_STS = 0 << Locality 3 Opened
[CHIPSEC] [15] TXT_LOCALITY1_OPEN_STS = 0 << Locality 1 Opened
[CHIPSEC] [16] TXT_LOCALITY2_OPEN_STS = 0 << Locality 2 Opened
[CHIPSEC] TXT_ESTS = 0x0000000000000000 (TXT Error Status, at FED30008)
[CHIPSEC] [00] TXT_RESET_STS = 0 << TXT Reset
[CHIPSEC] [01] ROGUE_STS = 0 << Rogue Status
[CHIPSEC] [06] WAKE_ERROR_STS = 0 << Wake Error
[CHIPSEC] TXT_E2STS = 0x0000000000000004 (TXT Extended Error Status, at FED308F0)
[CHIPSEC] [01] SECRETS_STS = 0 << Secrets in Memory
[CHIPSEC] TXT_ERRORCODE = 0x0000000000000000 (TXT Error Code (0xC0000001 when successful SINIT), at FED30030)
[CHIPSEC] [00] TYPE2_MODULE_TYPE = 0 << Module Type (0 for BIOS ACM, 1 for SINIT)
[CHIPSEC] [04] TYPE2_CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] TYPE2_MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] SOFTWARE_SOURCE = 0 << Software Source (0 for ACM, 1 of MLE)
[CHIPSEC] [16] TYPE1_MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [28] TYPE1_RESERVED = 0 << Failure Condition Details
[CHIPSEC] [30] SOFTWARE = 0 << Error reported by Software (0 for Processor)
[CHIPSEC] [31] VALID = 0 << Valid Register Content
[CHIPSEC]
[CHIPSEC] TXT_SPAD = 0x0000000000000000 (Boot Status, at FED300A0)
[CHIPSEC] [00] ACM_INTERNAL = 0 << ACM Internal Use
[CHIPSEC] [30] TXT_STARTUP_SUCCESS = 0 << TXT Startup Success
[CHIPSEC] [31] BOOT_STATUS = 0 << General Startup ACM to BIOS status communication
[CHIPSEC] [47] MEM_POWER_DOWN_EXECUTED = 0 << Memory content was cleared via power down
[CHIPSEC] [48] BOOT_STATUS_DETAILS_48 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [53] TXT_POLICY_ENABLE = 0 << Startup ACM indication of run-time enabled status of TXT
[CHIPSEC] [54] BOOT_STATUS_DETAILS_54 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [59] BIOS_TRUSTED = 0 << BIOS is trusted
[CHIPSEC] [60] TXT_POLICY_DISABLE = 0 << TXT has been disabled by runtime FIT type 0xA record policy setting
[CHIPSEC] [61] BOOT_STATUS_DETAILS_61 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [62] CPU_ERROR = 0 << ACM authentication error
[CHIPSEC] [63] S_ACM_SUCCESS = 0 << S-ACM successfully enforced its logic for all provisioned technologies
[CHIPSEC] TXT_ACM_STATUS = 0x00000000 (TXT ACM Status, at FED30328)
[CHIPSEC] [00] MODULE_TYPE = 0 << Module Type
[CHIPSEC] [04] CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] ACM_STARTED = 0 << ACM Started
[CHIPSEC] [16] MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [31] VALID = 0 << Valid
[CHIPSEC] TXT_FIT = 0x00000000 (FIT (Firmware Interface Table), at FED30340)
[CHIPSEC] [00] FIT_FAILED = 0 << FIT Failed
[CHIPSEC] [01] S_ACM_FAILED = 0 << S-ACM Failed
[CHIPSEC] [02] FIT_MEASURED = 0 << FIT Measured
[CHIPSEC] [03] FIT_FALLBACK = 0 << FIT Fallback
[CHIPSEC] TXT_SCRATCHPAD = 0x0000000000000000 (ACM Policy Status, at FED30378)
[CHIPSEC] [13] TPM_TYPE = 0 << TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)
[CHIPSEC] [15] TPM_SUCCESS = 0 << TPM Success
[CHIPSEC] [17] BOOT_POLICIES_2 = 0 << Boot Policies
[CHIPSEC] [18] BACKUP_ACTION = 0 << Backup Action
[CHIPSEC] [20] TXT_PROFILE = 0 << TXT Profile
[CHIPSEC] [25] MEMORY_SCRUB_POLICY = 0 << Memory Scrub Policy
[CHIPSEC] [29] IBB_DMA_PROTECTION = 0 << IBB (Initial Boot Block) DMA Protection
[CHIPSEC] [32] S_CRTM_STATUS = 0 << Startup ACM S-CRTM establishment
[CHIPSEC] [35] CPU_COSIGNING_ENABLE = 0 << CPU co-signing enabled
[CHIPSEC] [36] TPM_STARTUP_LOCALITY = 0 << Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)
[CHIPSEC]
[CHIPSEC] TXT_SINIT_BASE = 0x00000000 (SINIT Base Address, at FED30270)
[CHIPSEC] TXT_SINIT_SIZE = 0x00000000 (SINIT Size, at FED30278)
[CHIPSEC] TXT_MLE_JOIN = 0x00000000 (MLE Join Base Address, at FED30290)
[CHIPSEC] TXT_HEAP_BASE = 0x00000000 (TXT Heap Base Address, at FED30300)
[CHIPSEC] TXT_HEAP_SIZE = 0x00000000 (TXT Heap Size, at FED30308)
[CHIPSEC] TXT_MSEG_BASE = 0x00000000 (TXT MSEG Base Address, at FED30310)
[CHIPSEC] TXT_MSEG_SIZE = 0x00000000 (TXT MSEG Size, at FED30318)
[CHIPSEC]
[CHIPSEC] TXT_DPR = 0x00000000 (TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR), at FED30330)
[CHIPSEC] [00] LOCK = 0 << Lock Bits 19:0
[CHIPSEC] [04] SIZE = 0 << Protected Memory Size (in MB)
[CHIPSEC] [20] TOP = 0 << Top Address+1 of DPR (base of TSEG)
[CHIPSEC] TXT_VER_FSBIF = 0xFFFFFFFF (TXT Front Side Bus Interface, at FED30100)
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_VER_QPIIF = 0x9D003000 (TXT Intel QuickPath Interconnect Interface, at FED30200)
[CHIPSEC] [19] PMRC_CAPABLE = 0 << PMRC Capable
[CHIPSEC] [26] DPR_CAPABLE = 1 << DPR Capable
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_PCH_DIDVID = 0x00000001A1448086 (TXT Platform Controller Hub Device ID, at FED30810)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = A144 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] INSMM = 0x00000000 (InSMM.STS, at FED30880)
[CHIPSEC] [00] STS = 0 << BIOS Write Enable when enabled by SPI.BC.EISS=1
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2022-02-28 15:49:48 -08:00
e4e88dd5dc
Intel TXT: add several registers in the fed30000 memory area
...
Several registers from an old version of TXT were documented in an
"Intel® Trusted Execution Technology (Intel®TXT) LAB Handout" from 2010:
https://docplayer.net/42821782-Intel-trusted-execution-technology-intel-txt-lab-handout.html
This includes MSEG definition, which was also documented in tboot:
https://github.com/tklengyel/tboot/blob/c9ca81f41b4a3eaa8e00c12a3d1d6d3c783782d4/tboot/include/txt/config_regs.h
#define TXTCR_MSEG_BASE 0x0310
#define TXTCR_MSEG_SIZE 0x0318
Moreover, add registers from Intel TXT Software Development Guide 315168-017
(updated in January 2021) from
http://www.intel.com/content/dam/www/public/us/en/documents/guides/intel-txt-software-development-guide.pdf
Add TXT_ACM_STATUS from 9elements/converged-security-suite repository
https://github.com/9elements/converged-security-suite/commit/b5037f9c93701d52fe4f3beb4b44a65854479609
and slimbootloader project
https://github.com/slimbootloader/slimbootloader/blob/35813687fb2a69a70727f82b7ed125fc2b22d35b/Platform/CometlakevBoardPkg/Library/Stage1BBoardInitLib/Stage1BBoardInitLib.c
and coreboot project
https://github.com/coreboot/coreboot/blob/28894c57988076688395c8a122d79640a3702d1a/src/security/intel/cbnt/cbnt.h
2022-02-28 15:49:48 -08:00
5651a0d3ac
Intel TXT: add InSMM.STS bit definition
...
Several sources of information documents the first bit of 0xFED30880 to
be "InSMM.STS":
- Some PCH datasheet from
https://www.intel.fr/content/www/fr/fr/products/docs/processors/core/core-technical-resources.html
document the bit 5 of register BIOS_SPI_BC as:
Enable InSMM.STS (EISS): When this bit is set, the BIOS region is
not writable until the CPU sets the InSMM.STS bit.
If this bit [5] is set, then WPD must be a '1' and
InSMM.STS(0xFED3_0880[0]) must be '1' also in order to write to
BIOS region of SPI Flash.
If this bit [5] is clear, then the InSMM.STS is a do not care.
This bit is locked by LE.
(chipsec already defines this bit in pch_c620.xml, and it is named
SMM_BWP in other pch_...xml files)
- Support for this bit was added in coreboot:
https://review.coreboot.org/c/coreboot/+/51796/14
- Support for this bit was added in the EDK II project:
https://github.com/tianocore/edk2-platforms/commit/17f047154203c73065dcdad8b6a2c59460bf2f53
Enable to easy access this bit by definining an INSMM register.
2022-02-28 15:49:48 -08:00
01906dc1bf
Intel TXT: fix ERRORCODE.VALID bit definition
2022-02-28 15:49:48 -08:00
62394b6c1c
helper/linux: va2pa - handle ioctl() errors
...
Handle translation errors in ioctl(IOCTL_VA2PA) gracefully to avoid
throwing an exception.
Signed-off-by: Mathias Krause <minipli@grsecurity.net >
2022-02-28 15:39:19 -08:00
edc4545c8f
hal: va2pa - handle translation errors gracefully
...
If the helper specific va2p() method fails, we shouldn't try to print
'pa' as it might be 'None'.
Swap the error handling with the 'VA -> PA' debug message to avoid
generating a format exception in this case.
Signed-off-by: Mathias Krause <minipli@grsecurity.net >
2022-02-28 15:39:19 -08:00
15294ef53f
Fix bug in is_all_ones when passing size as string from xml config
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2022-02-28 14:34:54 -08:00
101729a562
Update vid also
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-02-28 14:25:26 -08:00
6c3f10ab82
Better device parsing in multi-bus
...
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-02-28 14:25:26 -08:00
d27a5ddfce
Check control return values in bios_ts.py
2022-02-25 13:38:13 -08:00
672d57f595
Change inputs
2022-02-25 13:37:31 -08:00
91b7cab442
Add routine for control 0xff checks
2022-02-25 13:37:31 -08:00
c570001e9b
Multi-Bus updates
...
* Allow duplicate PCI device names to map to the same function.
* Update PCI device bus entries to point to a valid bus based on PCI
enumeration.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2022-02-25 13:36:49 -08:00
95f757ed20
Clairify uefivar_fuzz.py documentation
2022-02-24 17:05:05 -08:00
90fc2bec0c
Fixed exception if size attribute is missing
...
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2022-02-16 08:27:08 -08:00
7fb6448aec
Fix TPM 1.2 commands logging
...
When running `chipset_util.py tpm pcrread 0 8` to read a PCR (for
example) on a system using a TPM 1.2, the following result is displayed:
[CHIPSEC] Executing command 'tpm' with args ['command', 'pcrread', '0', '8']
----------------------------------------------------------------
TPM response header
----------------------------------------------------------------
Response TAG: 0xc4
Data Size : 0x1e
Return Code : 0x0
Success
62 79 74 65 61 72 72 61 79 28 62 27 5C 78 30 30 | bytearray(b'\x00
5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
5C 78 30 30 5C 78 30 30 5C 78 30 30 5C 78 30 30 | \x00\x00\x00\x00
5C 78 30 30 5C 78 30 30 5C 78 30 30 27 29 | \x00\x00\x00')
Instead of displaying a hexdump of a Python representation of a
bytearray, display the hexdump of the bytes.
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2022-02-16 08:24:47 -08:00
244cfa80dc
Mem update and log alignment
2022-02-16 08:23:32 -08:00
Frinzell, Aaron