88d185e33f
Add a command to dump Intel TXT public registers
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Provide a way to dump the content of all TXT registers.
Here is an example of output:
$ ./chipsec_util.py txt state
################################################################
## ##
## CHIPSEC: Platform Hardware Security Assessment Framework ##
## ##
################################################################
[CHIPSEC] Version : 1.8.1
[CHIPSEC] OS : Linux 5.16.5-arch1-1 #1 SMP PREEMPT Tue, 01 Feb 2022 21:42:50 +0000 x86_64
[CHIPSEC] Python : 3.10.2 (64-bit)
****** Chipsec Linux Kernel module is licensed under GPL 2.0
[CHIPSEC] API mode: using CHIPSEC kernel module API
[CHIPSEC] Helper : LinuxHelper (/mnt/data/to-be-backed-up/projects/chipsec/drivers/linux/chipsec.ko)
[CHIPSEC] Platform: Desktop 6th Generation Core Processor Quad Core (Skylake CPU / Sunrise Point PCH)
[CHIPSEC] VID: 8086
[CHIPSEC] DID: 191F
[CHIPSEC] RID: 07
[CHIPSEC] PCH : Intel H170 (100 series) PCH
[CHIPSEC] VID: 8086
[CHIPSEC] DID: A144
[CHIPSEC] RID: 31
[CHIPSEC] Executing command 'txt' with args ['state']
[CHIPSEC] CPUID.01H.ECX[Bit 6] = 1 << Safer Mode Extensions (SMX)
[CHIPSEC] CPUID.01H.ECX[Bit 5] = 1 << Virtual Machine Extensions (VMX)
[CHIPSEC] CR4.SMXE[Bit 14] = 0 << Safer Mode Extensions Enable
[CHIPSEC] CR4.VMXE[Bit 13] = 0 << Virtual Machine Extensions Enable
[CHIPSEC] IA32_FEATURE_CONTROL = 0x00000005 (Processor Feature Control)
[CHIPSEC] [00] LOCK = 1 << Lock
[CHIPSEC] [01] EN_VMX_INSIDE_SMX = 0 << Enable VMX inside SMX operation
[CHIPSEC] [02] EN_VMX_OUTSIDE_SMX = 1 << Enable VMX outside SMX operation
[CHIPSEC] [03] Reserved0 = 0 << Reserved
[CHIPSEC] [08] SENTER_LOCAL_EN = 0 << SENTER Local Functions Enable
[CHIPSEC] [15] SENTER_GLOBAL_EN = 0 << SENTER Global Enable
[CHIPSEC] [16] Reserved1 = 0 << Reserved
[CHIPSEC] [17] SGX_LAUNCH_CTRL_EN = 0 << SGX Launch Control Enable
[CHIPSEC] [18] SGX_GLOBAL_EN = 0 << SGX Global Enable
[CHIPSEC] [19] Reserved2 = 0 << Reserved
[CHIPSEC] [20] LMCE_ON = 0 << Turn Local Machine Check On
[CHIPSEC]
[CHIPSEC] TXT_DIDVID = 0x00000001B0068086 (TXT Device ID, at FED30110)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = B006 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] [48] EXTID = 0 << Extended ID
[CHIPSEC]
[CHIPSEC] TXT Public Key Hash: 2d67ddd75ef9339266a56f27189555ae77a2b0de774222e5de248dbeb8e33dd7
[CHIPSEC] Public Key Hash in MSR[0x20...0x23]: c14a4b4be9b8aa001b65377fe689d252e6c68dcd66d37bce1da9769867d10cfd
[CHIPSEC]
[CHIPSEC] TXT_STS = 0x0000000000000002 (TXT Status, at FED30000)
[CHIPSEC] [00] SENTER_DONE_STS = 0 << SENTER Done
[CHIPSEC] [01] SEXIT_DONE_STS = 1 << SEXIT Done
[CHIPSEC] [04] MEM_UNLOCK_STS = 0 << Memory Unlocked
[CHIPSEC] [06] MEM_CONFIG_LOCK_STS = 0 << Memory Configuration Locked
[CHIPSEC] [07] PRIVATE_OPEN_STS = 0 << Open-Private Command Performed
[CHIPSEC] [10] NTP_ENABLE_STS = 0 << NTP Enabled
[CHIPSEC] [11] MEM_CONFIG_OK_STS = 0 << Mem CFG OK
[CHIPSEC] [12] PMRC_LOCK_STS = 0 << PMRC Locked
[CHIPSEC] [13] SMM_OPEN_STS = 0 << SMM Opened
[CHIPSEC] [14] TXT_LOCALITY3_OPEN_STS = 0 << Locality 3 Opened
[CHIPSEC] [15] TXT_LOCALITY1_OPEN_STS = 0 << Locality 1 Opened
[CHIPSEC] [16] TXT_LOCALITY2_OPEN_STS = 0 << Locality 2 Opened
[CHIPSEC] TXT_ESTS = 0x0000000000000000 (TXT Error Status, at FED30008)
[CHIPSEC] [00] TXT_RESET_STS = 0 << TXT Reset
[CHIPSEC] [01] ROGUE_STS = 0 << Rogue Status
[CHIPSEC] [06] WAKE_ERROR_STS = 0 << Wake Error
[CHIPSEC] TXT_E2STS = 0x0000000000000004 (TXT Extended Error Status, at FED308F0)
[CHIPSEC] [01] SECRETS_STS = 0 << Secrets in Memory
[CHIPSEC] TXT_ERRORCODE = 0x0000000000000000 (TXT Error Code (0xC0000001 when successful SINIT), at FED30030)
[CHIPSEC] [00] TYPE2_MODULE_TYPE = 0 << Module Type (0 for BIOS ACM, 1 for SINIT)
[CHIPSEC] [04] TYPE2_CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] TYPE2_MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] SOFTWARE_SOURCE = 0 << Software Source (0 for ACM, 1 of MLE)
[CHIPSEC] [16] TYPE1_MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [28] TYPE1_RESERVED = 0 << Failure Condition Details
[CHIPSEC] [30] SOFTWARE = 0 << Error reported by Software (0 for Processor)
[CHIPSEC] [31] VALID = 0 << Valid Register Content
[CHIPSEC]
[CHIPSEC] TXT_SPAD = 0x0000000000000000 (Boot Status, at FED300A0)
[CHIPSEC] [00] ACM_INTERNAL = 0 << ACM Internal Use
[CHIPSEC] [30] TXT_STARTUP_SUCCESS = 0 << TXT Startup Success
[CHIPSEC] [31] BOOT_STATUS = 0 << General Startup ACM to BIOS status communication
[CHIPSEC] [47] MEM_POWER_DOWN_EXECUTED = 0 << Memory content was cleared via power down
[CHIPSEC] [48] BOOT_STATUS_DETAILS_48 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [53] TXT_POLICY_ENABLE = 0 << Startup ACM indication of run-time enabled status of TXT
[CHIPSEC] [54] BOOT_STATUS_DETAILS_54 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [59] BIOS_TRUSTED = 0 << BIOS is trusted
[CHIPSEC] [60] TXT_POLICY_DISABLE = 0 << TXT has been disabled by runtime FIT type 0xA record policy setting
[CHIPSEC] [61] BOOT_STATUS_DETAILS_61 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [62] CPU_ERROR = 0 << ACM authentication error
[CHIPSEC] [63] S_ACM_SUCCESS = 0 << S-ACM successfully enforced its logic for all provisioned technologies
[CHIPSEC] TXT_ACM_STATUS = 0x00000000 (TXT ACM Status, at FED30328)
[CHIPSEC] [00] MODULE_TYPE = 0 << Module Type
[CHIPSEC] [04] CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] ACM_STARTED = 0 << ACM Started
[CHIPSEC] [16] MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [31] VALID = 0 << Valid
[CHIPSEC] TXT_FIT = 0x00000000 (FIT (Firmware Interface Table), at FED30340)
[CHIPSEC] [00] FIT_FAILED = 0 << FIT Failed
[CHIPSEC] [01] S_ACM_FAILED = 0 << S-ACM Failed
[CHIPSEC] [02] FIT_MEASURED = 0 << FIT Measured
[CHIPSEC] [03] FIT_FALLBACK = 0 << FIT Fallback
[CHIPSEC] TXT_SCRATCHPAD = 0x0000000000000000 (ACM Policy Status, at FED30378)
[CHIPSEC] [13] TPM_TYPE = 0 << TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)
[CHIPSEC] [15] TPM_SUCCESS = 0 << TPM Success
[CHIPSEC] [17] BOOT_POLICIES_2 = 0 << Boot Policies
[CHIPSEC] [18] BACKUP_ACTION = 0 << Backup Action
[CHIPSEC] [20] TXT_PROFILE = 0 << TXT Profile
[CHIPSEC] [25] MEMORY_SCRUB_POLICY = 0 << Memory Scrub Policy
[CHIPSEC] [29] IBB_DMA_PROTECTION = 0 << IBB (Initial Boot Block) DMA Protection
[CHIPSEC] [32] S_CRTM_STATUS = 0 << Startup ACM S-CRTM establishment
[CHIPSEC] [35] CPU_COSIGNING_ENABLE = 0 << CPU co-signing enabled
[CHIPSEC] [36] TPM_STARTUP_LOCALITY = 0 << Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)
[CHIPSEC]
[CHIPSEC] TXT_SINIT_BASE = 0x00000000 (SINIT Base Address, at FED30270)
[CHIPSEC] TXT_SINIT_SIZE = 0x00000000 (SINIT Size, at FED30278)
[CHIPSEC] TXT_MLE_JOIN = 0x00000000 (MLE Join Base Address, at FED30290)
[CHIPSEC] TXT_HEAP_BASE = 0x00000000 (TXT Heap Base Address, at FED30300)
[CHIPSEC] TXT_HEAP_SIZE = 0x00000000 (TXT Heap Size, at FED30308)
[CHIPSEC] TXT_MSEG_BASE = 0x00000000 (TXT MSEG Base Address, at FED30310)
[CHIPSEC] TXT_MSEG_SIZE = 0x00000000 (TXT MSEG Size, at FED30318)
[CHIPSEC]
[CHIPSEC] TXT_DPR = 0x00000000 (TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR), at FED30330)
[CHIPSEC] [00] LOCK = 0 << Lock Bits 19:0
[CHIPSEC] [04] SIZE = 0 << Protected Memory Size (in MB)
[CHIPSEC] [20] TOP = 0 << Top Address+1 of DPR (base of TSEG)
[CHIPSEC] TXT_VER_FSBIF = 0xFFFFFFFF (TXT Front Side Bus Interface, at FED30100)
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_VER_QPIIF = 0x9D003000 (TXT Intel QuickPath Interconnect Interface, at FED30200)
[CHIPSEC] [19] PMRC_CAPABLE = 0 << PMRC Capable
[CHIPSEC] [26] DPR_CAPABLE = 1 << DPR Capable
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_PCH_DIDVID = 0x00000001A1448086 (TXT Platform Controller Hub Device ID, at FED30810)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = A144 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] INSMM = 0x00000000 (InSMM.STS, at FED30880)
[CHIPSEC] [00] STS = 0 << BIOS Write Enable when enabled by SPI.BC.EISS=1
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2022-02-28 15:49:48 -08:00
90fc2bec0c
Fixed exception if size attribute is missing
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2022-02-16 08:27:08 -08:00
89a388f463
Added ability to dump unnamed MMIO regions
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2021-12-08 09:15:37 -08:00
aac6f1e01d
Extended PCI dump functionality
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Updated PCI dump to allow for optional device and function parameters.
This allows limiting the dump to a specific bus or bus and device.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2021-12-02 16:15:04 -08:00
1998d9032e
Fix bugs within locks_cmd
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-10-26 15:05:12 -07:00
bd9cfe0b95
Move docstring from class
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Update usage in argparser
Update for more than one class
Signed-off-by: Sae86 <sara.batllori@intel.com >
2021-09-28 10:20:55 -07:00
f46024c0cf
Address Comments
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-09-28 10:18:20 -07:00
9cfbd852ca
Update CONSISTENCY_CHECKING
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-09-28 10:18:20 -07:00
591b863112
Create hal locks and lock_check_cmd
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-09-28 10:18:20 -07:00
293e3e1e36
Update copyright date
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-08-26 10:50:51 -07:00
0e53326a83
Create exceptions.py for chipsec exceptions
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-08-26 10:50:51 -07:00
c8c14e21be
Remove shebang from all but the entry points. Update ep to py3
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2021-08-12 08:27:33 -07:00
c536db734a
Fix utilcmd to work with multibus enhancements
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-07-29 12:37:26 -07:00
80ef67a0ca
fixing copyright years
2021-07-27 14:17:10 -07:00
abfc984b38
Move TPM register dumps to config file
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TPM register dumps are currently hardcoded into the TPM HAL. By moving
them to xml config files and implementing functionality to read the
xml files, we can add more flexibility for register dumping, especially
as we add support for TPM2.0 registers.
Signed-off-by: Kevin Sun <kevin.sun@intel.com >
2021-07-27 14:17:10 -07:00
e30b841454
Delete unused import.
2021-06-21 16:26:11 -07:00
b8ef7ddd8b
Prompt the user to specify only existing ACPI tables.
2021-06-21 16:26:11 -07:00
07b2c3aac0
desc_cmd.py: fix log message typos
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Now since the GDT and IDT dumps work again, one sees the log messages
contain a typo -- referring to "acpi" instead of "idt" / "gdt".
Fix that.
Signed-off-by: Mathias Krause <minipli@grsecurity.net >
2021-06-21 16:24:21 -07:00
b91b0dccb2
moving change from hal to utilcmd
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Signed-off-by: Kevin Sun <kevin.sun@intel.com >
2021-06-21 12:46:49 -07:00
a7369b7092
Remove underscores that are no longer needed
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Signed-off-by: Sae86 <sae.batllori@intel.com >
2021-05-05 21:04:45 -07:00
413fc2af3c
Added partial MMIO region dump
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Added the ability to dump a portion of a MMIO region by supplying an
offset and/or length. Note that this does not do any bounds checking
so users can work around configuration limitations and explore more of
the system.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2021-04-30 15:08:07 -07:00
08dd0a7599
General Flake8 formatting cleanup
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Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2021-04-30 15:08:07 -07:00
ede0041b62
Fix payload reading for smi_smmc.
2021-04-30 14:58:34 -07:00
b76de5c38e
Use open() as a context manager instead of explicitly closing the file.
2021-03-31 16:41:45 -07:00
17d02c9499
Print textual representation of the status returned by send_smmc_SMI.
2021-03-31 16:28:10 -07:00
b984dc64c3
Fix a few register cases missed
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-03-31 13:40:31 -07:00
d585f13fc4
Add util config util command
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2021-03-31 13:40:31 -07:00
e86c4946ea
Update pci_cmd.py CLI
2021-03-31 10:38:08 -07:00
8e1cdb26e9
Add smmc port option
2021-03-25 10:13:35 -07:00
eb27e705db
Update interrupts_cmd.py CLI
2021-03-25 10:13:35 -07:00
1607ee8b42
Fixed parameter processing in I/O command
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The I/O command reversed the usage of metavar and the actual parameter.
Also cleaned up the command name and made parameter processing more
consistent with other commands.
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com >
2021-03-09 19:19:16 -08:00
8551e14b39
Update spidesc_cmd.py CLI
2021-01-26 16:11:45 -08:00
14b47b87fc
Update spd_cmd.py CLI
2021-01-26 16:11:06 -08:00
c7259cfac0
Signed-off-by: Sae86 <sae.batllori@intel.com>
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Modifying copyright date.
Hal msg bus - removed non working link
Hal spd - changed simmtester links to functioning ones
Cfg sfdp - added docstring
utilcmd mem_cmd - removed random lonely colon
Modules-Common-cpu-cpuinfo and iauntrusted - added temp docstrings
Tools-vmm-hv and xen folders -> imports needed more detail
Modules Me mfg mode - fixed error caused by asterisk in links
2021-01-26 16:10:34 -08:00
bd16a16d96
Update reg_cmd.py CLI
2021-01-26 16:08:15 -08:00
0caa5709cf
Update msgbus_cmd.py CLI
2021-01-26 16:06:14 -08:00
19922c2b03
Update vmm_cmd.py CLI
2021-01-26 16:05:52 -08:00
a241fdde9a
Update mmcfg_cmd.py CLI
2021-01-26 16:05:11 -08:00
702bb6a9b7
LGTM except
2020-12-15 15:29:25 -08:00
af5d51bb3d
Update vmem_cmd.py CLI
2020-12-15 15:29:25 -08:00
047235888c
Update ucode_cmd.py CLI
2020-12-15 15:28:59 -08:00
8fc0e629a2
Update tmp_util.py CLI
2020-12-15 15:28:46 -08:00
c6854c49e9
Update smbus_cmd.py CLI
2020-11-18 20:38:57 -08:00
b60d5c7ec3
Update spi_cmd.py CLI
2020-11-18 20:38:46 -08:00
a5bc9786f4
Update mem_cmd.py CLI
2020-11-18 20:38:33 -08:00
f942232fc9
Update msr_cmd.py CLI
2020-11-18 20:38:21 -08:00
edc73dacb3
Update iommu_cmd.py CLI
2020-11-18 20:38:10 -08:00
be928b5e56
Add decode option to save specific filetypes
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Modify uefi_cmd to add filetype argument
Modify spi_uefi to parse and save filetypes from a list
Modify spi_uefi to clean up flake8 issues
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2020-10-28 10:47:42 -07:00
350486d171
Update igd_cmd.py CLI
2020-10-28 10:10:37 -07:00
d8011e8601
Update mmio_cmd.py CLI
2020-10-28 10:02:36 -07:00
Nicolas Iooss