7 Commits

Author	SHA1	Message	Date
Sae86	bd9cfe0b95	Move docstring from class ... Update usage in argparser Update for more than one class Signed-off-by: Sae86 <sara.batllori@intel.com>	2021-09-28 10:20:55 -07:00
Nathaniel Mitchell	c8c14e21be	Remove shebang from all but the entry points. Update ep to py3 ... Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>	2021-08-12 08:27:33 -07:00
Aaron Frinzell	bd16a16d96	Update reg_cmd.py CLI	2021-01-26 16:08:15 -08:00
brentholtsclaw	f7fe1be074	More whitespace cleanup ... E231, E201, E226 Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>	2020-07-31 13:46:13 -07:00
BrentHoltsclaw	2efeda4345	Merge python3-rc2 branch into master (#656)	2019-08-15 14:11:20 -07:00
c7zero	16af0c7dfd	More operation in chipsec_util reg command (#238) ... * More operation in chipsec_util reg command Added write, read_field, write_field, get_control, set_control operations * reg read util command updated Returned back "chipsec_util reg read" syntax and added tests. * Commented out test_reg_get_control Need to implement get_MMIO_BAR_base_address or read_pci_reg for SPIBAR in mock_helper.py	2017-07-20 13:05:51 -07:00
Thiébaud Weksteen	9240e1aa58	Add register util command (#217)	2017-05-09 22:55:32 -07:00