f19760c63c
Replace print() with logger.log()
...
Signed-off-by: Dan Scott <dan.scott@intel.com >
2024-08-05 16:35:54 -07:00
aedaa7531f
Fix bug when msgbus_cmd returns wrong value type in windows
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2024-07-30 14:12:32 -07:00
591c10ec75
Fix missing size when doing ec dump
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2024-07-30 11:37:34 -07:00
39cf4bb620
Add UTs for ec_cmd and config_cmd
...
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2024-05-28 16:42:16 -07:00
93bb8b66c6
Add feature so that mmcfg_base reads address for all buses available
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Signed-off-by: Sae86 <sara.batllori@intel.com >
2024-05-28 16:40:35 -07:00
0e8192cfd0
Move files to library folder
2024-03-22 14:26:59 -07:00
a933b1337d
Update references to functions in new library files
2024-03-22 14:26:59 -07:00
1a632de9f4
Update mmcfg command ( #2035 )
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* Update mmcfg command
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2024-01-16 16:39:28 -08:00
2d1866844e
Improvements to iommu_cmd list command
...
Signed-off-by: Sae86 <sara.batllori@intel.com >
2023-12-12 16:43:14 -08:00
8e90f6c25d
Fix except codeql warning
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Signed-off-by: Jason Zhou <jun2.zhou@intel.com >
2023-11-29 16:37:26 -08:00
74a03ac39a
Add default cmd options ini config
...
Signed-off-by: Jason Zhou <jun2.zhou@intel.com >
2023-11-29 16:37:26 -08:00
c282cd9e2c
Add tpm_cmd and txt_cmd unit testing
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Signed-off-by: Sae86 <sara.batllori@intel.com >
2023-10-26 08:42:24 -07:00
00c80ff0c3
Update input name to avoid confusion of msr_cmd.py
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2023-10-25 16:33:54 -07:00
aff7ccc8a4
Update DMAR tables per specification
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Intel Virtualization Technology for Directed I/O Revision 4.1 Order Number: D51397-016
sections 8.3, 8.4, 8.5, 8.6, 8.7, 8.8, 8.9, 8.3.1
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2023-09-20 16:36:21 -07:00
6bbe67a7e6
Update lock_check_cmd to poke 'cs.consistency_checking'
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2023-08-15 16:39:22 -07:00
b40384ffb4
Propogate ability for files not being within LOGPATH
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2023-07-28 09:40:12 -07:00
b3d974b51a
Update modules and utils to match config parsing update
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-07-28 09:34:00 -07:00
fe3202cde9
Update utils to match chipsec_util update
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2023-07-27 11:39:28 -07:00
7e3ccae375
Add typehints and fstrings to igd_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-21 16:40:36 -07:00
1107435bf3
Add typehints and fstrings to ec_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-21 16:40:20 -07:00
2872f2fd90
Add typehints and fstrings to interrupts_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-20 16:36:48 -07:00
daf7d63d9f
Add typehints and fstrings to decode_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:38:34 -07:00
1841d2f1a2
Add typehints and fstrings to io_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:38:12 -07:00
d831476c65
Add typehints and fstrings to iommu_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:38:05 -07:00
01574b182b
Add typehints and fstrings to mem_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:37:51 -07:00
2e05fde8e4
Add typehints and fstrings to mmcfg_base_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:37:38 -07:00
c0adee5d6e
Add typehints and fstrings to mmcfg_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-14 16:37:27 -07:00
fda5180304
Add typehints and fstrings to desc_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-13 16:40:07 -07:00
5c5f334a76
Add typehints and fstrings to deltas_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-13 16:39:49 -07:00
5696bd9f74
Add typehints and fstrings to cpu_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-13 16:39:13 -07:00
704685a477
Add typehints and fstrings to cpu_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-13 16:39:13 -07:00
2e8becedc0
Add typehints and fstrings to cpu_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-06-13 16:39:13 -07:00
e8d41ab9ee
Replace binascii.hexlify with bytes.hex
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Python 3.5 introduced `bytes.hex` to represent bytes in hexadecimal:
https://docs.python.org/3.5/library/stdtypes.html#bytes.hex
This function directly returns a string, contrary to `binascii.hexlify`
which returns bytes. Using `binascii.hexlify` without transforming the
output to string actually produced buggy output. For example:
$ ./chipsec_util.py spidesc spi_rom.bin
...
+ 0x0000 Reserved : 0xb'FFFFFFFFFFFFFFFFFFFFFFFFFFFFFF'
This `b'` is not desired. Using `bytes.hex` fixes this issue and makes
the code simpler.
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2023-06-05 16:43:15 -07:00
4b38d41a29
Move helper.getcwd() from *helper to oshelper
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2023-06-05 16:41:07 -07:00
9be66dadbd
Replace print_buffer(bytestostring(data)) with print_buffer_bytes
...
`print_buffer_bytes` can directly handle bytes, instead of converting
them to a string.
While at it, replace buggy calls to `print_buffer(buffer)` (when
`buffer` uses type `bytes`) with `print_buffer_bytes(buffer)`.
This fixes `./chipsec_util.py idt 0`. Before it failed with:
[CHIPSEC] Dumping IDT of 8 CPU threads
[cpu0] Physical Address: 0x000000036639E000
[cpu0] # of entries : 256
[cpu0] Contents (4 entries):
Traceback (most recent call last):
File "./chipsec_util.py", line 210, in <module>
sys.exit(main())
File "./chipsec_util.py", line 205, in main
return chipsecMain.main()
File "./chipsec_util.py", line 190, in main
comm.run()
File "chipsec/utilcmd/desc_cmd.py", line 84, in run
self.cs.msr.IDT_all(4)
File "chipsec/hal/msr.py", line 166, in IDT_all
self.IDT(tid, num_entries)
File "chipsec/hal/msr.py", line 158, in IDT
return self.dump_Descriptor_Table(cpu_thread_id, DESCRIPTOR_TABLE_CODE_IDTR, num_entries)
File "chipsec/hal/msr.py", line 144, in dump_Descriptor_Table
print_buffer(dt)
File "chipsec/logger.py", line 493, in print_buffer
prt_str = bytes2string(arr, length)
File "chipsec/logger.py", line 466, in bytes2string
num_string += [f'{ord(c):02X} ']
TypeError: ord() expected string of length 1, but int found
There was another bug in `hal/msr.py` where `ord(dt[...])` was used
instead of `dt`.
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2023-05-31 16:39:35 -07:00
7806ebd04c
Make EC, SMBus and SPD use bytes instead of list of characters
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Using a list of unicode characters instead of bytes is strange in Python
3. Replace these lists with bytes, which is the usual type to hold
binary data.
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2023-05-31 16:39:20 -07:00
45f945c760
Add typehints and fstrings to cmos_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-05-26 12:03:28 -07:00
8746808990
Add typehints and fstrings to config_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-05-24 16:36:24 -07:00
77dc15f900
Add typehints and fstrings to config_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-05-24 16:36:24 -07:00
7db7f32b2c
Add typehints and fstrings to acpi_cmd.py
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Signed-off-by: Dan Scott <dan.scott@intel.com >
2023-05-10 16:47:52 -07:00
a2fcfb742c
Remove sphinx warnings and spaces in installation file names
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Signed-off-by: Sara Batllori <sara.batllori@intel.com >
2023-03-24 08:57:25 -07:00
9d08f37dd1
Update doc-string, add Type Hints & fstrings in lock_check_cmd.py
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2023-02-07 16:48:03 -08:00
7af173a43c
Module and command changes to work with hal
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Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com >
2022-12-05 16:34:48 -08:00
291632c0ee
Apply flake8 code formatting rules against repo
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Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com >
2022-07-28 09:17:10 -07:00
69b1f8a5c4
Fixed pylint issue R1703
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Fixed the simplicity of the return deleting bool() in the hasattr function
2022-07-27 17:51:23 -07:00
2444a8fee8
Fixed pylint issue R1719 and E0602
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Fix undefined variable and simplifiable-if-statement
2022-07-27 17:51:23 -07:00
68b3ab8540
Update logger.error() in utilcmd files
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-06-30 11:29:31 -07:00
4b53a058ea
Update logging in spi_cmd.py
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-06-16 16:03:55 -07:00
7a772c0c44
Code clean up in decode_cmd.py
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Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com >
2022-05-18 10:10:01 -07:00
88d185e33f
Add a command to dump Intel TXT public registers
...
Provide a way to dump the content of all TXT registers.
Here is an example of output:
$ ./chipsec_util.py txt state
################################################################
## ##
## CHIPSEC: Platform Hardware Security Assessment Framework ##
## ##
################################################################
[CHIPSEC] Version : 1.8.1
[CHIPSEC] OS : Linux 5.16.5-arch1-1 #1 SMP PREEMPT Tue, 01 Feb 2022 21:42:50 +0000 x86_64
[CHIPSEC] Python : 3.10.2 (64-bit)
****** Chipsec Linux Kernel module is licensed under GPL 2.0
[CHIPSEC] API mode: using CHIPSEC kernel module API
[CHIPSEC] Helper : LinuxHelper (/mnt/data/to-be-backed-up/projects/chipsec/drivers/linux/chipsec.ko)
[CHIPSEC] Platform: Desktop 6th Generation Core Processor Quad Core (Skylake CPU / Sunrise Point PCH)
[CHIPSEC] VID: 8086
[CHIPSEC] DID: 191F
[CHIPSEC] RID: 07
[CHIPSEC] PCH : Intel H170 (100 series) PCH
[CHIPSEC] VID: 8086
[CHIPSEC] DID: A144
[CHIPSEC] RID: 31
[CHIPSEC] Executing command 'txt' with args ['state']
[CHIPSEC] CPUID.01H.ECX[Bit 6] = 1 << Safer Mode Extensions (SMX)
[CHIPSEC] CPUID.01H.ECX[Bit 5] = 1 << Virtual Machine Extensions (VMX)
[CHIPSEC] CR4.SMXE[Bit 14] = 0 << Safer Mode Extensions Enable
[CHIPSEC] CR4.VMXE[Bit 13] = 0 << Virtual Machine Extensions Enable
[CHIPSEC] IA32_FEATURE_CONTROL = 0x00000005 (Processor Feature Control)
[CHIPSEC] [00] LOCK = 1 << Lock
[CHIPSEC] [01] EN_VMX_INSIDE_SMX = 0 << Enable VMX inside SMX operation
[CHIPSEC] [02] EN_VMX_OUTSIDE_SMX = 1 << Enable VMX outside SMX operation
[CHIPSEC] [03] Reserved0 = 0 << Reserved
[CHIPSEC] [08] SENTER_LOCAL_EN = 0 << SENTER Local Functions Enable
[CHIPSEC] [15] SENTER_GLOBAL_EN = 0 << SENTER Global Enable
[CHIPSEC] [16] Reserved1 = 0 << Reserved
[CHIPSEC] [17] SGX_LAUNCH_CTRL_EN = 0 << SGX Launch Control Enable
[CHIPSEC] [18] SGX_GLOBAL_EN = 0 << SGX Global Enable
[CHIPSEC] [19] Reserved2 = 0 << Reserved
[CHIPSEC] [20] LMCE_ON = 0 << Turn Local Machine Check On
[CHIPSEC]
[CHIPSEC] TXT_DIDVID = 0x00000001B0068086 (TXT Device ID, at FED30110)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = B006 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] [48] EXTID = 0 << Extended ID
[CHIPSEC]
[CHIPSEC] TXT Public Key Hash: 2d67ddd75ef9339266a56f27189555ae77a2b0de774222e5de248dbeb8e33dd7
[CHIPSEC] Public Key Hash in MSR[0x20...0x23]: c14a4b4be9b8aa001b65377fe689d252e6c68dcd66d37bce1da9769867d10cfd
[CHIPSEC]
[CHIPSEC] TXT_STS = 0x0000000000000002 (TXT Status, at FED30000)
[CHIPSEC] [00] SENTER_DONE_STS = 0 << SENTER Done
[CHIPSEC] [01] SEXIT_DONE_STS = 1 << SEXIT Done
[CHIPSEC] [04] MEM_UNLOCK_STS = 0 << Memory Unlocked
[CHIPSEC] [06] MEM_CONFIG_LOCK_STS = 0 << Memory Configuration Locked
[CHIPSEC] [07] PRIVATE_OPEN_STS = 0 << Open-Private Command Performed
[CHIPSEC] [10] NTP_ENABLE_STS = 0 << NTP Enabled
[CHIPSEC] [11] MEM_CONFIG_OK_STS = 0 << Mem CFG OK
[CHIPSEC] [12] PMRC_LOCK_STS = 0 << PMRC Locked
[CHIPSEC] [13] SMM_OPEN_STS = 0 << SMM Opened
[CHIPSEC] [14] TXT_LOCALITY3_OPEN_STS = 0 << Locality 3 Opened
[CHIPSEC] [15] TXT_LOCALITY1_OPEN_STS = 0 << Locality 1 Opened
[CHIPSEC] [16] TXT_LOCALITY2_OPEN_STS = 0 << Locality 2 Opened
[CHIPSEC] TXT_ESTS = 0x0000000000000000 (TXT Error Status, at FED30008)
[CHIPSEC] [00] TXT_RESET_STS = 0 << TXT Reset
[CHIPSEC] [01] ROGUE_STS = 0 << Rogue Status
[CHIPSEC] [06] WAKE_ERROR_STS = 0 << Wake Error
[CHIPSEC] TXT_E2STS = 0x0000000000000004 (TXT Extended Error Status, at FED308F0)
[CHIPSEC] [01] SECRETS_STS = 0 << Secrets in Memory
[CHIPSEC] TXT_ERRORCODE = 0x0000000000000000 (TXT Error Code (0xC0000001 when successful SINIT), at FED30030)
[CHIPSEC] [00] TYPE2_MODULE_TYPE = 0 << Module Type (0 for BIOS ACM, 1 for SINIT)
[CHIPSEC] [04] TYPE2_CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] TYPE2_MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] SOFTWARE_SOURCE = 0 << Software Source (0 for ACM, 1 of MLE)
[CHIPSEC] [16] TYPE1_MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [28] TYPE1_RESERVED = 0 << Failure Condition Details
[CHIPSEC] [30] SOFTWARE = 0 << Error reported by Software (0 for Processor)
[CHIPSEC] [31] VALID = 0 << Valid Register Content
[CHIPSEC]
[CHIPSEC] TXT_SPAD = 0x0000000000000000 (Boot Status, at FED300A0)
[CHIPSEC] [00] ACM_INTERNAL = 0 << ACM Internal Use
[CHIPSEC] [30] TXT_STARTUP_SUCCESS = 0 << TXT Startup Success
[CHIPSEC] [31] BOOT_STATUS = 0 << General Startup ACM to BIOS status communication
[CHIPSEC] [47] MEM_POWER_DOWN_EXECUTED = 0 << Memory content was cleared via power down
[CHIPSEC] [48] BOOT_STATUS_DETAILS_48 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [53] TXT_POLICY_ENABLE = 0 << Startup ACM indication of run-time enabled status of TXT
[CHIPSEC] [54] BOOT_STATUS_DETAILS_54 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [59] BIOS_TRUSTED = 0 << BIOS is trusted
[CHIPSEC] [60] TXT_POLICY_DISABLE = 0 << TXT has been disabled by runtime FIT type 0xA record policy setting
[CHIPSEC] [61] BOOT_STATUS_DETAILS_61 = 0 << Startup ACM to BIOS communication in MP platforms
[CHIPSEC] [62] CPU_ERROR = 0 << ACM authentication error
[CHIPSEC] [63] S_ACM_SUCCESS = 0 << S-ACM successfully enforced its logic for all provisioned technologies
[CHIPSEC] TXT_ACM_STATUS = 0x00000000 (TXT ACM Status, at FED30328)
[CHIPSEC] [00] MODULE_TYPE = 0 << Module Type
[CHIPSEC] [04] CLASS_CODE = 0 << Class Code
[CHIPSEC] [10] MAJOR_ERROR_CODE = 0 << Major Error Code
[CHIPSEC] [15] ACM_STARTED = 0 << ACM Started
[CHIPSEC] [16] MINOR_ERROR_CODE = 0 << Minor Error Code
[CHIPSEC] [31] VALID = 0 << Valid
[CHIPSEC] TXT_FIT = 0x00000000 (FIT (Firmware Interface Table), at FED30340)
[CHIPSEC] [00] FIT_FAILED = 0 << FIT Failed
[CHIPSEC] [01] S_ACM_FAILED = 0 << S-ACM Failed
[CHIPSEC] [02] FIT_MEASURED = 0 << FIT Measured
[CHIPSEC] [03] FIT_FALLBACK = 0 << FIT Fallback
[CHIPSEC] TXT_SCRATCHPAD = 0x0000000000000000 (ACM Policy Status, at FED30378)
[CHIPSEC] [13] TPM_TYPE = 0 << TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)
[CHIPSEC] [15] TPM_SUCCESS = 0 << TPM Success
[CHIPSEC] [17] BOOT_POLICIES_2 = 0 << Boot Policies
[CHIPSEC] [18] BACKUP_ACTION = 0 << Backup Action
[CHIPSEC] [20] TXT_PROFILE = 0 << TXT Profile
[CHIPSEC] [25] MEMORY_SCRUB_POLICY = 0 << Memory Scrub Policy
[CHIPSEC] [29] IBB_DMA_PROTECTION = 0 << IBB (Initial Boot Block) DMA Protection
[CHIPSEC] [32] S_CRTM_STATUS = 0 << Startup ACM S-CRTM establishment
[CHIPSEC] [35] CPU_COSIGNING_ENABLE = 0 << CPU co-signing enabled
[CHIPSEC] [36] TPM_STARTUP_LOCALITY = 0 << Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)
[CHIPSEC]
[CHIPSEC] TXT_SINIT_BASE = 0x00000000 (SINIT Base Address, at FED30270)
[CHIPSEC] TXT_SINIT_SIZE = 0x00000000 (SINIT Size, at FED30278)
[CHIPSEC] TXT_MLE_JOIN = 0x00000000 (MLE Join Base Address, at FED30290)
[CHIPSEC] TXT_HEAP_BASE = 0x00000000 (TXT Heap Base Address, at FED30300)
[CHIPSEC] TXT_HEAP_SIZE = 0x00000000 (TXT Heap Size, at FED30308)
[CHIPSEC] TXT_MSEG_BASE = 0x00000000 (TXT MSEG Base Address, at FED30310)
[CHIPSEC] TXT_MSEG_SIZE = 0x00000000 (TXT MSEG Size, at FED30318)
[CHIPSEC]
[CHIPSEC] TXT_DPR = 0x00000000 (TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR), at FED30330)
[CHIPSEC] [00] LOCK = 0 << Lock Bits 19:0
[CHIPSEC] [04] SIZE = 0 << Protected Memory Size (in MB)
[CHIPSEC] [20] TOP = 0 << Top Address+1 of DPR (base of TSEG)
[CHIPSEC] TXT_VER_FSBIF = 0xFFFFFFFF (TXT Front Side Bus Interface, at FED30100)
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_VER_QPIIF = 0x9D003000 (TXT Intel QuickPath Interconnect Interface, at FED30200)
[CHIPSEC] [19] PMRC_CAPABLE = 0 << PMRC Capable
[CHIPSEC] [26] DPR_CAPABLE = 1 << DPR Capable
[CHIPSEC] [31] DEBUG_FUSE = 1 << Chipset is Production Fused (0 for Debug)
[CHIPSEC] TXT_PCH_DIDVID = 0x00000001A1448086 (TXT Platform Controller Hub Device ID, at FED30810)
[CHIPSEC] [00] VID = 8086 << Vendor ID
[CHIPSEC] [16] DID = A144 << Device ID
[CHIPSEC] [32] RID = 1 << Revision ID
[CHIPSEC] INSMM = 0x00000000 (InSMM.STS, at FED30880)
[CHIPSEC] [00] STS = 0 << BIOS Write Enable when enabled by SPI.BC.EISS=1
Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org >
2022-02-28 15:49:48 -08:00
Dan Scott