admin/chipsec-chipsec
1
0
Fork 0
mirror of https://github.com/chipsec/chipsec synced 2026-06-08 13:31:00 +00:00
Code Issues Packages Projects Releases Wiki Activity
2,553 Commits 16 Branches 107 Tags
fc2b3cbbbb5433364348cc4e0b1cd4fda7e7bf85
Commit Graph

63 Commits

Author SHA1 Message Date
Nathaniel Mitchell 34015902fd Add defaults when getting options 2026-04-16 13:19:48 -07:00
brentholtsclaw db40bd72bf Fix if from MMIO range within configuration 
FIX: get_objlist() with a single-component name like 'PCU_MMIO' does scope
resolution that searches at Platform level (vendors), not inside any vendor.
The range IP exists at Vendor('8086') -> IP('PCU_MMIO') but is unreachable
via single-component scope. Search MEMORY_RANGES dict directly as fallback.

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-03-23 16:38:26 -07:00
William Leara 79f81bbb7e fix for flake8 rules related to whitespace 
This commit fixes whitespace errors from checkers W291,W292,W293,W391.  They were found by running "flake8 ." from the root directory.  These are errors defined by "pycodestyle", and have no functional impact to the source.  This is simply fixing whitespace as defined by CHIPSEC's .flake8 configuration.

background:
https://www.flake8rules.com/rules/W291.html
https://www.flake8rules.com/rules/W292.html
https://www.flake8rules.com/rules/W293.html
https://www.flake8rules.com/rules/W391.html

tool versions: flake8 v7.3.0, python v3.13.11

Signed-off-by: William Leara <william.leara@dell.com>
 2026-03-10 14:20:23 -07:00
LEE YONGJIN 8391f35706 Fix typo and missing object reference in interrupt HAL 
Fix an execution error in the send_smmc_SMI function by:
- Correcting the HAL module name typo (memorymem -> memory)
- Adding the missing chipset object reference (cs)

Signed-off-by: LEE YONGJIN <0jin.git@gmail.com>
 2026-03-10 11:33:21 -07:00
brentholtsclaw 6d27c8b95f enforce uppercase registernames 
Fix instances where registers were able to be referenced as lowercase
causing errors

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-02-11 09:58:05 -08:00
brentholtsclaw ad7e148041 Requested Fixes 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-01-29 13:43:54 -08:00
brentholtsclaw e5f5668159 dev/chipsec2 Add basic acpi aml parser 
Add basic parser for dsdt and sdst tables to find memory regions.  Still
recommend using acpi and iasl for full results.

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-01-29 13:43:54 -08:00
brentholtsclaw 6c19755952 Requested Fixes 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-01-29 13:31:48 -08:00
brentholtsclaw 9988bc0a6e Update IOMMU to use DMAR parsing 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2026-01-29 13:31:48 -08:00
Nathaniel Mitchell 93c2a23d7c Enable MMIO BAR Address cacheing (resolves unit test failure) 
Original commit for chipsec v1: 60ab31da9d

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2026-01-29 11:59:38 -08:00
William Leara e6a67f3be0 remove unused imports from ec.py 
These imports are not used within this module.

Signed-off-by: William Leara <william.leara@dell.com>
 2026-01-29 11:59:38 -08:00
brentholtsclaw 3dfc3c27b0 Minor bug fixes 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-12-09 13:50:59 -08:00
Nathaniel Mitchell 1259e568de Change all HAL objects in cs.hals to be lowercase 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-12-09 13:49:37 -08:00
brentholtsclaw 92cfae82fb dev/chipsec2 fixes 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-09-02 10:20:38 -07:00
Nathaniel Mitchell c50165a2a4 Add 'is_enabled' to regs and 'filter_enabled' to objlist 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-09-01 22:45:59 -07:00
Nathaniel Mitchell 99f9b9c6f4 Update files 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-07-23 15:09:44 -07:00
brentholtsclaw 77bb71e895 Splitting msgbus and mm_msgbus 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-06-05 11:35:52 +08:00
brentholtsclaw 51065bc7a9 Fix locks functionality to work with register objects 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-06-05 07:54:21 +08:00
brentholtsclaw 5ee89e8675 Split mmcfg into separate hal 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-05-28 00:06:20 +08:00
brentholtsclaw f7f5f2c610 Add pci write function for hal 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-05-15 09:07:28 -07:00
Nathaniel Mitchell e918c17494 Clean up debug and commented out code 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell 14bda6657d Update iommu unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell 5aaf69f6d0 Get iommu working 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell 7f669cfd2d Add register specific functions to platform.py 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-08 01:07:54 +08:00
Nathaniel Mitchell b8d11ca5d9 Initial commit for new Cfg.platform object and register structure 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-05-02 09:06:31 -07:00
Nathaniel Mitchell 439c1a4d09 General update to chipsec2 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-04-18 12:00:31 -07:00
Nathaniel Mitchell bea2860e8e Update device functions and port register.read*/write* functions 
Updated the device.get_obj/objlist functions to match the other types e.g. "get_list_by_name" and "get_instance_by_name".

Updated register.read/read_field/write/write_field functions to first get the register objects, then read*/write* from there.

Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-18 16:29:21 -07:00
Nathaniel Mitchell de6ffa0409 Update smbus hal, cmd and unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-17 09:07:19 -07:00
Nathaniel Mitchell c8cfacd732 Move paging from hal to library 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-12 09:07:23 -07:00
Nathaniel Mitchell 088a2ca69c Fixup spi HAL and additional unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-11 20:45:54 -07:00
Nathaniel Mitchell 947f67a6e1 Fix acpi tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-11 20:45:54 -07:00
Nathaniel Mitchell 4b65243d9c Fix more unit tests 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-10 09:06:35 -07:00
Nathaniel Mitchell 9d3e2842f0 fix iobar, and a few modules 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-05 07:59:36 -08:00
Nathaniel Mitchell b59f5a5525 Fix second level mmio ranages 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-05 07:59:36 -08:00
Nathaniel Mitchell b9c9b0afac Few fixes, mostly WRT mmio 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-05 07:59:36 -08:00
Nathaniel Mitchell 443b019f32 Few fixes, mostly WRT mmio 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-05 07:59:36 -08:00
Nathaniel Mitchell f0fb769d70 Move acpi_tables to library from hal 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-04 22:15:21 -08:00
Nathaniel Mitchell 7e1a53149e Add fix to interrupts_cmd 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-04 22:15:21 -08:00
Nathaniel Mitchell 29d1a2a364 Update to hals 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-04 22:15:21 -08:00
brentholtsclaw 51b088ffae Normalize spi and spi descriptor 
SPI descriptor still needs changes but this should help get it working

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-03-04 22:15:04 -08:00
brentholtsclaw f9021e8ea8 dev/chipsec2 - spi_jedec_ids 
Moving to library

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-03-04 22:15:04 -08:00
Nathaniel Mitchell b5a34ffd49 Update rtclock module 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-03-03 09:04:08 -08:00
brentholtsclaw 4877f96d0e Fixing comments 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-25 17:03:50 -08:00
brentholtsclaw 642c9c6470 Update tpm for dev/chipsec2 
Move tpm12_commands and tpm_events to library
Change logic to remove bare except
Use hals functionality
Add read, write functions to normalize functionality

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-25 17:03:50 -08:00
Nathaniel Mitchell 655014a50f Update igd hal 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-25 10:57:24 -08:00
brentholtsclaw 1f5ab18ae0 Updating to satisfy comments 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-25 10:22:47 -08:00
brentholtsclaw 07f123c96c /dev/chipsec2 ucode hal update 
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-25 10:22:47 -08:00
brentholtsclaw 21e45ae281 dev/chipsec2 fix rebase issue 
hal/spi_uefi was moved to library/uefi/spi.  It appears to have returned
due to a separate PR

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
 2025-02-20 12:31:34 -08:00
Nathaniel Mitchell 7725ebe841 Enable bios_wp module to run successfully on ADL 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-18 13:19:38 -08:00
Nathaniel Mitchell 6164ca86db Update to enable mmio 
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
 2025-02-18 13:19:38 -08:00