24 Commits

Author SHA1 Message Date
Dan Scott 0e8192cfd0 Move files to library folder 2024-03-22 14:26:59 -07:00
Dan Scott a933b1337d Update references to functions in new library files 2024-03-22 14:26:59 -07:00
Nathaniel Mitchell ae0bd2a053 Fix hal.cpu to not call set_affinity in single threaded env
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2024-02-12 16:36:17 -08:00
Frinzell, Aaron a2867869bd Type Hint and fstring updates to cpu.py
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2023-02-07 16:47:29 -08:00
Nathaniel Mitchell 291632c0ee Apply flake8 code formatting rules against repo
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2022-07-28 09:17:10 -07:00
Ricardo Brandan c27a83999d Remove parenthesis 2022-07-25 17:04:42 -07:00
Ricardo Brandan a677f27fb3 fix simplified-if-expression 2022-07-25 17:04:42 -07:00
Frinzell, Aaron 1b9b194c78 Update logger.error() in hal modules
Signed-off-by: Frinzell, Aaron <aaron.frinzell@intel.com>
2022-06-30 10:50:37 -07:00
brentholtsclaw 0e53326a83 Create exceptions.py for chipsec exceptions
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2021-08-26 10:50:51 -07:00
Nathaniel Mitchell c8c14e21be Remove shebang from all but the entry points. Update ep to py3
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
2021-08-12 08:27:33 -07:00
Ignacio Hernandez 57ff8b6bd2 Adding get_cpu_topology()
Returns a topology dictionary which contains two dictionaries:
'packages', where each item  contains a list of the threads
	    sharing the same package_id
'cores', where each item contains the list of threads running on
         the same physical core.

Signed-off-by: Ignacio Hernandez <ignacio.hernandez@intel.com>
2020-08-27 11:05:14 -07:00
brentholtsclaw f7fe1be074 More whitespace cleanup
E231, E201, E226

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-07-31 13:46:13 -07:00
brentholtsclaw a00b2838e5 Cleanup trailing whitespace
W291,W293,W391

Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-07-01 15:44:21 -07:00
brentholtsclaw f2b0d31d31 HAL fixes from LGTM (1/3)
Signed-off-by: brentholtsclaw <brent.holtsclaw@intel.com>
2020-04-16 12:00:18 -07:00
BrentHoltsclaw 2efeda4345 Merge python3-rc2 branch into master (#656) 2019-08-15 14:11:20 -07:00
BrentHoltsclaw 2d1d96b5cb Util_cmd cpu fixup info command
Changed find_EFI_Configuration_Table to not log error and only log if HAL logging is enabled
Changed get_number_threads_from_APIC_table to utilize return structure from get_parse_ACPI_table

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-07-16 09:47:17 -07:00
Eli 84f470eff1 Removed workaround for RwEverything over Hyper-V
A workaround for RWE driver causing CHIPSEC over Hyper-V to report SMRR is not supported regardless of used driver.
Since CHIPSEC manual states that it no longer supprts RwEverything driver on Windows, that workaround should be removed.
If this workaround is still needed for some reason, better tell RWE driver from CHIPSEC driver, and act accordingly.
2019-07-03 10:42:52 -07:00
BrentHoltsclaw 789314a142 Normalizing logging for various sections of chipsec:
HAL now only use logger().HAL
helpers now only use logger.DEBUG
modules now only use logger.VERBOSE
2019-04-25 14:19:08 -07:00
Takaaki Fukai f6bc58abcd Fix module references in chipsec/hal/cpu.py 2017-09-13 10:07:38 -07:00
Thiébaud Weksteen bdea49936a Remove unused __version__ (#215) 2017-05-08 22:17:35 -07:00
Andrew Furtak 14904f35e6 RWE helper added. SMRR support check added where required. HyperV workaround for SMRR msrs. 2017-02-22 13:07:36 -08:00
abazhaniuk c377a72e28 Deb package (#135)
* merge

* Add Debian packaging

* cleanup

* Removed incorrect info into Copyright.

* One more: removed incorrect info in Copyright.
2017-01-06 12:57:13 -08:00
Thiébaud Weksteen 1a284132f8 Use HALBase for all HAL modules (#124) 2016-11-17 23:21:26 -08:00
abazhaniuk 94fe7f02f1 change setup.py build driver by default. change root directory of chipsec. move WARNING.txt to chipsec. remove PKG-INFO (#107) 2016-10-18 18:19:42 -07:00