admin/chipsec-chipsec
1
0
Fork 0
mirror of https://github.com/chipsec/chipsec synced 2026-06-08 13:31:00 +00:00
Code Issues Packages Projects Releases Wiki Activity
Files
Expand_Arch
chipsec-chipsec/chipsec/cfg/cfl.xml
T
Erik Bjorge ed544448b9 Adding fixed address fallback support 
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-07-23 11:14:17 -07:00

284 lines
16 KiB
XML
Raw Permalink Blame History

<?xml version="1.0"?>
<configuration platform="CFL">
<!--
XML configuration file for Coffee Lake
* 8th Generation Intel(R) Processor Family for S-Processor Platforms
https://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
-->
<!-- #################################### -->
<!-- -->
<!-- Integrated devices -->
<!-- -->
<!-- #################################### -->
<pci>
<device name="P2SBC" bus="0" dev="0x1F" fun="1" vid="0x8086" />
<device name="SMBUS" bus="0" dev="0x1F" fun="4" vid="0x8086" />
<device name="SPI" bus="0" dev="0x1F" fun="5" vid="0x8086" />
</pci>
<!-- #################################### -->
<!-- -->
<!-- Memory Mapped I/O spaces (MMIO BARs) -->
<!-- -->
<!-- #################################### -->
<mmio>
<bar name="GTTMMADR" bus="0" dev="2" fun="0" reg="0x10" width="8" mask="0x7FFF000000" desc="Graphics Translation Table Range"/>
<bar name="HDABAR" bus="0" dev="0x1F" fun="3" reg="0x10" width="8" mask="0xFFFFFFFFFFFFC000" size="0x1000" desc="HD Audio Base"/>
<bar name="SPIBAR" bus="0" dev="0x1F" fun="5" reg="0x10" width="4" mask="0xFFFFF000" size="0x1000" desc="SPI Controller Register Range" offset="0x0"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" fixed_address="0xFE000000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" fixed_address="0xFD000000" desc="Sideband Register Access BAR"/>
</mmio>
<!-- #################################### -->
<!-- -->
<!-- I/O spaces (I/O BARs) -->
<!-- -->
<!-- #################################### -->
<io>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" desc="ACPI Base Address"/>
<bar name="TCOBASE" register="TCOBASE" base_field="TCOBA" size="0x20" desc="TCO Base Address"/>
<!-- old definition -->
<bar name="SMBUS_BASE" bus="0" dev="0x1F" fun="4" reg="0x20" mask="0xFFE0" size="0x80" desc="SMBus Base Address"/>
</io>
<!-- #################################### -->
<!-- -->
<!-- Memory ranges -->
<!-- -->
<!-- #################################### -->
<memory>
</memory>
<!-- #################################### -->
<!-- -->
<!-- Configuration registers -->
<!-- -->
<!-- #################################### -->
<registers>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- PCIe Configuration registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Sideband Register Access Registers -->
<register name="SBREG_BAR" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x10" size="4" desc="Sideband Register Access BAR">
<field name="RBA" bit="24" size="8" desc="Register Base Address"/>
</register>
<register name="P2SBC" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0xE0" size="2" desc="P2SB Configuration Register">
<field name="HIDE" bit="8" size="1" desc="Hide SBREG_BAR"/>
</register>
<register name="P2SB_HIDE" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0xE1" size="1" desc="P2SB Configuration Register hide-unhide">
<field name="HIDE" bit="0" size="1" desc="Hide SBREG_BAR"/>
</register>
<!-- Power Management Controller -->
<register name="ABASE" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x40" size="4" desc="ACPI Base Address">
<field name="STYPE" bit="0" size="1" desc="Space Type (always 1 - I/O space)"/>
<field name="BA" bit="8" size="8" desc="Base Address"/>
</register>
<register name="ACTL" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x44" size="4" desc="ACPI Control">
<field name="SCIS" bit="0" size="2" desc="SCI IRQ Select"/>
<field name="EN" bit="7" size="1" desc="ACPI Enable"/>
<field name="PWRM_EN" bit="8" size="1" desc="PWRM Enable"/>
</register>
<register name="PWRMBASE" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0x48" size="4" desc="PM Base Address">
<field name="STYPE" bit="0" size="1" desc="Space Type (always 0 - memory space)"/>
<field name="BA" bit="12" size="20" desc="Base Address"/>
</register>
<register name="GEN_PMCON_1" type="pcicfg" bus="0" dev="0x1f" fun="2" offset="0xA0" size="2" desc="General PM Configuration A">
<field name="SMI_LOCK" bit="4" size="1"/>
</register>
<!-- SMBus Host Controller -->
<register name="SMBUS_VID" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x00" size="2" desc="VID" />
<register name="SMBUS_DID" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x02" size="2" desc="DID" />
<register name="SMBUS_CMD" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x04" size="2" desc="CMD" />
<register name="SMBUS_HCFG" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x40" size="1" desc="Host Configuration">
<field name="HST_EN" bit="0" size="1"/>
<field name="SMB_SMI_EN" bit="1" size="1"/>
<field name="I2C_EN" bit="2" size="2"/>
<field name="SSRESET" bit="3" size="1"/>
<field name="SPD_WD" bit="4" size="1"/>
</register>
<register name="TCOBASE" type="pcicfg" bus="0" dev="0x1f" fun="4" offset="0x50" size="4" desc="TCO Base Address">
<field name="IOS" bit="0" size="1" desc="I/O space"/>
<field name="TCOBA" bit="5" size="11" desc="TCO Base Address"/>
</register>
<register name="TCOCTL" type="pcicfg" bus="0" dev="0x1f" fun="4" offset="0x54" size="4" desc="TCO Control">
<field name="TCO_BASE_LOCK" bit="0" size="1" desc="TCO Base Lock"/>
<field name="TCO_BASE_EN" bit="8" size="1" desc="TCO Base Enable"/>
</register>
<!-- SPI Interface Controller -->
<register name="BC" type="pcicfg" bus="0" dev="0x1F" fun="5" offset="0xDC" size="4" desc="BIOS Control">
<field name="BIOSWE" bit="0" size="1" desc="BIOS Write Enable" />
<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable" />
<field name="SRC" bit="2" size="2" desc="SPI Read Configuration" />
<field name="TSS" bit="4" size="1" desc="Top Swap Status" />
<field name="SMM_BWP" bit="5" size="1" desc="SMM BIOS Write Protection" />
<field name="BBS" bit="6" size="1" desc="Boot BIOS Strap" />
<field name="BILD" bit="7" size="1" desc="BIOS Interface Lock Down"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- MMIO registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- PCH SPIBAR registers -->
<register name="HSFS" type="mmio" bar="SPIBAR" offset="0x04" size="4" desc="Hardware Sequencing Flash Status Register">
<field name="FDONE" bit="0" size="1" desc="Flash Cycle Done"/>
<field name="FCERR" bit="1" size="1" desc="Flash Cycle Error"/>
<field name="AEL" bit="2" size="1" desc="Access Error Log"/>
<field name="SCIP" bit="5" size="1" desc="SPI cycle in progress"/>
<field name="WRSDIS" bit="11" size="1" desc="Write status disable"/>
<field name="PR34LKD" bit="12" size="1" desc="PRR3 PRR4 Lock-Down"/>
<field name="FDOPSS" bit="13" size="1" desc="Flash Descriptor Override Pin-Strap Status"/>
<field name="FDV" bit="14" size="1" desc="Flash Descriptor Valid"/>
<field name="FLOCKDN" bit="15" size="1" desc="Flash Configuration Lock-Down"/>
<field name="FGO" bit="16" size="1" desc="Flash cycle go"/>
<field name="FCYCLE" bit="17" size="4" desc="Flash Cycle Type"/>
<field name="WET" bit="21" size="1" desc="Write Enable Type"/>
<field name="FDBC" bit="24" size="6" desc="Flash Data Byte Count"/>
<field name="FSMIE" bit="31" size="1" desc="Flash SPI SMI# Enable"/>
</register>
<register name="FREG0_FLASHD" type="mmio" bar="SPIBAR" offset="0x54" size="4" desc="Flash Region 0 (Flash Descriptor)">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG1_BIOS" type="mmio" bar="SPIBAR" offset="0x58" size="4" desc="Flash Region 1 (BIOS)">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG2_ME" type="mmio" bar="SPIBAR" offset="0x5C" size="4" desc="Flash Region 2 (ME)">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG3_GBE" type="mmio" bar="SPIBAR" offset="0x60" size="4" desc="Flash Region 3 (GBe)">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG4_PD" type="mmio" bar="SPIBAR" offset="0x64" size="4" desc="Flash Region 4 (Platform Data)">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG5" type="mmio" bar="SPIBAR" offset="0x68" size="4" desc="Flash Region 5">
<field name="RB" bit="0" size="15" desc="Region Base"/>
<field name="RL" bit="16" size="15" desc="Region Limit"/>
</register>
<register name="FREG6" undef="Flash Region 6 not defined for this platform" />
<register name="PR0" type="mmio" bar="SPIBAR" offset="0x84" size="4" desc="Protected Range 0">
<field name="PRB" bit="0" size="13"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR1" type="mmio" bar="SPIBAR" offset="0x88" size="4" desc="Protected Range 1">
<field name="PRB" bit="0" size="13"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR2" type="mmio" bar="SPIBAR" offset="0x8C" size="4" desc="Protected Range 2">
<field name="PRB" bit="0" size="13"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR3" type="mmio" bar="SPIBAR" offset="0x90" size="4" desc="Protected Range 3">
<field name="PRB" bit="0" size="13"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR4" type="mmio" bar="SPIBAR" offset="0x94" size="4" desc="Protected Range 4">
<field name="PRB" bit="0" size="13"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="FDOC" type="mmio" bar="SPIBAR" offset="0xB4" size="4" desc="Flash Descriptor Observability Control Register">
<field name="FDSI" bit="2" size="10" desc="Flash Descriptor Section Index"/>
<field name="FDSS" bit="12" size="3" desc="Flash Descriptor Section Select"/>
</register>
<register name="FDOD" type="mmio" bar="SPIBAR" offset="0xB8" size="4" desc="Flash Descriptor Observability Data Register">
<field name="FDSD" bit="0" size="32" desc="Flash Descriptor Section Data"/>
</register>
<register name="LVSCC" type="mmio" bar="SPIBAR" offset="0xC4" size="4" desc="Vendor Specific Component Capabilities">
<field name="WG" bit="2" size="1" desc="Write Granularity"/>
<field name="WSR" bit="3" size="1" desc="Write Status Required"/>
<field name="WEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="QER" bit="5" size="3" desc="Quad Enable Requirements"/>
<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
<field name="SOFT_RST_SUP" bit="24" size="1" desc="Soft Reset Supported"/>
<field name="SUSPEND_RESUME_SUP" bit="25" size="1" desc="Suspend/Resume Supported"/>
<field name="DEEP_PWRDN_SUP" bit="26" size="1" desc="Deep Powerdown Supported"/>
<field name="RPMC_SUP" bit="27" size="1" desc="RPMC Supported"/>
<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
<field name="VCL" bit="30" size="1" desc="Vendor Component Lock"/>
<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
</register>
<register name="UVSCC" type="mmio" bar="SPIBAR" offset="0xC8" size="4" desc="Vendor Specific Component Capabilities">
<field name="WG" bit="2" size="1" desc="Write Granularity"/>
<field name="WSR" bit="3" size="1" desc="Write Status Required"/>
<field name="WEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="QER" bit="5" size="3" desc="Quad Enable Requirements"/>
<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
<field name="SOFT_RST_SUP" bit="24" size="1" desc="Soft Reset Supported"/>
<field name="SUSPEND_RESUME_SUP" bit="25" size="1" desc="Suspend/Resume Supported"/>
<field name="DEEP_PWRDN_SUP" bit="26" size="1" desc="Deep Powerdown Supported"/>
<field name="RPMC_SUP" bit="27" size="1" desc="RPMC Supported"/>
<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
</register>
<!-- PCH RTC registers -->
<register name="RC" type="mm_msgbus" port="0xC3" offset="0x3400" size="4" desc="RTC Configuration">
<field name="UE" bit="2" size="1" desc="Upper 128 Byte Enable"/>
<field name="LL" bit="3" size="1" desc="Lower 128 Byte Lock"/>
<field name="UL" bit="4" size="1" desc="Upper 128 Byte Lock"/>
<field name="BILD" bit="31" size="1" desc="BIOS Interface Lock-Down"/>
</register>
<register name="BUC" type="mm_msgbus" port="0xC3" offset="0x3414" size="4" desc="Backed Up Control">
<field name="TS" bit="0" size="1" desc="Top Swap"/>
</register>
<register name="PM_CFG" type="mmio" bar="PWRMBASE" offset="0x18" size="4" desc="Power Management Configuration Reg 1"/>
<!-- DCI registers -->
<register name="ECTRL" type="mm_msgbus" port="0xB8" offset="0x0004" size="4" desc="DCI Control Register">
<field name="ENABLE" bit="4" size="1"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- I/O registers (I/O ports) -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- PCH TCOBASE (SMBus TCO) I/O registers -->
<register name="TCO1_CNT" type="iobar" bar="TCOBASE" offset="0x8" size="2" desc="TCO1 Control">
<field name="TCO_LOCK" bit="12" size="1" desc="TCO Lock"/>
</register>
</registers>
<!-- #################################### -->
<!-- -->
<!-- 'Controls' -->
<!-- -->
<!-- #################################### -->
<controls>
<control name="BiosInterfaceLockDown" register="BC" field="BILD" desc="BIOS Interface Lock-Down"/>
<control name="SpiWriteStatusDis" register="HSFS" field="WRSDIS" desc="Write Status Disable"/>
</controls>
</configuration>
Reference in New Issue View Git Blame Copy Permalink