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chipsec-chipsec/chipsec/cfg/cht.xml
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Erik Bjorge e754444f1c Improve configuration doc formatting 
Signed-off-by: Erik Bjorge <erik.c.bjorge@intel.com>
2019-03-05 17:25:06 -08:00

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<?xml version="1.0"?>
<configuration platform="CHT">
<!--
XML configuration for Cherry Trail and Braswell SoCs
* Intel(R) Atom(TM) Processor Z8000 series datasheet
http://www.intel.com/content/www/us/en/processors/atom/atom-z8000-datasheet-vol-2.html
* N-series Intel(R) Pentium(R) and Celeron(R) Processors Datasheet
http://www.intel.com/content/dam/www/public/us/en/documents/datasheets/pentium-celeron-n-series-datasheet-vol-2.pdf
-->
<!-- #################################### -->
<!-- -->
<!-- Memory Mapped I/O spaces (MMIO BARs) -->
<!-- -->
<!-- #################################### -->
<mmio>
<!-- Section 4.1.7-8 -->
<bar name="GTTMMADR" bus="0" dev="0x02" fun="0" reg="0x10" width="8" mask="0xFFFFFFF0FFC00000" desc="Graphics Translation Table Range"/>
<!-- Section 35.6 -->
<bar name="PMBASE" register="PBASE" base_field="Base" size="0x200" enable_field="Enable" desc="PM Base"/>
<bar name="IOBASE" register="IOBASE" base_field="Base" size="0x2000" enable_field="Enable" desc="I/O Controller Base"/>
<bar name="IBASE" register="IBASE" base_field="Base" size="0x200" enable_field="Enable" desc="iLB Base"/>
<bar name="MPBASE" register="MPBASE" base_field="Base" size="0x100000" enable_field="Enable" desc="MPHY Base"/>
<bar name="PUBASE" register="PUBASE" base_field="Base" size="0x800" enable_field="Enable" desc="PUnit Base"/>
<bar name="SPIBAR" register="SBASE" base_field="Base" size="0x200" enable_field="Enable" desc="SPI Base"/>
<bar name="MMCFG" register="BECREG" base_field="ECBASE" size="0x10000000" enable_bit="ECENABLE" desc="PCI Express Register Range"/>
</mmio>
<!-- #################################### -->
<!-- -->
<!-- I/O spaces (I/O BARs) -->
<!-- -->
<!-- #################################### -->
<io>
<!-- Section 10.20 -->
<bar name="ABASE" register="ABASE" base_field="Base" size="0x1000" enable_field="Enable" desc="ACPI Base Address"/>
<bar name="GBASE" register="GBASE" base_field="Base" size="0x100" enable_field="Enable" desc="GPIO Base Address"/>
</io>
<!-- #################################### -->
<!-- -->
<!-- Configuration registers -->
<!-- -->
<!-- #################################### -->
<registers>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- PCIe Configuration registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Sections 1.6 -->
<register name="MSG_CTRL_REG" type="pcicfg" bus="0" dev="0" fun="0" offset="0xD0" desc="Message Bus Control Register">
<field name="MESSAGE_WR_BYTE_ENABLES" bit="4" size="4" desc="Message write byte enable" />
<field name="MESSAGE_ADDRESS_OFFSET" bit="8" size="8" desc="Message register address" />
<field name="MESSAGE_PORT" bit="16" size="8" desc="Message port" />
<field name="MESSAGE_OPCODE" bit="24" size="8" desc="Message opcode" />
</register>
<register name="MSG_DATA_REG" type="pcicfg" bus="0" dev="0" fun="0" offset="0xD4" desc="Message Bus Data Register">
<field name="MESSAGE_DATA" bit="0" size="32" desc="Message data" />
</register>
<register name="MSG_CTRL_REG_EXT" type="pcicfg" bus="0" dev="0" fun="0" offset="0xD8" desc="Message Bus Control Register Extension">
<field name="MESSAGE_ADDRESS_OFFSET_EXT" bit="8" size="24" desc="Message register address extension" />
</register>
<!-- Graphics -->
<!-- Section 4.1.13 -->
<register name="PCI0.0.0_GGC" type="pcicfg" bus="0" dev="0x2" fun="0" offset="0x50" size="4" desc="GMCH Graphics Control">
<field name="GGCLOCK" bit="0" size="1" desc="GGC Lock"/>
<field name="VGA_DISABLE" bit="1" size="1" desc="VGA Disable"/>
<field name="GMS" bit="3" size="7" desc="Graphics Mode Select"/>
<field name="GGMS" bit="8" size="2" desc="GTT Graphics Memory Size"/>
<field name="VAMEN" bit="14" size="1" desc="Versatile Acceleration"/>
</register>
<!-- Section 4.1.14 -->
<register name="PCI0.0.0_BDSM" type="pcicfg" bus="0" dev="0x2" fun="0" offset="0x5C" size="4" desc="Base of Data Stolen Memory">
<field name="LOCK" bit="0" size="1" desc="BDSM Lock"/>
<field name="BDSM" bit="20" size="12" desc="GFx Base of Data Stolen Memory"/>
</register>
<!-- Section 4.1.16 -->
<register name="PCI0.0.0_BGSM" type="pcicfg" bus="0" dev="0x2" fun="0" offset="0x70" size="4" desc="Base of Graphics Stolen Memory">
<field name="LOCK" bit="0" size="1" desc="BGSM Lock"/>
<field name="BGSM" bit="20" size="12" desc="GFx Base of GTT Stolen Memory"/>
</register>
<!-- iLB LPC Bridge -->
<!-- Section 10.20 PCU -->
<register name="ABASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x40" size="4" desc="ACPI Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="Base" bit="7" size="9" desc="Base Address"/>
</register>
<register name="PBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x44" size="4" desc="PMC Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="9" size="23" desc="Base Address"/>
</register>
<register name="GBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x48" size="4" desc="GPIO Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="Base" bit="8" size="8" desc="Base Address"/>
</register>
<register name="IOBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x4C" size="4" desc="I/O Controller Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="14" size="18" desc="Base Address"/>
</register>
<register name="IBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x50" size="4" desc="ILB Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="9" size="23" desc="Base Address"/>
</register>
<register name="SBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x54" size="4" desc="SPI Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="9" size="23" desc="Base Address"/>
</register>
<register name="MPBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x58" size="4" desc="MPHY Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="20" size="12" desc="Base Address"/>
</register>
<register name="PUBASE" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0x5C" size="4" desc="PUnit Base Address">
<field name="MEMI" bit="0" size="1" desc="Memory Space Indication"/>
<field name="Enable" bit="1" size="1" desc="Enable"/>
<field name="ADDRNG" bit="2" size="1" desc="Address Range"/>
<field name="PREF" bit="3" size="1" desc="Prefetchable"/>
<field name="Base" bit="11" size="21" desc="Base Address"/>
</register>
<register name="BIOS_DECODE_EN" type="pcicfg" bus="0" dev="0x1F" fun="0" offset="0xD8" size="2" desc="BIOS Decode Enable">
<field name="E40" bit="0" size="1" desc="40-4F Enable"/>
<field name="E50" bit="1" size="1" desc="50-5F Enable"/>
<field name="E60" bit="2" size="1" desc="60-6F Enable"/>
<field name="E70" bit="3" size="1" desc="70-7F Enable"/>
<field name="LEE" bit="6" size="1" desc="Legacy E Segment Enable"/>
<field name="LFE" bit="7" size="1" desc="Legacy F Segment Enable"/>
<field name="EC0" bit="8" size="1" desc="C0-C8 Enable"/>
<field name="EC8" bit="9" size="1" desc="C8-CF Enable"/>
<field name="ED0" bit="10" size="1" desc="D0-D8 Enable"/>
<field name="ED8" bit="11" size="1" desc="D8-DF Enable"/>
<field name="EE0" bit="12" size="1" desc="E0-E8 Enable"/>
<field name="EE8" bit="13" size="1" desc="E8-EF Enable"/>
<field name="EF0" bit="14" size="1" desc="F0-F8 Enable"/>
<field name="EF8" bit="15" size="1" desc="F8-FF Enable"/>
</register>
<!-- Section 10.12.1 -->
<register name="GCS" type="mmio" bar="RCBA" offset="0x0" size="4" desc="General Control and Status">
<field name="BILD" bit="0" size="1" desc="BIOS Interface Lock Down"/>
<field name="TS" bit="1" size="1" desc="Top Swap"/>
<field name="BBS" bit="10" size="2" desc="Boot BIOS Straps"/>
<field name="BBSize" bit="29" size="2" desc="Boot Block Size"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- MMIO registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Section 10.9.48 -->
<register name="BC" type="mmio" bar="SPIBAR" offset="0xFC" size="4" desc="BIOS Control Register (BCR)">
<field name="BIOSWE" bit="0" size="1" desc="BIOS Write Enable"/>
<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable"/>
<field name="SRC" bit="2" size="2" desc="SPI Read Configuration"/>
<field name="SMM_BWP" bit="5" size="1" desc="SMM BIOS Write Protect"/>
</register>
<!-- PMBASE MMIO registers -->
<!-- Section 10.2.9 -->
<register name="GEN_PMCON2" type="mmio" bar="PMBASE" offset="0x24" size="4" desc="General PM Configuration 2">
<field name="PER_SMI_SEL" bit="0" size="2" desc="Period SMI Select"/>
<field name="SMI_LOCK" bit="4" size="1" desc="SMI Lock"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- I/O registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- ABASE I/O registers -->
<!-- Section 10.17.6 -->
<register name="SMI_EN" type="iobar" bar="ABASE" offset="0x30" size="4" desc="SMI Control and Enable">
<field name="GBL_SMI_EN" bit="0" size="1"/>
<field name="EOS" bit="1" size="1"/>
<field name="BIOS_EN" bit="2" size="1"/>
<field name="SLP_SMI_EN" bit="4" size="1"/>
<field name="APMC_EN" bit="5" size="1"/>
<field name="SWSMI_TMR_EN" bit="6" size="1"/>
<field name="BIOS_RLS" bit="7" size="1"/>
<field name="TCO_EN" bit="13" size="1"/>
<field name="PERIODIC_EN" bit="14" size="1"/>
<field name="USB_SMI_EN" bit="17" size="1"/>
<field name="USB_IS_SMI_EN" bit="18" size="1"/>
</register>
<!-- Section 10.17.14 -->
<register name="TCO1_CNT" type="iobar" bar="ABASE" offset="0x68" size="4" desc="TCO Timer Control">
<field name="TCO_TMR_HALT" bit="11" size="1" desc="TCO Timre Halt"/>
<field name="TCO_LOCK" bit="12" size="1" desc="TCO Lock" />
<field name="OS_POLICY" bit="20" size="2" desc="OS Policy" />
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- CPU MSRs -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Message Bus registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- B-unit -->
<register name="BECREG" type="msgbus" port="0x3" offset="0x27" size="4" desc="Extended Configuration Space Base" >
<field name="ECENABLE" bit="0" size="1" desc="EC Enable"/>
<field name="ECBASE" bit="28" size="4" desc="EC Boundary"/>
</register>
</registers>
<!-- #################################### -->
<!-- -->
<!-- 'Controls' -->
<!-- -->
<!-- #################################### -->
<controls>
<control name="TopSwapStatus" register="GCS" field="TS" desc="Top Swap Status"/>
<control name="TopSwap" register="GCS" field="TS" desc="Top Swap"/>
<control name="BiosInterfaceLockDown" register="GCS" field="BILD" desc="BIOS Interface Lock-Down"/>
<control name="SMILock" register="GEN_PMCON2" field="SMI_LOCK" desc="SMI Global Configuration Lock"/>
</controls>
</configuration>
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