mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Sushmith Hiremath
0849635b15
- Bug fixes in spi_util Signed-off-by: Sushmith Hiremath <sushmith.m.hiremath@intel.com>
191 lines
8.2 KiB
Python
191 lines
8.2 KiB
Python
#!/usr/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2019, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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# -------------------------------------------------------------------------------
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#
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# CHIPSEC: Platform Hardware Security Assessment Framework
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# (c) 2010 - 2019 Intel Corporation
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#
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# -------------------------------------------------------------------------------
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#
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import struct
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from collections import namedtuple
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from chipsec.defines import *
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class Cfg:
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def __init__(self):
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self.CONFIG_PCI = {}
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self.REGISTERS = {}
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self.MMIO_BARS = {}
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self.IO_BARS = {}
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self.MEMORY_RANGES = {}
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self.CONTROLS = {}
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self.BUS = {}
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self.XML_CONFIG_LOADED = False
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#pass
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##############################################################################
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# CPU common configuration
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##############################################################################
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# ----------------------------------------------------------------------------
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# Device 0 MMIO BARs
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# ----------------------------------------------------------------------------
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PCI_MCHBAR_REG_OFF = 0x48
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PCI_PCIEXBAR_REG_OFF = 0x60
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PCI_PCIEXBAR_REG_LENGTH_MASK = (0x3 << 1)
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PCI_PCIEXBAR_REG_LENGTH_256MB = 0x0
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PCI_PCIEXBAR_REG_LENGTH_128MB = 0x1
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PCI_PCIEXBAR_REG_LENGTH_64MB = 0x2
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PCI_PCIEXBAR_REG_ADMSK64 = (1 << 26)
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PCI_PCIEXBAR_REG_ADMSK128 = (1 << 27)
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PCI_PCIEXBAR_REG_ADMSK256 = 0xF0000000
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PCI_DMIBAR_REG_OFF = 0x68
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# ----------------------------------------------------------------------------
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# Device 2 (Processor Graphics/Display) MMIO BARs
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# ----------------------------------------------------------------------------
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PCI_GTTMMADR_REG_OFF = 0x10
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PCI_GMADR_REG_OFF = 0x18
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# ----------------------------------------------------------------------------
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# HD Audio device configuration
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# ----------------------------------------------------------------------------
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PCI_HDA_DEV = 0x3
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PCI_HDA_MMC_REG_OFF = 0x62
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PCI_HDA_MMAL_REG_OFF = 0x64
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PCI_HDA_MMAH_REG_OFF = 0x68
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PCI_HDA_MMD_REG_OFF = 0x6C
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PCI_HDAUDIOBAR_REG_OFF = 0x10
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# ----------------------------------------------------------------------------
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# CPU MSRs
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# ----------------------------------------------------------------------------
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MTRR_MEMTYPE_UC = 0x0
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MTRR_MEMTYPE_WC = 0x1
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MTRR_MEMTYPE_WT = 0x4
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MTRR_MEMTYPE_WP = 0x5
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MTRR_MEMTYPE_WB = 0x6
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MemType = {
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MTRR_MEMTYPE_UC: 'Uncacheable (UC)',
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MTRR_MEMTYPE_WB: 'Write Combining (WC)',
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MTRR_MEMTYPE_WT: 'Write-through (WT)',
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MTRR_MEMTYPE_WP: 'Write-protected (WP)',
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MTRR_MEMTYPE_WB: 'Writeback (WB)'
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}
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IA32_MSR_CORE_THREAD_COUNT = 0x35
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IA32_MSR_CORE_THREAD_COUNT_THREADCOUNT_MASK = 0xFFFF
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IA32_MSR_CORE_THREAD_COUNT_CORECOUNT_MASK = 0xFFFF0000
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##############################################################################
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# PCH common configuration
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##############################################################################
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#----------------------------------------------------------------------------
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# SPI Host Interface Registers
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#----------------------------------------------------------------------------
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PCH_RCBA_SPI_HSFSTS_SCIP = BIT5 # SPI cycle in progress
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PCH_RCBA_SPI_HSFSTS_BERASE_MASK = (BIT4 | BIT3) # Block/Sector Erase Size
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PCH_RCBA_SPI_HSFSTS_BERASE_256B = 0x00 # Block/Sector = 256 Bytes
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PCH_RCBA_SPI_HSFSTS_BERASE_4K = 0x01 # Block/Sector = 4K Bytes
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PCH_RCBA_SPI_HSFSTS_BERASE_8K = 0x10 # Block/Sector = 8K Bytes
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PCH_RCBA_SPI_HSFSTS_BERASE_64K = 0x11 # Block/Sector = 64K Bytes
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PCH_RCBA_SPI_HSFSTS_AEL = BIT2 # Access Error Log
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PCH_RCBA_SPI_HSFSTS_FCERR = BIT1 # Flash Cycle Error
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PCH_RCBA_SPI_HSFSTS_FDONE = BIT0 # Flash Cycle Done
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PCH_RCBA_SPI_HSFCTL_FCYCLE_MASK = 0x0006 # Flash Cycle
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PCH_RCBA_SPI_HSFCTL_FCYCLE_READ = 0 # Flash Cycle Read
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PCH_RCBA_SPI_HSFCTL_FCYCLE_WRITE = 2 # Flash Cycle Write
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PCH_RCBA_SPI_HSFCTL_FCYCLE_ERASE = 3 # Flash Cycle Block Erase
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PCH_RCBA_SPI_HSFCTL_FCYCLE_JEDEC = 6 # Flash Cycle Read JEDEC ID
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PCH_RCBA_SPI_HSFCTL_FCYCLE_SFDP = 5 # Flash Cycle SFDP
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PCH_RCBA_SPI_HSFCTL_FCYCLE_FGO = BIT0 # Flash Cycle GO
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#PCH_RCBA_SPI_FADDR = 0x08 # SPI Flash Address
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PCH_RCBA_SPI_FADDR_MASK = 0x07FFFFFF # SPI Flash Address Mask [0:26]
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PCH_RCBA_SPI_FREGx_LIMIT_MASK = 0x7FFF0000 # Size
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PCH_RCBA_SPI_FREGx_BASE_MASK = 0x00007FFF # Base
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# Protected Range Registers
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PCH_RCBA_SPI_PR0_WPE = BIT31 # Write Protection Enable
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PCH_RCBA_SPI_PR0_PRL_MASK = 0x7FFF0000 # Protected Range Limit Mask
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PCH_RCBA_SPI_PR0_RPE = BIT15 # Read Protection Enable
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PCH_RCBA_SPI_PR0_PRB_MASK = 0x00007FFF # Protected Range Base Mask
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PCH_RCBA_SPI_OPTYPE_RDNOADDR = 0x00
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PCH_RCBA_SPI_OPTYPE_WRNOADDR = 0x01
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PCH_RCBA_SPI_OPTYPE_RDADDR = 0x02
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PCH_RCBA_SPI_OPTYPE_WRADDR = 0x03
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PCH_RCBA_SPI_FDOC_FDSS_FSDM = 0x0000 # Flash Signature and Descriptor Map
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PCH_RCBA_SPI_FDOC_FDSS_COMP = 0x1000 # Component
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PCH_RCBA_SPI_FDOC_FDSS_REGN = 0x2000 # Region
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PCH_RCBA_SPI_FDOC_FDSS_MSTR = 0x3000 # Master
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PCH_RCBA_SPI_FDOC_FDSI_MASK = 0x0FFC # Flash Descriptor Section Index
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# ----------------------------------------------------------------------------
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# PCI 0/31/0: PCH LPC Root Complex
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# ----------------------------------------------------------------------------
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PCI_B0D31F0_LPC_DEV = 31
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PCI_B0D31F0_LPC_FUN = 0
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CFG_REG_PCH_LPC_PMBASE = 0x40 # ACPI I/O Base (PMBASE/ABASE)
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LPC_RCBA_REG_OFFSET = 0xF0
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RCBA_BASE_ADDR_SHIFT = 14
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# ----------------------------------------------------------------------------
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# SPI Controller MMIO
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# ----------------------------------------------------------------------------
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SPI_MMIO_BUS = 0
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SPI_MMIO_DEV = PCI_B0D31F0_LPC_DEV
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SPI_MMIO_FUN = PCI_B0D31F0_LPC_FUN
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SPI_MMIO_REG_OFFSET = 0xF0
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SPI_BASE_ADDR_SHIFT = 14
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SPI_MMIO_BASE_OFFSET = 0x3800 # Base address of the SPI host interface registers off of RCBA
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SPI_MMIO_BASE_LENGTH = 0x200
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#SPI_MMIO_BASE_OFFSET = 0x3020 # Old (ICH8 and older) SPI registers base
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SPI_BIOS_CONTROL_OFFSET = 0xDC # BIOS Control Register
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CFG_REG_PCH_SMB_HCFG_HST_EN = BIT0 # SMBus Host Enable
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# ----------------------------------------------------------------------------
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# PCH I/O Base Registers
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# ----------------------------------------------------------------------------
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TCOBASE_ABASE_OFFSET = 0x60
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