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chipsec-chipsec/chipsec/cfg/common.xml
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Sushmith Hiremath 0849635b15 - SFDP module to parse JDEC parameter table 
- Bug fixes in spi_util

Signed-off-by: Sushmith Hiremath <sushmith.m.hiremath@intel.com>
2020-02-05 23:55:30 -08:00

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<?xml version="1.0"?>
<configuration>
<!--
Common (default) XML platform configuration file
-->
<!-- #################################### -->
<!-- -->
<!-- Integrated devices -->
<!-- -->
<!-- #################################### -->
<pci>
<device name="HOSTCTRL" bus="0" dev="0x00" fun="0" vid="0x8086" />
<device name="PEG10" bus="0" dev="0x01" fun="0" vid="0x8086" />
<device name="PEG11" bus="0" dev="0x01" fun="1" vid="0x8086" />
<device name="PEG12" bus="0" dev="0x01" fun="2" vid="0x8086" />
<device name="IGD" bus="0" dev="0x02" fun="0" vid="0x8086" />
<device name="HDAUDIO" bus="0" dev="0x03" fun="0" vid="0x8086" />
<device name="XHCI" bus="0" dev="0x14" fun="0" vid="0x8086" />
<device name="MEI1" bus="0" dev="0x16" fun="0" vid="0x8086" />
<device name="MEI2" bus="0" dev="0x16" fun="1" vid="0x8086" />
<device name="IDER" bus="0" dev="0x16" fun="2" vid="0x8086" />
<device name="KT" bus="0" dev="0x16" fun="3" vid="0x8086" />
<device name="GBE" bus="0" dev="0x19" fun="0" vid="0x8086" />
<device name="EHCI2" bus="0" dev="0x1A" fun="0" vid="0x8086" />
<device name="AUDIO" bus="0" dev="0x1B" fun="0" vid="0x8086" />
<device name="PCIE1" bus="0" dev="0x1C" fun="0" vid="0x8086" />
<device name="PCIE2" bus="0" dev="0x1C" fun="1" vid="0x8086" />
<device name="PCIE3" bus="0" dev="0x1C" fun="2" vid="0x8086" />
<device name="PCIE4" bus="0" dev="0x1C" fun="3" vid="0x8086" />
<device name="PCIE5" bus="0" dev="0x1C" fun="4" vid="0x8086" />
<device name="PCIE6" bus="0" dev="0x1C" fun="5" vid="0x8086" />
<device name="PCIE7" bus="0" dev="0x1C" fun="6" vid="0x8086" />
<device name="PCIE8" bus="0" dev="0x1C" fun="7" vid="0x8086" />
<device name="EHCI1" bus="0" dev="0x1D" fun="0" vid="0x8086" />
<device name="LPC" bus="0" dev="0x1F" fun="0" vid="0x8086" />
<device name="SATA1" bus="0" dev="0x1F" fun="2" vid="0x8086" />
<device name="SMBUS" bus="0" dev="0x1F" fun="3" vid="0x8086" />
<device name="SATA2" bus="0" dev="0x1F" fun="5" vid="0x8086" />
<device name="THERMAL" bus="0" dev="0x1F" fun="6" vid="0x8086" />
</pci>
<!-- #################################### -->
<!-- -->
<!-- Memory Mapped I/O spaces (MMIO BARs) -->
<!-- -->
<!-- #################################### -->
<mmio>
<bar name="PXPEPBAR" bus="0" dev="0" fun="0" reg="0x40" width="8" mask="0x7FFFFFF000" size="0x1000" enable_bit="0" desc="PCI Express Egress Port Register Range"/>
<bar name="MCHBAR" bus="0" dev="0" fun="0" reg="0x48" width="8" mask="0x7FFFFF8000" size="0x8000" enable_bit="0" desc="Host Memory Mapped Register Range"/>
<bar name="MMCFG" bus="0" dev="0" fun="0" reg="0x60" width="8" mask="0x7FFFFFF000" size="0x1000" enable_bit="0" desc="PCI Express Register Range"/>
<bar name="DMIBAR" bus="0" dev="0" fun="0" reg="0x68" width="8" mask="0x7FFFFFF000" size="0x1000" enable_bit="0" desc="Root Complex Register Range"/>
<bar name="GTTMMADR" bus="0" dev="2" fun="0" reg="0x10" width="8" mask="0x7FFFC00000" desc="Graphics Translation Table Range"/>
<bar name="GMADR" bus="0" dev="2" fun="0" reg="0x18" width="8" mask="0x7FF8000000" desc="Graphics Memory Range"/>
<bar name="HDABAR" bus="0" dev="3" fun="0" reg="0x10" width="8" mask="0x7FFFFFF000" size="0x1000" desc="HD Audio Controller Register Range"/>
<bar name="HDBAR" bus="0" dev="0x1B" fun="0" reg="0x10" width="8" mask="0x7FFFFFC000" size="0x1000" desc="PCH HD Audio Controller Register Range"/>
<bar name="RCBA" bus="0" dev="0x1F" fun="0" reg="0xF0" width="4" mask="0xFFFFC000" size="0x4000" enable_bit="0" desc="PCH Root Complex Register Range"/>
<bar name="SPIBAR" bus="0" dev="0x1F" fun="0" reg="0xF0" width="4" mask="0xFFFFC000" size="0x200" enable_bit="0" desc="SPI Controller Register Range" offset="0x3800"/>
<!-- TODO
<bar name="SPIBAR" parent="RCBA" offset="0x3800" desc="SPI Controller Register Range"/>
-->
<bar name="RCBA_RTC" bus="0" dev="0x1F" fun="0" reg="0xF0" width="4" mask="0xFFFFC000" size="0x200" enable_bit="0" desc="General Control Register Range" offset="0x3400"/>
<!-- VT-d BARs -->
<bar name="VTBAR" register="VTBAR" base_field="Base" size="0x1000" enable_field="Enable" desc="Intel VT-d Register Register Range"/>
<bar name="GFXVTBAR" register="GFXVTBAR" base_field="Base" size="0x1000" enable_field="Enable" desc="Intel Processor Graphics VT-d Register Range"/>
</mmio>
<!-- #################################### -->
<!-- -->
<!-- I/O spaces (I/O BARs) -->
<!-- -->
<!-- #################################### -->
<io>
<bar name="ABASE" register="ABASE" base_field="Base" size="0x80" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="Base" size="0x80" desc="ACPI Base Address"/>
<bar name="TCOBASE" register="ABASE" base_field="Base" size="0x80" desc="TCO Base Address" offset="0x60"/>
<bar name="GPIOBASE" register="GPIOBASE" base_field="Base" size="0x80" desc="GPIO Base Address"/>
<bar name="SMBUS_BASE" register="SMB_BASE" base_field="Base" size="0x20" desc="SMBus Base Address"/>
</io>
<!-- #################################### -->
<!-- -->
<!-- Memory ranges -->
<!-- -->
<!-- #################################### -->
<memory>
<range name="Legacy DOS" access="dram" address="0x0" size="0x100000"/>
<range name="TPM" access="mmio" address="0xFED40000" size="0x10000"/>
</memory>
<!-- #################################### -->
<!-- -->
<!-- Configuration registers -->
<!-- -->
<!-- #################################### -->
<registers>
<!-- PCIe Configuration (CFG) Registers -->
<!-- Host Controller -->
<register name="PCI0.0.0_VID" type="pcicfg" device="HOSTCTRL" offset="0x0" size="2" desc="Vendor ID"/>
<register name="PCI0.0.0_DID" type="pcicfg" device="HOSTCTRL" offset="0x2" size="2" desc="Device ID"/>
<register name="PCI0.0.0_PXPEPBAR" type="pcicfg" device="HOSTCTRL" offset="0x40" size="8" desc="PCI Express Egress Port Base Address"/>
<register name="PCI0.0.0_MCHBAR" type="pcicfg" device="HOSTCTRL" offset="0x48" size="8" desc="MCH Base Address"/>
<register name="PCI0.0.0_GGC" type="pcicfg" device="HOSTCTRL" offset="0x50" size="2" desc="Graphics Control">
<field name="GGCLOCK" bit="0" size="1" desc="GGC Lock"/>
</register>
<register name="PCI0.0.0_DEVEN" type="pcicfg" device="HOSTCTRL" offset="0x54" size="4" desc="Device Enables"/>
<register name="PCI0.0.0_PAVPC" type="pcicfg" device="HOSTCTRL" offset="0x58" size="4" desc="PAVP Configuration">
<field name="PAVPLCK" bit="2" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_DPR" type="pcicfg" device="HOSTCTRL" offset="0x5C" size="4" desc="DMA Protected Range">
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_PCIEXBAR" type="pcicfg" device="HOSTCTRL" offset="0x60" size="8" desc="PCIe MMCFG Base Address"/>
<register name="PCI0.0.0_DMIBAR" type="pcicfg" device="HOSTCTRL" offset="0x68" size="8" desc="DMI Base Address"/>
<register name="PCI0.0.0_MESEG_BASE" type="pcicfg" device="HOSTCTRL" offset="0x70" size="8" desc="Manageability Engine Base Address Register"/>
<register name="PCI0.0.0_MESEG_MASK" type="pcicfg" device="HOSTCTRL" offset="0x78" size="8" desc="Manageability Engine Limit Address Register">
<field name="MELCK" bit="10" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_PAM0" type="pcicfg" device="HOSTCTRL" offset="0x80" size="1" desc="Programmable Attribute Map 0"/>
<register name="PCI0.0.0_PAM1" type="pcicfg" device="HOSTCTRL" offset="0x81" size="1" desc="Programmable Attribute Map 1"/>
<register name="PCI0.0.0_PAM2" type="pcicfg" device="HOSTCTRL" offset="0x82" size="1" desc="Programmable Attribute Map 2"/>
<register name="PCI0.0.0_PAM3" type="pcicfg" device="HOSTCTRL" offset="0x83" size="1" desc="Programmable Attribute Map 3"/>
<register name="PCI0.0.0_PAM4" type="pcicfg" device="HOSTCTRL" offset="0x84" size="1" desc="Programmable Attribute Map 4"/>
<register name="PCI0.0.0_PAM5" type="pcicfg" device="HOSTCTRL" offset="0x85" size="1" desc="Programmable Attribute Map 5"/>
<register name="PCI0.0.0_PAM6" type="pcicfg" device="HOSTCTRL" offset="0x86" size="1" desc="Programmable Attribute Map 6"/>
<register name="PCI0.0.0_LAC" type="pcicfg" device="HOSTCTRL" offset="0x87" size="1" desc="Legacy Access Control"/>
<register name="PCI0.0.0_SMRAMC" type="pcicfg" device="HOSTCTRL" offset="0x88" size="1" desc="System Management RAM Control">
<field name="D_OPEN" bit="6" size="1" desc="SMRAM Open"/>
<field name="D_CLS" bit="5" size="1" desc="SMRAM Closed"/>
<field name="D_LCK" bit="4" size="1" desc="SMRAM Locked"/>
<field name="G_SMRAME" bit="3" size="1" desc="SMRAM Enabled"/>
<field name="C_BASE_SEG" bit="0" size="3" desc="SMRAM Base Segment = 010b"/>
</register>
<register name="PCI0.0.0_REMAPBASE" type="pcicfg" device="HOSTCTRL" offset="0x90" size="8" desc="Memory Remap Base Address">
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_REMAPLIMIT" type="pcicfg" device="HOSTCTRL" offset="0x98" size="8" desc="Memory Remap Limit Address">
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_TOM" type="pcicfg" device="HOSTCTRL" offset="0xA0" size="8" desc="Top of Memory">
<field name="TOM" bit="20" size="19" desc="Top of Memory"/>
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_TOUUD" type="pcicfg" device="HOSTCTRL" offset="0xA8" size="8" desc="Top of Upper Usable DRAM">
<field name="TOUUD" bit="20" size="19" desc="Top of Upper Usable DRAM"/>
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_BDSM" type="pcicfg" device="HOSTCTRL" offset="0xB0" size="4" desc="Base of Graphics Stolen Memory">
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_BGSM" type="pcicfg" device="HOSTCTRL" offset="0xB4" size="4" desc="Base of GTT Stolen Memory">
<field name="BGSM" bit="20" size="12" desc="Base of GTT Stolen Memory"/>
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_TSEGMB" type="pcicfg" device="HOSTCTRL" offset="0xB8" size="4" desc="TSEG Memory Base">
<field name="TSEGMB" bit="20" size="12" desc="TSEG Memory Base"/>
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_TOLUD" type="pcicfg" device="HOSTCTRL" offset="0xBC" size="4" desc="Top of Low Usable DRAM">
<field name="TOLUD" bit="20" size="12" desc="Top of Lower Usable DRAM"/>
<field name="LOCK" bit="0" size="1" desc="Lock"/>
</register>
<register name="PCI0.0.0_SKPD" type="pcicfg" device="HOSTCTRL" offset="0xDC" size="4" desc="Scratchpad Data"/>
<register name="PCI0.0.0_CAPID0_A" type="pcicfg" device="HOSTCTRL" offset="0xE4" size="4" desc="Capabilities A"/>
<register name="PCI0.0.0_CAPID0_B" type="pcicfg" device="HOSTCTRL" offset="0xE8" size="4" desc="Capabilities B"/>
<!-- IGD registers -->
<register name="PCI0.2.0_DID" type="pcicfg" device="IGD" offset="2" size="2" desc="Device Identification Number">
</register>
<!-- LPC Interface Bridge -->
<register name="ABASE" type="pcicfg" device="LPC" offset="0x40" size="4" desc="ACPI Base Address">
<field name="Base" bit="7" size="9" desc="Base Address"/>
</register>
<register name="GPIOBASE" type="pcicfg" device="LPC" offset="0x48" size="4" desc="GPIO Base Address">
<field name="Base" bit="7" size="9" desc="Base Address"/>
</register>
<register name="GC" type="pcicfg" device="LPC" offset="0x4C" size="1" desc="GPIO Control">
<field name="GLE" bit="0" size="1" desc="GPIO Lockdown Enable" />
<field name="EN" bit="4" size="1" desc="GPIO Enable" />
</register>
<register name="GEN_PMCON_1" type="pcicfg" device="LPC" offset="0xA0" size="2" desc="General PM Configuration 1">
<field name="SMI_LOCK" bit="4" size="1"/>
</register>
<register name="BC" type="pcicfg" device="LPC" offset="0xDC" size="1" desc="BIOS Control">
<field name="BIOSWE" bit="0" size="1" desc="BIOS Write Enable"/>
<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable"/>
<field name="SRC" bit="2" size="2" desc="SPI Read Configuration"/>
<field name="TSS" bit="4" size="1" desc="Top Swap Status"/>
<field name="SMM_BWP" bit="5" size="1" desc="SMM BIOS Write Protection"/>
</register>
<!-- SMBus Host Controller -->
<register name="SMBUS_VID" type="pcicfg" device="SMBUS" offset="0x00" size="2" desc="VID" />
<register name="SMBUS_DID" type="pcicfg" device="SMBUS" offset="0x02" size="2" desc="DID" />
<register name="SMBUS_CMD" type="pcicfg" device="SMBUS" offset="0x04" size="2" desc="CMD" />
<register name="SMB_BASE" type="pcicfg" device="SMBUS" offset="0x20" size="4" desc="SMBus Base Address">
<field name="Base" bit="5" size="11" desc="Base Address"/>
</register>
<register name="SMBUS_HCFG" type="pcicfg" device="SMBUS" offset="0x40" size="1" desc="Host Configuration">
<field name="HST_EN" bit="0" size="1"/>
<field name="SMB_SMI_EN" bit="1" size="1"/>
<field name="I2C_EN" bit="2" size="2"/>
<field name="SSRESET" bit="3" size="1"/>
<field name="SPD_WD" bit="4" size="1"/>
</register>
<!-- ME Host Firmware Status https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/{pch,me}.h -->
<register name="HFS" type="pcicfg" bus="0" dev="0x16" fun="0" offset="0x40" size="4" desc="ME Host Firmware Status">
<field name="MFG_MODE" bit="4" size="1" desc="ME Manufacturing Mode" />
<field name="FW_INIT_COMPLETE" bit="9" size="1" desc="ME Firmware Initialization Complete" />
<field name="UPDATE_IN_PROGRESS" bit="11" size="1" desc="ME Update In Progress" />
</register>
<!-- Memory-Mapped I/O (MMIO) Registers -->
<!-- SPI Flash Controller -->
<register name="BFPR" type="mmio" bar="SPIBAR" offset="0x00" size="4" desc="BIOS Flash Primary Region Register (= FREG1)">
<field name="PRB" bit="0" size="13" desc="BIOS Flash Primary Region Base"/>
<field name="PRL" bit="16" size="13" desc="BIOS Flash Primary Region Limit"/>
</register>
<register name="HSFS" type="mmio" bar="SPIBAR" offset="0x04" size="2" desc="Hardware Sequencing Flash Status Register">
<field name="FDONE" bit="0" size="1" desc="Flash Cycle Done"/>
<field name="FCERR" bit="1" size="1" desc="Flash Cycle Error"/>
<field name="AEL" bit="2" size="1" desc="Access Error Log"/>
<field name="BERASE" bit="3" size="2" desc="Block/Sector Erase Size"/>
<field name="SCIP" bit="5" size="1" desc="SPI cycle in progress"/>
<field name="FDOPSS" bit="13" size="1" desc="Flash Descriptor Override Pin-Strap Status"/>
<field name="FDV" bit="14" size="1" desc="Flash Descriptor Valid"/>
<field name="FLOCKDN" bit="15" size="1" desc="Flash Configuration Lock-Down"/>
</register>
<register name="HSFC" type="mmio" bar="SPIBAR" offset="0x06" size="2" desc="Hardware Sequencing Flash Control Register">
<field name="FGO" bit="0" size="1" desc="Flash Cycle GO"/>
<field name="FCYCLE" bit="1" size="2" desc="Flash Cycle"/>
<field name="FDBC" bit="8" size="6" desc="Flash Data Byte Count, Count = FDBC + 1"/>
<field name="FSMIE" bit="15" size="1" desc="Flash SPI SMI Enable"/>
</register>
<register name="FADDR" type="mmio" bar="SPIBAR" offset="0x08" size="4" desc="Flash Address Register"/>
<register name="FDATA0" type="mmio" bar="SPIBAR" offset="0x10" size="4" desc="Flash Data 0"/>
<register name="FDATA1" type="mmio" bar="SPIBAR" offset="0x14" size="4" desc="Flash Data 1"/>
<register name="FDATA2" type="mmio" bar="SPIBAR" offset="0x18" size="4" desc="Flash Data 2"/>
<register name="FDATA3" type="mmio" bar="SPIBAR" offset="0x1C" size="4" desc="Flash Data 3"/>
<register name="FDATA4" type="mmio" bar="SPIBAR" offset="0x20" size="4" desc="Flash Data 4"/>
<register name="FDATA5" type="mmio" bar="SPIBAR" offset="0x24" size="4" desc="Flash Data 5"/>
<register name="FDATA6" type="mmio" bar="SPIBAR" offset="0x28" size="4" desc="Flash Data 6"/>
<register name="FDATA7" type="mmio" bar="SPIBAR" offset="0x2C" size="4" desc="Flash Data 7"/>
<register name="FDATA8" type="mmio" bar="SPIBAR" offset="0x30" size="4" desc="Flash Data 8"/>
<register name="FDATA9" type="mmio" bar="SPIBAR" offset="0x34" size="4" desc="Flash Data 9"/>
<register name="FDATA10" type="mmio" bar="SPIBAR" offset="0x38" size="4" desc="Flash Data 10"/>
<register name="FDATA11" type="mmio" bar="SPIBAR" offset="0x3C" size="4" desc="Flash Data 11"/>
<register name="FDATA12" type="mmio" bar="SPIBAR" offset="0x40" size="4" desc="Flash Data 12"/>
<register name="FDATA13" type="mmio" bar="SPIBAR" offset="0x44" size="4" desc="Flash Data 13"/>
<register name="FDATA14" type="mmio" bar="SPIBAR" offset="0x48" size="4" desc="Flash Data 14"/>
<register name="FDATA15" type="mmio" bar="SPIBAR" offset="0x4C" size="4" desc="Flash Data 15"/>
<register name="FRAP" type="mmio" bar="SPIBAR" offset="0x50" size="4" desc="SPI Flash Regions Access Permissions Register">
<field name="BRRA" bit="0" size="8" desc="BIOS Region Read Access"/>
<field name="BRWA" bit="8" size="8" desc="BIOS Region Write Access"/>
<field name="BMRAG" bit="16" size="8" desc="BIOS Master Read Access Grant"/>
<field name="BMWAG" bit="24" size="8" desc="BIOS Master Write Access Grant"/>
</register>
<register name="FREG0_FLASHD" type="mmio" bar="SPIBAR" offset="0x54" size="4" desc="Flash Region 0 (Flash Descriptor)">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG1_BIOS" type="mmio" bar="SPIBAR" offset="0x58" size="4" desc="Flash Region 1 (BIOS)">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG2_ME" type="mmio" bar="SPIBAR" offset="0x5C" size="4" desc="Flash Region 2 (ME)">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG3_GBE" type="mmio" bar="SPIBAR" offset="0x60" size="4" desc="Flash Region 3 (GBe)">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG4_PD" type="mmio" bar="SPIBAR" offset="0x64" size="4" desc="Flash Region 4 (Platform Data)">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG5" type="mmio" bar="SPIBAR" offset="0x68" size="4" desc="Flash Region 5">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="FREG6" type="mmio" bar="SPIBAR" offset="0x6C" size="4" desc="Flash Region 6">
<field name="RB" bit="0" size="12" desc="Region Base"/>
<field name="RL" bit="16" size="12" desc="Region Limit"/>
</register>
<register name="PR0" type="mmio" bar="SPIBAR" offset="0x74" size="4" desc="Protected Range 0">
<field name="PRB" bit="0" size="13" desc="Protected Range Base"/>
<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
<field name="PRL" bit="16" size="13" desc="Protected Range Limit"/>
<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
</register>
<register name="PR1" type="mmio" bar="SPIBAR" offset="0x78" size="4" desc="Protected Range 1">
<field name="PRB" bit="0" size="13" desc="Protected Range Base"/>
<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
<field name="PRL" bit="16" size="13" desc="Protected Range Limit"/>
<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
</register>
<register name="PR2" type="mmio" bar="SPIBAR" offset="0x7C" size="4" desc="Protected Range 2">
<field name="PRB" bit="0" size="13" desc="Protected Range Base"/>
<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
<field name="PRL" bit="16" size="13" desc="Protected Range Limit"/>
<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
</register>
<register name="PR3" type="mmio" bar="SPIBAR" offset="0x80" size="4" desc="Protected Range 3">
<field name="PRB" bit="0" size="13" desc="Protected Range Base"/>
<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
<field name="PRL" bit="16" size="13" desc="Protected Range Limit"/>
<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
</register>
<register name="PR4" type="mmio" bar="SPIBAR" offset="0x84" size="4" desc="Protected Range 4">
<field name="PRB" bit="0" size="13" desc="Protected Range Base"/>
<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
<field name="PRL" bit="16" size="13" desc="Protected Range Limit"/>
<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
</register>
<register name="PREOP" type="mmio" bar="SPIBAR" offset="0x94" size="2" desc="Prefix Opcode Configuration Register">
<field name="PREOP0" bit="0" size="8" desc="Prefix Opcode 0"/>
<field name="PREOP1" bit="8" size="8" desc="Prefix Opcode 1"/>
</register>
<register name="OPTYPE" type="mmio" bar="SPIBAR" offset="0x96" size="2" desc="Opcode Type Configuration Register">
<field name="OPTYPE0" bit="0" size="2" desc="Opcode Type 0"/>
<field name="OPTYPE1" bit="2" size="2" desc="Opcode Type 1"/>
<field name="OPTYPE2" bit="4" size="2" desc="Opcode Type 2"/>
<field name="OPTYPE3" bit="6" size="2" desc="Opcode Type 3"/>
<field name="OPTYPE4" bit="8" size="2" desc="Opcode Type 4"/>
<field name="OPTYPE5" bit="10" size="2" desc="Opcode Type 5"/>
<field name="OPTYPE6" bit="12" size="2" desc="Opcode Type 6"/>
<field name="OPTYPE7" bit="14" size="2" desc="Opcode Type 7"/>
</register>
<register name="OPMENU" type="mmio" bar="SPIBAR" offset="0x98" size="8" desc="Opcode Menu Configuration Register">
<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
<field name="OPCODE4" bit="32" size="8" desc="Allowable Opcode 4"/>
<field name="OPCODE5" bit="40" size="8" desc="Allowable Opcode 5"/>
<field name="OPCODE6" bit="48" size="8" desc="Allowable Opcode 6"/>
<field name="OPCODE7" bit="56" size="8" desc="Allowable Opcode 7"/>
</register>
<register name="OPMENU_LO" type="mmio" bar="SPIBAR" offset="0x98" size="4" desc="Opcode Menu Configuration Register Low">
<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
</register>
<register name="OPMENU_HI" type="mmio" bar="SPIBAR" offset="0x9C" size="4" desc="Opcode Menu Configuration Register High">
<field name="OPCODE4" bit="0" size="8" desc="Allowable Opcode 4"/>
<field name="OPCODE5" bit="8" size="8" desc="Allowable Opcode 5"/>
<field name="OPCODE6" bit="16" size="8" desc="Allowable Opcode 6"/>
<field name="OPCODE7" bit="24" size="8" desc="Allowable Opcode 7"/>
</register>
<register name="FDOC" type="mmio" bar="SPIBAR" offset="0xB0" size="4" desc="Flash Descriptor Observability Control Register">
<field name="FDSI" bit="2" size="10" desc="Flash Descriptor Section Index"/>
<field name="FDSS" bit="12" size="3" desc="Flash Descriptor Section Select"/>
</register>
<register name="FDOD" type="mmio" bar="SPIBAR" offset="0xB4" size="4" desc="Flash Descriptor Observability Data Register">
<field name="FDSD" bit="0" size="32" desc="Flash Descriptor Section Data"/>
</register>
<register name="LVSCC" type="mmio" bar="SPIBAR" offset="0xC4" size="4" desc="Host Lower Vendor Specific Component Capabilities">
<field name="LBES" bit="0" size="2" desc="Lower Block/Sector Erase Size"/>
<field name="LWG" bit="2" size="1" desc="Lower Write Granularity"/>
<field name="LWSR" bit="3" size="1" desc="Lower Write Status Required"/>
<field name="LWEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="LEO" bit="8" size="8" desc="Lower Erase Opcode"/>
<field name="VCL" bit="23" size="1" desc="Vendor Component Lock"/>
</register>
<register name="UVSCC" type="mmio" bar="SPIBAR" offset="0xC8" size="4" desc="Host Upper Vendor Specific Component Capabilities">
<field name="UBES" bit="0" size="2" desc="Upper Block/Sector Erase Size"/>
<field name="UWG" bit="2" size="1" desc="Upper Write Granularity"/>
<field name="UWSR" bit="3" size="1" desc="Upper Write Status Required"/>
<field name="UWEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="UEO" bit="8" size="8" desc="Upper Erase Opcode"/>
</register>
<register name="BIOS_PTINX" type="mmio" bar="SPIBAR" offset="0xCC" size="4" desc="Parameter Table Index"/>
<register name="BIOS_PTDATA" type="mmio" bar="SPIBAR" offset="0xD0" size="4" desc="Parameter Table Data"/>
<!-- SPI Flash Descriptor registers -->
<register name="FLMAP0" type="mmio" bar="FDBAR" offset="0x14" size="4" desc="Flash Map 0 Register">
<field name="FCBA" bit="0" size="8" desc="Flash Component Base Address"/>
<field name="NC" bit="8" size="2" desc="Number of Components"/>
<field name="FRBA" bit="16" size="8" desc="Flash Region Base Address"/>
<field name="NR" bit="24" size="3" desc="Number of Regions"/>
</register>
<register name="FLMAP1" type="mmio" bar="FDBAR" offset="0x18" size="4" desc="Flash Map 1 Register">
<field name="FMBA" bit="0" size="8" desc="Flash Master Base Address"/>
<field name="NM" bit="8" size="2" desc="Number of Masters"/>
<field name="FPSBA" bit="16" size="8" desc="Flash PCH Strap Base Address"/>
<field name="PSL" bit="24" size="8" desc="PCH Strap Length"/>
</register>
<register name="FLMAP2" type="mmio" bar="FDBAR" offset="0x1C" size="4" desc="Flash Map 2 Register">
<field name="FCPUSBA" bit="0" size="8" desc="Flash CPU Strap Base Address"/>
<field name="CPUSL" bit="8" size="8" desc="Processor Strap Length"/>
<field name="ICCRIBA" bit="16" size="8" desc="ICC Register Init Base Address"/>
</register>
<register name="FLREG0" type="mmio" bar="FRBA" offset="0x0" size="4" desc="Flash Region 0 (Flash Descriptor) Register">
<field name="RB" bit="0" size="13" desc="Region Base"/>
<field name="RL" bit="16" size="13" desc="Region Limit"/>
</register>
<register name="FLREG1" type="mmio" bar="FRBA" offset="0x4" size="4" desc="Flash Region 1 (BIOS) Register">
<field name="RB" bit="0" size="13" desc="Region Base"/>
<field name="RL" bit="16" size="13" desc="Region Limit"/>
</register>
<register name="FLREG2" type="mmio" bar="FRBA" offset="0x8" size="4" desc="Flash Region 2 (Intel ME) Register">
<field name="RB" bit="0" size="13" desc="Region Base"/>
<field name="RL" bit="16" size="13" desc="Region Limit"/>
</register>
<register name="FLREG3" type="mmio" bar="FRBA" offset="0xC" size="4" desc="Flash Region 3 (GBe) Register">
<field name="RB" bit="0" size="13" desc="Region Base"/>
<field name="RL" bit="16" size="13" desc="Region Limit"/>
</register>
<register name="FLREG4" type="mmio" bar="FRBA" offset="0x10" size="4" desc="Flash Region 4 (Platform Data) Register">
<field name="RB" bit="0" size="13" desc="Region Base"/>
<field name="RL" bit="16" size="13" desc="Region Limit"/>
</register>
<register name="FLMSTR1" type="mmio" bar="FMBA" offset="0x0" size="4" desc="Flash Master 1">
<field name="MRRA" bit="16" size="8" desc="Master Region Read Access"/>
<field name="MRWA" bit="24" size="8" desc="Master Region Write Access"/>
</register>
<!-- PCH Root Complex Register Base -->
<register name="RC" type="mmio" bar="RCBA" offset="0x3400" size="4" desc="RTC Configuration">
<field name="UE" bit="2" size="1" desc="Upper 128 Byte Enable"/>
<field name="LL" bit="3" size="1" desc="Lower 128 Byte Lock"/>
<field name="UL" bit="4" size="1" desc="Upper 128 Byte Lock"/>
</register>
<register name="GCS" type="mmio" bar="RCBA" offset="0x3410" size="4" desc="General Control and Status">
<field name="BILD" bit="0" size="1" desc="BIOS Interface Lock Down"/>
<field name="BBS" bit="10" size="2" desc="Boot BIOS Straps"/>
</register>
<register name="BUC" type="mmio" bar="RCBA" offset="0x3414" size="4" desc="Backed Up Control">
<field name="TS" bit="0" size="1" desc="Top Swap"/>
</register>
<!-- MCHBAR -->
<!-- Sections 7.40 - 7.41 6th Generation Intel Processor Datasheet -->
<register name="GFXVTBAR" type="mmio" bar="MCHBAR" offset="0x5400" size="8" desc="Processor Graphics VT-d MMIO Base Address">
<field name="Enable" bit="0" size="1" desc="Enable"/>
<field name="Base" bit="12" size="27" desc="GFX VTD Base Address"/>
</register>
<register name="VTBAR" type="mmio" bar="MCHBAR" offset="0x5410" size="8" desc="VT-d MMIO Base Address">
<field name="Enable" bit="0" size="1" desc="Enable"/>
<field name="Base" bit="12" size="27" desc="VTD Base Address"/>
</register>
<!-- Port I/O Registers -->
<register name="RST_CNT" type="io" port="0xCF9" size="1" desc="Reset Control">
<field name="SYS_RST" bit="1" size="1" desc="System Reset"/>
<field name="RST_CPU" bit="2" size="1" desc="Reset Processor"/>
<field name="FULL_RST" bit="3" size="1" desc="Full Reset"/>
</register>
<!-- PCH ABASE (PMBASE) -->
<register name="PM1_STS" type="iobar" bar="ABASE" offset="0x0" size="2" desc="PM1 Status">
<field name="WAK_STS" bit="15" size="1" desc="Wake Status"/>
<field name="PCIEXPWAK_STS" bit="14" size="1" desc="PCI Express Wake Status"/>
<field name="PWRBTNOR_STS" bit="11" size="1" desc="Power Button Override Status"/>
<field name="RTC_STS" bit="10" size="1" desc="RTC Status"/>
<field name="PWRBTN_STS" bit="8" size="1" desc="Power Button Status"/>
<field name="GBL_STS" bit="5" size="1" desc="Global Status"/>
<field name="BM_STS" bit="4" size="1" desc="Bus Master Status"/>
<field name="TMROF_STS" bit="0" size="1" desc="Timer Overflow Status"/>
</register>
<register name="PM1_EN" type="iobar" bar="ABASE" offset="0x2" size="2" desc="PM1 Enable">
<field name="PCIEXPWAK_DIS" bit="14" size="1" desc="PCI Express Wake Disable"/>
<field name="RTC_EN" bit="10" size="1" desc="RTC Event Enable"/>
<field name="PWRBTN_EN" bit="8" size="1" desc="Power Button Enable"/>
<field name="GBL_EN" bit="5" size="1" desc="Global Enable"/>
<field name="TMROF_EN" bit="0" size="1" desc="Timer Overflow Interrupt Enable"/>
</register>
<register name="PM1_CNT" type="iobar" bar="ABASE" offset="0x4" size="4" desc="PM1 Control">
<field name="SLP_EN" bit="13" size="1" desc="Sleep Enable"/>
<field name="SLP_TYP" bit="10" size="3" desc="Sleep Type"/>
<field name="GBL_RLS" bit="2" size="1" desc="Global Release"/>
<field name="BM_RLD" bit="1" size="1" desc="Bus Master Reload"/>
<field name="SCI_EN" bit="0" size="1" desc="SCI Enable"/>
</register>
<register name="PM1_TMR" type="iobar" bar="ABASE" offset="0x8" size="4" desc="PM1 Timer">
<field name="TMR_VAL" bit="0" size="24" desc="Timer Value"/>
</register>
<register name="SMI_EN" type="iobar" bar="ABASE" offset="0x30" size="4" desc="SMI Control and Enable">
<field name="GBL_SMI_EN" bit="0" size="1"/>
<field name="EOS" bit="1" size="1"/>
<field name="BIOS_EN" bit="2" size="1"/>
<field name="LEGACY_USB_EN" bit="3" size="1"/>
<field name="SLP_SMI_EN" bit="4" size="1"/>
<field name="APMC_EN" bit="5" size="1"/>
<field name="SWSMI_TMR_EN" bit="6" size="1"/>
<field name="BIOS_RLS" bit="7" size="1"/>
<field name="MCSMI_EN" bit="11" size="1"/>
<field name="TCO_EN" bit="13" size="1"/>
<field name="PERIODIC_EN" bit="14" size="1"/>
<field name="LEGACY_USB2_EN" bit="17" size="1"/>
<field name="INTEL_USB2_EN" bit="18" size="1"/>
<field name="GPIO_UNLOCK_SMI_EN" bit="27" size="1"/>
<field name="ME_SMI_EN" bit="30" size="1"/>
<field name="xHCI_SMI_EN" bit="31" size="1"/>
</register>
<register name="TCO1_CNT" type="iobar" bar="ABASE" offset="0x68" size="2" desc="TCO1 Control">
<field name="TCO_LOCK" bit="12" size="1"/>
</register>
<!-- SMBUS BASE -->
<register name="SMBUS_HST_STS" type="iobar" bar="SMBUS_BASE" offset="0x00" size="1" desc="SMBus Host Status">
<field name="BUSY" bit="0" size="1" desc="SMBus Busy" />
<field name="INTR" bit="1" size="1" desc="Interrupt" />
<field name="DEV_ERR" bit="2" size="1" desc="Device Error" />
<field name="BUS_ERR" bit="3" size="1" desc="Bus Error" />
<field name="FAILED" bit="4" size="1" desc="SMBus Error/Failed" />
<field name="SMBALERT_STS" bit="5" size="1" desc="SMBALERT# Signal Status" />
<field name="INUSE_STS" bit="6" size="1" desc="InUse Semaphore Status" />
<field name="DS" bit="7" size="1" desc="Done Status" />
</register>
<register name="SMBUS_HST_CNT" type="iobar" bar="SMBUS_BASE" offset="0x02" size="1" desc="SMBus Host Control">
<field name="INTREN" bit="0" size="1" desc="Interrupt Enable" />
<field name="KILL" bit="1" size="1" desc="Kill" />
<field name="SMB_CMD" bit="2" size="3" desc="Command" />
<field name="LAST_BYTE" bit="5" size="1" desc="Last Byte (for Block Read commands)" />
<field name="START" bit="6" size="1" desc="Start/Trigger" />
<field name="PEC_EN" bit="7" size="1" desc="Packet Error Checking Enable" />
</register>
<register name="SMBUS_HST_CMD" type="iobar" bar="SMBUS_BASE" offset="0x03" size="1" desc="SMBus Host Command">
<field name="DataOffset" bit="0" size="8" desc="Command Data" />
</register>
<register name="SMBUS_HST_SLVA" type="iobar" bar="SMBUS_BASE" offset="0x04" size="1" desc="SMBus Host Slave Address">
<field name="RW" bit="0" size="1" desc="Read/Write Command" />
<field name="Address" bit="1" size="7" desc="Slave Address" />
</register>
<register name="SMBUS_HST_D0" type="iobar" bar="SMBUS_BASE" offset="0x05" size="1" desc="SMBus Host Data 0">
<field name="Data" bit="0" size="8" desc="Data0/Count" />
</register>
<register name="SMBUS_HST_D1" type="iobar" bar="SMBUS_BASE" offset="0x06" size="1" desc="SMBus Host Data 1">
<field name="Data" bit="0" size="8" desc="Data1" />
</register>
<!-- CPU Model Specific Registers (MSR) -->
<register name="IA32_BIOS_SIGN_ID" type="msr" msr="0x8B" desc="Microcode Update Signature Register">
<field name="Microcode" bit="32" size="32" desc="Microcode update signature" />
</register>
<register name="IA32_SMRR_PHYSBASE" type="msr" msr="0x1F2" desc="SMRR Base Address MSR">
<field name="Type" bit="0" size="8" desc="SMRR memory type" />
<field name="PhysBase" bit="12" size="20" desc="SMRR physical base address" />
</register>
<register name="IA32_SMRR_PHYSMASK" type="msr" msr="0x1F3" desc="SMRR Range Mask MSR">
<field name="Valid" bit="11" size="1" desc="SMRR valid" />
<field name="PhysMask" bit="12" size="20" desc="SMRR address range mask" />
</register>
<register name="MTRRCAP" type="msr" msr="0xFE" desc="MTRR Capabilities MSR">
<field name="Fixed_Range_MTRR" bit="8" size="1" desc="Fixed range MTRRs Supported" />
<field name="WC" bit="10" size="1" desc="WC Supported" />
<field name="SMRR" bit="11" size="1" desc="SMRR Supported" />
<field name="PRMRR" bit="12" size="1" desc="PRMRR Supported" />
</register>
<register name="IA32_FEATURE_CONTROL" type="msr" msr="0x3A" desc="Processor Feature Control">
<field name="LOCK" bit="0" size="1" desc="Lock" />
<field name="EN_VMX_INSIDE_SMX" bit="1" size="1" desc="Enable VMX inside SMX operation" />
<field name="EN_VMX_OUTSIDE_SMX" bit="2" size="1" desc="Enable VMX outside SMX operation" />
<field name="Reserved0" bit="3" size="5" desc="Reserved" />
<field name="SENTER_LOCAL_EN" bit="8" size="7" desc="SENTER Local Functions Enable" />
<field name="SENTER_GLOBAL_EN" bit="15" size="1" desc="SENTER Global Enable" />
<field name="Reserved1" bit="16" size="1" desc="Reserved" />
<field name="SGX_LAUNCH_CTRL_EN" bit="17" size="1" desc="SGX Launch Control Enable" />
<field name="SGX_GLOBAL_EN" bit="18" size="1" desc="SGX Global Enable" />
<field name="Reserved2" bit="19" size="1" desc="Reserved" />
<field name="LMCE_ON" bit="20" size="1" desc="Turn Local Machine Check On" />
</register>
<register name="IA32_APIC_BASE" type="msr" msr="0x1B" desc="Local APIC Base">
<field name="BSP" bit="8" size="1" desc="Bootstrap Processor" />
<field name="x2APICEn" bit="10" size="1" desc="Enable x2APIC mode" />
<field name="En" bit="11" size="1" desc="APIC Global Enable" />
<field name="APICBase" bit="12" size="20" desc="APIC Base" />
</register>
<register name="MSR_SMI_COUNT" type="msr" msr="0x34" desc="SMI Count">
<field name="Count" bit="0" size="64" />
</register>
<register name="IA32_ARCH_CAPABILITIES" type="msr" msr="0x10A" desc="Architectural Capabilities MSR">
<field name="RDCL_NO" bit="0" size="1" desc="Processor is not susceptible to RDCL (Rogue Data Cache Load)" />
<field name="IBRS_ALL" bit="1" size="1" desc="Processor supports enhanced Indirect Branch Restricted Speculation (IBRS)" />
</register>
<register name="IA32_SPEC_CTRL" type="msr" msr="0x48" desc="Speculation Control MSR">
<field name="IBRS" bit="0" size="1" desc="Enable Indirect Branch Restricted Speculation (IBRS)" />
<field name="STIBP" bit="1" size="1" desc="Enable Single Thread Indirect Branch Predictors (STIBP)" />
<field name="SSBD" bit="2" size="1" desc="Delays speculative execution of load until the addr for all older stores are known" />
</register>
<register name="IA32_PRED_CMD" type="msr" msr="0x49" desc="Prediction Command MSR">
<field name="IBPB" bit="0" size="1" desc="IBPB Command" />
</register>
<register name="MSR_LT_LOCK_MEMORY" type="msr" msr="0x2E7" desc="LT lock memory configuration MSR">
<field name="LT_LOCK" bit="0" size="1" desc="Lock bit" />
</register>
<register name="IA32_DEBUG_INTERFACE" type="msr" msr="0xC80" desc="Silicon Debug Feature Control">
<field name="ENABLE" bit="0" size="1" desc="Enable" />
<field name="LOCK" bit="30" size="1" desc="Lock (set automatically on the first SMI)" />
<field name="DEBUG_OCCURRED" bit="31" size="1" desc="Debug Occurred (set by hardware)" />
</register>
<!-- SGX related Model Specific Registers (MSR) -->
<!-- Check if CPUID(EAX=7,ECX=0):EBX[2] is set before accessing these registers-->
<register name="BIOS_SE_SVN" type="msr" msr="0x302" desc="BIOS SGX SVN values">
<field name="PFAT_SE_SVN" bit="40" size="8" desc="PFAT_SE_SVN" />
<field name="ANC_SE_SVN" bit="32" size="8" desc="ANC_SE_SVN" />
<field name="SCLEAN_SE_SVN" bit="24" size="8" desc="SCLEAN_SE_SVN" />
<field name="SINIT_SE_SVN" bit="16" size="8" desc="SINIT_SE_SVN" />
</register>
<register name="BIOS_SE_SVN_STATUS" type="msr" msr="0x500" desc="BIOS SGX SVN status register">
<field name="LOCK" bit="0" size="1" desc="ACM threshold locked" />
<field name="SINIT_SE_SVN" bit="16" size="8" desc="SINIT_SE_SVN" />
</register>
<register name="PRMRR_VALID_CONFIG" type="msr" msr="0x1FB" desc="PRMRR VALID register">
<field name="PRMRR_SIZE_SUPPORT" bit="5" size="4" desc="PRMRR size support"/>
</register>
<register name="PRMRR_PHYBASE" type="msr" msr="0x1F4" desc="PRMRR BASE Address">
<field name="PRMRR_MEMTYPE" bit="0" size="3" desc="PRMRR Memory Type" />
<field name="PRMRR_base_address_fields" bit="12" size="34" desc="PRMRR base address bits" />
</register>
<register name="PRMRR_MASK" type="msr" msr="0x1F5" desc="PRMRR MASK register">
<field name= "PRMRR_LOCK" bit="10" size="1" desc = "PRMRR Lock Bit" />
<field name= "PRMRR_VLD" bit="11" size="1" desc = "PRMRR Valid Bit set by mcheck" />
<field name="PRMRR_mask_bits" bit="12" size="34" desc="PRMRR mask bits" />
</register>
<register name="PRMRR_UNCORE_PHYBASE" type="msr" msr="0x2F4" desc="PRMRR uncore BASE Address">
<field name="PRMRR_base_address_fields" bit="12" size="27" desc="PRMRR uncore base address bits" />
</register>
<register name="PRMRR_UNCORE_MASK" type="msr" msr="0x2F5" desc="PRMRR uncore MASK register">
<field name= "PRMRR_LOCK" bit="10" size="1" desc = "PRMRR uncore Lock Bit" />
<field name= "PRMRR_VLD" bit="11" size="1" desc = "PRMRR uncore Valid Bit set by mcheck" />
<field name="PRMRR_mask_bits" bit="12" size="27" desc="PRMRR uncore mask bits" />
</register>
<register name="SGX_DEBUG_MODE" type="msr" msr="0x503" desc="SGX debug mode resiter">
<field name="SGX_DEBUG_MODE_STATUS_BIT" bit="1" size="1" desc="Debug mode status but"/>
</register>
</registers>
<!-- #################################### -->
<!-- -->
<!-- 'Controls' -->
<!-- -->
<!-- #################################### -->
<controls>
<control name="SmmBiosWriteProtection" register="BC" field="SMM_BWP" desc="SMM BIOS Write Protection"/>
<control name="BiosLockEnable" register="BC" field="BLE" desc="BIOS Lock Enable"/>
<control name="BiosWriteEnable" register="BC" field="BIOSWE" desc="BIOS Write Enable"/>
<control name="TopSwapStatus" register="BC" field="TSS" desc="Top Swap Status"/>
<control name="TopSwap" register="BUC" field="TS" desc="Top Swap"/>
<control name="FlashLockDown" register="HSFS" field="FLOCKDN" desc="Flash Configuration Lock-Down"/>
<control name="BiosInterfaceLockDown" register="GCS" field="BILD" desc="BIOS Interface Lock-Down"/>
<control name="GlobalSMIEnable" register="SMI_EN" field="GBL_SMI_EN" desc="Global SMI Enable"/>
<control name="GPIOSMIEnable" register="SMI_EN" field="GPIO_UNLOCK_SMI_EN" desc="GPIO Config SMI Enable"/>
<control name="SMILock" register="GEN_PMCON_1" field="SMI_LOCK" desc="SMI Global Configuration Lock"/>
<control name="TCOSMIEnable" register="SMI_EN" field="TCO_EN" desc="TCO SMI Enable"/>
<control name="TCOSMILock" register="TCO1_CNT" field="TCO_LOCK" desc="TCO SMI Lock"/>
<control name="SMRAMDLock" register="PCI0.0.0_SMRAMC" field="D_LCK" desc="SMRAM D_LCK"/>
<control name="TSEGBaseLock" register="PCI0.0.0_TSEGMB" field="LOCK" desc="TSEG Base Lock"/>
<control name="TSEGLimitLock" register="PCI0.0.0_BGSM" field="LOCK" desc="TSEG Limit Lock"/>
<control name="Ia32FeatureControlLock" register="IA32_FEATURE_CONTROL" field="LOCK" desc="Lock IA32 Feature Control"/>
</controls>
</configuration>
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