mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
BrentHoltsclaw
192 lines
12 KiB
XML
192 lines
12 KiB
XML
<?xml version="1.0"?>
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<configuration platform="DNV" >
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<!--
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XML configuration file for Denverton
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* Intel Atom(R) Processor C3000 Product Family
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https://www.intel.com/content/www/us/en/processors/atom/atom-technical-resources.html
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337018-002
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-->
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<pci>
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</pci>
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<mmio>
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<bar name="SPIBAR" bus="0" dev="0x1F" fun="5" reg="0x10" width="4" mask="0xFFFFC000" size="0x200" desc="SPI Controller Register Range"/>
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</mmio>
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<io>
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<bar name="ABASE" register="ABASE" base_field="Base" size="0x100" desc="ACPI Base Address"/>
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<bar name="TCOBASE" register="TCOBASE" base_field="Base" size="0x20" desc="TCO Base Address"/>
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</io>
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<memory>
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</memory>
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<registers>
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<register name="P2SBC" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0xE0" size="4" desc="P2SB Control">
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<field name="MASKLOCK" bit="17" size="12" desc="Base address"/>
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</register>
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<register name="SMBUS_HCFG" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x40" size="1" desc="Host Configuration">
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<field name="SPD_WD" bit="4" size="1" desc="SPD Write Disable"/>
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</register>
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<register name="SMI_EN" type="iobar" bar="ABASE" offset="0x30" size="4" desc="SMI Control and Enable">
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<field name="GBL_SMI_EN" bit="0" size="1"/>
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<field name="TCO_EN" bit="13" size="1"/>
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</register>
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<register name="TCO1_CNT" type="iobar" bar="TCOBASE" offset="0x8" size="4" desc="SMI Control and Enable">
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<field name="TCO_LOCK" bit="12" size="1"/>
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</register>
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<register name="BC" type="pcicfg" bus="0" dev="0x1F" fun="5" offset="0xDC" size="1" desc="BIOS Control">
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<field name="BIOSWE" bit="0" size="1" desc="Write Protect Disable"/>
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<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable"/>
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<field name="SRC" bit="2" size="2" desc="SPI Read Configuration"/>
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<field name="TSS" bit="4" size="1" desc="Top Swap Status"/>
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<field name="SMM_BWP" bit="5" size="1" desc="Enable InSMM.STS"/>
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<field name="BILD" bit="7" size="1" desc="BIOS Interface Lock-Down"/>
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</register>
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<register name="ABASE" type="pcicfg" bus="0" dev="0x1F" fun="2" offset="0x40" size="4" desc="ACPI Base Address">
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<field name="Base" bit="8" size="24" desc="Base Address"/>
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</register>
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<register name="TCOBASE" type="pcicfg" bus="0" dev="0x1F" fun="4" offset="0x50" size="4" desc="TCO Base Address">
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<field name="Base" bit="5" size="11" desc="Base Address"/>
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</register>
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<!-- SPI Flash Controller MMIO registers -->
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<register name="HSFS" type="mmio" bar="SPIBAR" offset="0x04" size="4" desc="Hardware Sequencing Flash Status Register">
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<field name="SCIP" bit="5" size="1" desc="SPI cycle in progress"/>
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<field name="WRSDIS" bit="11" size="1" desc="Write status disable"/>
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<field name="PR34LKD" bit="12" size="1" desc="PRR3 PRR4 Lock-Down"/>
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<field name="FDOPSS" bit="13" size="1" desc="Flash Descriptor Override Pin-Strap Status"/>
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<field name="FDV" bit="14" size="1" desc="Flash Descriptor Valid"/>
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<field name="FLOCKDN" bit="15" size="1" desc="Flash Configuration Lock-Down"/>
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<field name="FGO" bit="16" size="1" desc="Flash cycle go"/>
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<field name="FCYCLE" bit="17" size="4" desc="Flash Cycle Type"/>
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<field name="WET" bit="21" size="1" desc="Write Enable Type"/>
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<field name="FDBC" bit="24" size="6" desc="Flash Data Byte Count"/>
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<field name="FSMIE" bit="31" size="1" desc="Flash SPI SMI Enable"/>
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</register>
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<register name="PR0" type="mmio" bar="SPIBAR" offset="0x84" size="4" desc="Protected Range 0">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="PR1" type="mmio" bar="SPIBAR" offset="0x88" size="4" desc="Protected Range 1">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="PR2" type="mmio" bar="SPIBAR" offset="0x8C" size="4" desc="Protected Range 2">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="PR3" type="mmio" bar="SPIBAR" offset="0x90" size="4" desc="Protected Range 3">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="PR4" type="mmio" bar="SPIBAR" offset="0x94" size="4" desc="Protected Range 4">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="GPR0" type="mmio" bar="SPIBAR" offset="0x98" size="4" desc="Global Protected Range 0">
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<field name="PRB" bit="0" size="15" desc="Protected Range Base"/>
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<field name="RPE" bit="15" size="1" desc="Read Protection Enabled"/>
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<field name="PRL" bit="16" size="15" desc="Protected Range Limit"/>
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<field name="WPE" bit="31" size="1" desc="Write Protection Enabled"/>
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</register>
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<register name="PREOP" type="mmio" bar="SPIBAR" offset="0xA4" size="2" desc="Prefix Opcode Configuration Register">
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<field name="PREOP0" bit="0" size="8" desc="Prefix Opcode 0"/>
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<field name="PREOP1" bit="8" size="8" desc="Prefix Opcode 1"/>
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</register>
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<register name="OPTYPE" type="mmio" bar="SPIBAR" offset="0xA4" size="4" desc="Opcode Type Configuration Register">
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<field name="PREFIX0" bit="0" size="8" desc="Prefix Opcode 0"/>
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<field name="PREFIX1" bit="8" size="8" desc="Prefix Opcode 1"/>
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<field name="OPTYPE0" bit="16" size="2" desc="Opcode Type 0"/>
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<field name="OPTYPE1" bit="18" size="2" desc="Opcode Type 1"/>
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<field name="OPTYPE2" bit="20" size="2" desc="Opcode Type 2"/>
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<field name="OPTYPE3" bit="22" size="2" desc="Opcode Type 3"/>
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<field name="OPTYPE4" bit="24" size="2" desc="Opcode Type 4"/>
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<field name="OPTYPE5" bit="26" size="2" desc="Opcode Type 5"/>
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<field name="OPTYPE6" bit="28" size="2" desc="Opcode Type 6"/>
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<field name="OPTYPE7" bit="30" size="2" desc="Opcode Type 7"/>
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</register>
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<register name="OPMENU" type="mmio" bar="SPIBAR" offset="0xA8" size="8" desc="Opcode Menu Configuration Register">
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<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
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<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
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<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
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<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
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<field name="OPCODE4" bit="32" size="8" desc="Allowable Opcode 4"/>
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<field name="OPCODE5" bit="40" size="8" desc="Allowable Opcode 5"/>
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<field name="OPCODE6" bit="48" size="8" desc="Allowable Opcode 6"/>
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<field name="OPCODE7" bit="56" size="8" desc="Allowable Opcode 7"/>
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</register>
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<register name="OPMENU_LO" type="mmio" bar="SPIBAR" offset="0xA8" size="4" desc="Opcode Menu Configuration Register Low">
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<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
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<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
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<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
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<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
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</register>
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<register name="OPMENU_HI" type="mmio" bar="SPIBAR" offset="0xAC" size="4" desc="Opcode Menu Configuration Register High">
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<field name="OPCODE4" bit="0" size="8" desc="Allowable Opcode 4"/>
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<field name="OPCODE5" bit="8" size="8" desc="Allowable Opcode 5"/>
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<field name="OPCODE6" bit="16" size="8" desc="Allowable Opcode 6"/>
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<field name="OPCODE7" bit="24" size="8" desc="Allowable Opcode 7"/>
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</register>
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<register name="LVSCC" type="mmio" bar="SPIBAR" offset="0xC4" size="4" desc="Vendor Specific Component Capabilities for Component 0">
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<field name="LWG" bit="2" size="1" desc="Lower Write Granularity"/>
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<field name="LWSR" bit="3" size="1" desc="Lower Write Status Required"/>
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<field name="LWEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
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<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
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<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
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<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
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<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
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<field name="VCL" bit="30" size="1" desc="Vendor Component Lock"/>
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<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
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</register>
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<register name="UVSCC" type="mmio" bar="SPIBAR" offset="0xC8" size="4" desc="Vendor Specific Component Capabilities for Component 1">
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<field name="UWG" bit="2" size="1" desc="Upper Write Granularity"/>
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<field name="UWSR" bit="3" size="1" desc="Upper Write Status Required"/>
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<field name="UWEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
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<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
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<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
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<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
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<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
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<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
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</register>
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<!-- ME Host Firmware Status https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/{pch,me}.h -->
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<register name="HFS" type="pcicfg" bus="0" dev="0x18" fun="0" offset="0x40" size="4" desc="ME Host Firmware Status">
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<field name="MFG_MODE" bit="4" size="1" desc="ME Manufacturing Mode" />
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<field name="FW_INIT_COMPLETE" bit="9" size="1" desc="ME Firmware Initialization Complete" />
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<field name="UPDATE_IN_PROGRESS" bit="11" size="1" desc="ME Update In Progress" />
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</register>
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</registers>
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<controls>
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<control name="FlashLockDown" register="HSFS" field="FLOCKDN" desc="Flash Configuration Lock-Down"/>
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<control name="SpiWriteStatusDis" register="HSFS" field="WRSDIS" desc="Write Status Disable"/>
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<control name="SmmBiosWriteProtection" register="BC" field="SMM_BWP" desc="SMM BIOS Write Protection"/>
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<control name="BiosLockEnable" register="BC" field="BLE" desc="BIOS Lock Enable"/>
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<control name="BiosWriteEnable" register="BC" field="BIOSWE" desc="BIOS Write Enable"/>
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<control name="TopSwapStatus" register="BC" field="TSS" desc="Top Swap Status"/>
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<control name="BiosInterfaceLockDown" register="BC" field="BILD" desc="BIOS Interface Lock-Down"/>
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<control name="GlobalSMIEnable" register="SMI_EN" field="GBL_SMI_EN" desc="Global SMI Enable"/>
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<control name="TCOSMILock" register="TCO1_CNT" field="TCO_LOCK" desc="TCO SMI Lock"/>
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<control name="TCOSMIEnable" register="SMI_EN" field="TCO_EN" desc="TCO SMI Enable"/>
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</controls>
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</configuration>
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