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chipsec-chipsec/chipsec/cfg/glk.xml
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BrentHoltsclaw e7680eb3d2 Add GLK support 
Document ID: 336561-001

Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
2019-12-11 09:43:03 -08:00

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<?xml version="1.0"?>
<configuration platform="GLK">
<!-- XML configuration for GLK
Document ID: 336561-001
-->
<!-- #################################### -->
<!-- -->
<!-- Integrated devices -->
<!-- -->
<!-- #################################### -->
<pci>
<device name="P2SBC" bus="0" dev="0x0D" fun="0" vid="0x8086" />
<device name="MEI1" bus="0" dev="0x0F" fun="0" vid="0x8086" />
<device name="MEI2" bus="0" dev="0x0F" fun="1" vid="0x8086" />
<device name="MEI3" bus="0" dev="0x0F" fun="2" vid="0x8086" />
<device name="SMBUS" bus="0" dev="0x1F" fun="1" vid="0x8086" />
<device name="SPI" bus="0" dev="0x0D" fun="2" vid="0x8086" />
</pci>
<!-- #################################### -->
<!-- -->
<!-- Memory Mapped I/O spaces (MMIO BARs) -->
<!-- -->
<!-- #################################### -->
<mmio>
<bar name="SPIBAR" bus="0" dev="0xD" fun="0x2" reg="0x10" width="4" mask="0xFFFFFE00" size="0x200" enable_bit="1" desc="SPI Controller Register Range"/>
<bar name="GTTMMADR" bus="0" dev="0x02" fun="0" reg="0x10" width="8" mask="0x7FF000000" desc="Graphics Translation Table Range"/>
<bar name="PWRMBASE" register="PWRMBASE" base_field="BA" size="0x1000" desc="Power Management Register Range"/>
<bar name="SBREGBAR" register="SBREG_BAR" base_field="RBA" size="0x1000000" fixed_address="0xFD000000" desc="Sideband Register Access BAR"/>
</mmio>
<!-- #################################### -->
<!-- -->
<!-- I/O spaces (I/O BARs) -->
<!-- -->
<!-- #################################### -->
<io>
<bar name="TCOBASE" register="TCOBASE" base_field="TCOBA" size="0x20" desc="TCO Base Address"/>
<bar name="ABASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x400" desc="ACPI Base Address"/>
<bar name="PMBASE" register="ABASE" base_field="BA" size="0x100" fixed_address="0x400" desc="ACPI Base Address"/>
<bar name="SMBUS_BASE" bus="0" dev="0x1F" fun="1" reg="0x20" mask="0xFFE0" size="0x80" desc="SMBus Base Address"/>
</io>
<!-- #################################### -->
<!-- -->
<!-- Configuration registers -->
<!-- -->
<!-- #################################### -->
<registers>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- PCIe Configuration registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- Sideband Register Access Registers -->
<register name="SBREG_BAR" type="pcicfg" bus="0" dev="0xD" fun="0" offset="0x10" size="4" desc="Sideband Register Access BAR">
<field name="RBA" bit="24" size="8" desc="Register Base Address"/>
</register>
<register name="P2SBC" type="pcicfg" bus="0" dev="0xD" fun="0" offset="0xE0" size="2" desc="P2SB Configuration Register">
<field name="HIDE" bit="8" size="1" desc="Hide SBREG_BAR"/>
</register>
<register name="P2SB_HIDE" type="pcicfg" bus="0" dev="0xD" fun="0" offset="0xE1" size="1" desc="P2SB Configuration Register hide-unhide">
<field name="HIDE" bit="0" size="1" desc="Hide SBREG_BAR"/>
</register>
<!-- ME Host Firmware Status https://github.com/coreboot/coreboot/blob/master/src/southbridge/intel/*/{pch,me}.h -->
<register name="HFS" type="pcicfg" bus="0" dev="0x0F" fun="0" offset="0x40" size="4" desc="ME Host Firmware Status">
<field name="MFG_MODE" bit="4" size="1" desc="ME Manufacturing Mode" />
<field name="FW_INIT_COMPLETE" bit="9" size="1" desc="ME Firmware Initialization Complete" />
<field name="UPDATE_IN_PROGRESS" bit="11" size="1" desc="ME Update In Progress" />
</register>
<!-- GFx PCI device registers -->
<register name="PCI0.0.0_GGC" type="pcicfg" bus="0" dev="0" fun="0" offset="0x50" size="4" desc="GMCH Graphics Control">
<field name="GGCLCK" bit="0" size="1"/>
</register>
<register name="PCI0.0.0_BDSM" type="pcicfg" bus="0" dev="0" fun="0" offset="0xB0" size="4" desc="Base of Data Stolen Memory">
<field name="BDSM_LOCK" bit="0" size="1"/>
</register>
<register name="PCI0.0.0_BGSM" type="pcicfg" bus="0" dev="0" fun="0" offset="0xB4" size="4" desc="Base of Graphics Stolen Memory">
<field name="BGSM_LOCK" bit="0" size="1"/>
</register>
<register name="PCI0.0.0_PAVPC" type="pcicfg" bus="0" dev="0" fun="0" offset="0x58" size="4" desc="PAVP Control">
<field name="PAVPC_LOCK" bit="2" size="1"/>
</register>
<register name="PWRMBASE" type="pcicfg" bus="0" dev="0x0D" fun="1" offset="0x10" size="8" desc="PM Base Address"> <field name="STYPE" bit="2" size="1" desc="Space Type (if 0 - 32bit, 1 - 64bit)"/>
<field name="BA" bit="12" size="52" desc="Base Address"/>
</register>
<register name="ABASE" type="pcicfg" bus="0" dev="0x0D" fun="1" offset="0x20" size="2" desc="ACPI Base Address">
<field name="BA" bit="8" size="8" desc="Base Address"/>
</register>
<register name="RC" type="mm_msgbus" port="0xC3" offset="0x3400" size="4" desc="RTC Configuration">
<field name="UE" bit="2" size="1" desc="Upper 128 Byte Enable"/>
<field name="LL" bit="3" size="1" desc="Lower 128 Byte Lock"/>
<field name="UL" bit="4" size="1" desc="Upper 128 Byte Lock"/>
<field name="BILD" bit="31" size="1" desc="BIOS Interface Lock-Down"/>
</register>
<register name="BUC" type="mm_msgbus" port="0xC3" offset="0x3414" size="4" desc="Backed Up Control">
<field name="TS" bit="0" size="1" desc="Top Swap"/>
</register>
<!-- SMBus Host Controller -->
<register name="SMBUS_VID" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x00" size="2" desc="VID" />
<register name="SMBUS_DID" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x02" size="2" desc="DID" />
<register name="SMBUS_CMD" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x04" size="2" desc="CMD" />
<register name="SMBUS_HCFG" type="pcicfg" bus="0" dev="0x1F" fun="1" offset="0x40" size="1" desc="Host Configuration">
<field name="HST_EN" bit="0" size="1"/>
<field name="SMB_SMI_EN" bit="1" size="1"/>
<field name="I2C_EN" bit="2" size="2"/>
<field name="SSRESET" bit="3" size="1"/>
<field name="SPD_WD" bit="4" size="1"/>
</register>
<register name="TCOBASE" type="pcicfg" bus="0" dev="0x1f" fun="1" offset="0x50" size="4" desc="TCO Base Address">
<field name="IOS" bit="0" size="1" desc="I/O space"/>
<field name="TCOBA" bit="5" size="11" desc="TCO Base Address"/>
</register>
<register name="TCOCTL" type="pcicfg" bus="0" dev="0x1f" fun="1" offset="0x54" size="4" desc="TCO Control">
<field name="TCO_BASE_EN" bit="8" size="1" desc="TCO Base Enable"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- MMIO registers -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- SPI Flash Controller MMIO registers -->
<register name="BC" type="pcicfg" bus="0" dev="0xD" fun="0x2" offset="0xDC" size="4" desc="BIOS Control Register (BCR)">
<field name="BIOSWE" bit="0" size="1" desc="BIOS Write Enable"/>
<field name="BLE" bit="1" size="1" desc="BIOS Lock Enable"/>
<field name="SRC" bit="2" size="2" desc="SPI Read Configuration"/>
<field name="TS" bit="4" size="1" desc="BIOS Top Swap Mode"/>
<field name="SMM_BWP" bit="5" size="1" desc="SMM BIOS Write Protect"/>
<field name="BILD" bit="7" size="1" desc="BIOS Interface Lock-Down"/>
</register>
<register name="HSFS" type="mmio" bar="SPIBAR" offset="0x4" size="4" desc="HW sequencing flash status">
<field name="FDONE" bit="0" size="1" desc="Flash Cycle Done"/>
<field name="FCERR" bit="1" size="1" desc="Flash Cycle Error"/>
<field name="AEL" bit="2" size="1" desc="Access Error Log"/>
<field name="SCIP" bit="5" size="1" desc="SPI cycle in progress"/>
<field name="WRSDIS" bit="11" size="1" desc="Write status disable"/>
<field name="PR34LKD" bit="12" size="1" desc="PRR3 PRR4 Lock-Down"/>
<field name="FDOPSS" bit="13" size="1" desc="Flash Descriptor Override Pin-Strap Status"/>
<field name="FDV" bit="14" size="1" desc="Flash Descriptor Valid"/>
<field name="FLOCKDN" bit="15" size="1" desc="Flash Configuration Lock-Down"/>
<field name="FGO" bit="16" size="1" desc="Flash cycle go"/>
<field name="FCYCLE" bit="17" size="4" desc="Flash Cycle Type"/>
<field name="WET" bit="21" size="1" desc="Write Enable Type"/>
<field name="FDBC" bit="24" size="6" desc="Flash Data Byte Count"/>
<field name="FSMIE" bit="31" size="1" desc="Flash SPI SMI Enable"/>
</register>
<register name="LOCK" type="mmio" bar="SPIBAR" offset="0x0C" size="4" desc="Individual lock register">
<field name="BMWAG" bit="0" size="1"/>
<field name="BMRAG" bit="1" size="1"/>
<field name="SBMWAG" bit="2" size="1"/>
<field name="SBMRAG" bit="3" size="1"/>
<field name="PR0" bit="8" size="1"/>
<field name="PR1" bit="9" size="1"/>
<field name="PR2" bit="10" size="1"/>
<field name="PR3" bit="11" size="1"/>
<field name="PR4" bit="12" size="1"/>
<field name="SLD" bit="16" size="1"/>
</register>
<register name="PR0" type="mmio" bar="SPIBAR" offset="0x84" size="4" desc="Protected Range 0">
<field name="PRB" bit="0" size="15"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR1" type="mmio" bar="SPIBAR" offset="0x88" size="4" desc="Protected Range 1">
<field name="PRB" bit="0" size="15"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR2" type="mmio" bar="SPIBAR" offset="0x8C" size="4" desc="Protected Range 2">
<field name="PRB" bit="0" size="15"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR3" type="mmio" bar="SPIBAR" offset="0x90" size="4" desc="Protected Range 3">
<field name="PRB" bit="0" size="15"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PR4" type="mmio" bar="SPIBAR" offset="0x94" size="4" desc="Protected Range 4">
<field name="PRB" bit="0" size="15"/>
<field name="RPE" bit="15" size="1"/>
<field name="PRL" bit="16" size="15"/>
<field name="WPE" bit="31" size="1"/>
</register>
<register name="PREOP" type="mmio" bar="SPIBAR" offset="0xA4" size="2" desc="Prefix Opcode Configuration Register">
<field name="PREOP0" bit="0" size="8" desc="Prefix Opcode 0"/>
<field name="PREOP1" bit="8" size="8" desc="Prefix Opcode 1"/>
</register>
<register name="OPTYPE" type="mmio" bar="SPIBAR" offset="0xA6" size="2" desc="Opcode Type Configuration Register">
<field name="OPTYPE0" bit="0" size="2" desc="Opcode Type 0"/>
<field name="OPTYPE1" bit="2" size="2" desc="Opcode Type 1"/>
<field name="OPTYPE2" bit="4" size="2" desc="Opcode Type 2"/>
<field name="OPTYPE3" bit="6" size="2" desc="Opcode Type 3"/>
<field name="OPTYPE4" bit="8" size="2" desc="Opcode Type 4"/>
<field name="OPTYPE5" bit="10" size="2" desc="Opcode Type 5"/>
<field name="OPTYPE6" bit="12" size="2" desc="Opcode Type 6"/>
<field name="OPTYPE7" bit="14" size="2" desc="Opcode Type 7"/>
</register>
<register name="OPMENU" type="mmio" bar="SPIBAR" offset="0xA8" size="8" desc="Opcode Menu Configuration Register">
<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
<field name="OPCODE4" bit="32" size="8" desc="Allowable Opcode 4"/>
<field name="OPCODE5" bit="40" size="8" desc="Allowable Opcode 5"/>
<field name="OPCODE6" bit="48" size="8" desc="Allowable Opcode 6"/>
<field name="OPCODE7" bit="56" size="8" desc="Allowable Opcode 7"/>
</register>
<register name="OPMENU_LO" type="mmio" bar="SPIBAR" offset="0xA8" size="4" desc="Opcode Menu Configuration Register Low">
<field name="OPCODE0" bit="0" size="8" desc="Allowable Opcode 0"/>
<field name="OPCODE1" bit="8" size="8" desc="Allowable Opcode 1"/>
<field name="OPCODE2" bit="16" size="8" desc="Allowable Opcode 2"/>
<field name="OPCODE3" bit="24" size="8" desc="Allowable Opcode 3"/>
</register>
<register name="OPMENU_HI" type="mmio" bar="SPIBAR" offset="0xAC" size="4" desc="Opcode Menu Configuration Register High">
<field name="OPCODE4" bit="0" size="8" desc="Allowable Opcode 4"/>
<field name="OPCODE5" bit="8" size="8" desc="Allowable Opcode 5"/>
<field name="OPCODE6" bit="16" size="8" desc="Allowable Opcode 6"/>
<field name="OPCODE7" bit="24" size="8" desc="Allowable Opcode 7"/>
</register>
<register name="FDOC" type="mmio" bar="SPIBAR" offset="0xB4" size="4" desc="Flash Descriptor Observability Control Register">
<field name="FDSI" bit="2" size="10" desc="Flash Descriptor Section Index"/>
<field name="FDSS" bit="12" size="3" desc="Flash Descriptor Section Select"/>
</register>
<register name="FDOD" type="mmio" bar="SPIBAR" offset="0xB8" size="4" desc="Flash Descriptor Observability Data Register">
<field name="FDSD" bit="0" size="32" desc="Flash Descriptor Section Data"/>
</register>
<register name="LVSCC" type="mmio" bar="SPIBAR" offset="0xC4" size="4" desc="Vendor Specific Component Capabilities">
<field name="WG" bit="2" size="1" desc="Write Granularity"/>
<field name="WSR" bit="3" size="1" desc="Write Status Required"/>
<field name="WEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="QER" bit="5" size="3" desc="Quad Enable Requirements"/>
<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
<field name="SOFT_RST_SUP" bit="24" size="1" desc="Soft Reset Supported"/>
<field name="SUSPEND_RESUME_SUP" bit="25" size="1" desc="Suspend/Resume Supported"/>
<field name="DEEP_PWRDN_SUP" bit="26" size="1" desc="Deep Powerdown Supported"/>
<field name="RPMC_SUP" bit="27" size="1" desc="RPMC Supported"/>
<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
<field name="VCL" bit="30" size="1" desc="Vendor Component Lock"/>
<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
</register>
<register name="UVSCC" type="mmio" bar="SPIBAR" offset="0xC8" size="4" desc="Vendor Specific Component Capabilities">
<field name="WG" bit="2" size="1" desc="Write Granularity"/>
<field name="WSR" bit="3" size="1" desc="Write Status Required"/>
<field name="WEWS" bit="4" size="1" desc="Write Enable on Write Status"/>
<field name="QER" bit="5" size="3" desc="Quad Enable Requirements"/>
<field name="EO_4k" bit="8" size="8" desc="4k Erase Opcode"/>
<field name="EO_64k" bit="16" size="8" desc="64k Erase Opcode"/>
<field name="SOFT_RST_SUP" bit="24" size="1" desc="Soft Reset Supported"/>
<field name="SUSPEND_RESUME_SUP" bit="25" size="1" desc="Suspend/Resume Supported"/>
<field name="DEEP_PWRDN_SUP" bit="26" size="1" desc="Deep Powerdown Supported"/>
<field name="RPMC_SUP" bit="27" size="1" desc="RPMC Supported"/>
<field name="EO_4k_VALID" bit="28" size="1" desc="4k Erase Valid"/>
<field name="EO_64k_VALID" bit="29" size="1" desc="64k Erase Valid"/>
<field name="CPPTV" bit="31" size="1" desc="Component Property Parameter Table Valid"/>
</register>
<!-- Power Management Registers -->
<register name="GEN_PMCON_1" type="mmio" bar="PWRMBASE" offset="0x1020" size="4" desc="General PM Configuration 1" />
<register name="GEN_PMCON_2" type="mmio" bar="PWRMBASE" offset="0x1024" size="4" desc="General PM Configuration 2">
<field name="SMI_LOCK" bit="4" size="1"/>
</register>
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<!-- CPU MSRs -->
<!-- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~ -->
<register name="PRMRR_UNCORE_PHYBASE" undef="Not supported by GLK" />
<register name="PRMRR_UNCORE_MASK" undef="Not supported by GLK" />
<register name="BIOS_SE_SVN" undef="Not supported by GLK" />
<!-- Port I/O Registers -->
<!-- PCH TCOBASE (SMBus TCO) I/O registers -->
<register name="TCO1_CNT" type="iobar" bar="ABASE" offset="0x68" size="4" desc="TCO1 Control">
<field name="TCO_LOCK" bit="12" size="1" desc="TCO Lock"/>
</register>
<!-- PCH ABASE (PMBASE) -->
<register name="SMI_EN" type="iobar" bar="ABASE" offset="0x40" size="4" desc="SMI Control and Enable">
<field name="GBL_SMI_EN" bit="0" size="1"/>
<field name="EOS" bit="1" size="1"/>
<field name="BIOS_EN" bit="2" size="1"/>
<field name="LEGACY_USB_EN" bit="3" size="1"/>
<field name="SLP_SMI_EN" bit="4" size="1"/>
<field name="APMC_EN" bit="5" size="1"/>
<field name="SWSMI_TMR_EN" bit="6" size="1"/>
<field name="BIOS_RLS" bit="7" size="1"/>
<field name="MCSMI_EN" bit="11" size="1"/>
<field name="TCO_EN" bit="13" size="1"/>
<field name="PERIODIC_EN" bit="14" size="1"/>
<field name="LEGACY_USB2_EN" bit="17" size="1"/>
<field name="INTEL_USB2_EN" bit="18" size="1"/>
<field name="GPIO_UNLOCK_SMI_EN" bit="27" size="1"/>
<field name="ME_SMI_EN" bit="30" size="1"/>
<field name="xHCI_SMI_EN" bit="31" size="1"/>
</register>
</registers>
<!-- #################################### -->
<!-- -->
<!-- 'Controls' -->
<!-- -->
<!-- #################################### -->
<controls>
<control name="TopSwapStatus" register="BC" field="TS" desc="Top Swap Status"/>
<control name="TopSwap" register="BC" field="TS" desc="Top Swap"/>
<control name="BiosInterfaceLockDown" register="BC" field="BILD" desc="BIOS Interface Lock-Down"/>
<control name="SpiWriteStatusDis" register="HSFS" field="WRSDIS" desc="Write Status Disable"/>
<control name="SMILock" register="GEN_PMCON_2" field="SMI_LOCK" desc="SMI Global Configuration Lock"/>
<control name="TcoCtlLock" register="TCOCTL" field="TCO_BASE_LOCK" desc="TCO Base Lock"/>
</controls>
</configuration>
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