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https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
BrentHoltsclaw
63189c29ba
Add reqs_pch to configuration attributes within template.xml Add reqs_pch as field for WHL as example Update logic within chipset.py to check if reqs_pch attribute exists Update logic within chipset.py to raise error if pch is required and driver needs to be loaded Note can still work around with the -i flag Signed-off-by: BrentHoltsclaw <brent.holtsclaw@intel.com>
66 lines
3.1 KiB
XML
66 lines
3.1 KiB
XML
<?xml version="1.0"?>
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<configuration platform="[PLATFORM_CODE]" req_pch="BOOLEAN">
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<!--
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Template for XML configuration file
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-->
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<!-- #################################### -->
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<!-- -->
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<!-- Integrated devices -->
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<!-- -->
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<!-- #################################### -->
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<pci>
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<device name="[DEVICE NAME]" bus="[BUS#]" dev="[DEVICE#]" fun="[FUNCTION#]" vid="[VENDOR ID]" />
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</pci>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory Mapped I/O spaces (MMIO BARs) -->
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<!-- -->
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<!-- #################################### -->
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<mmio>
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<!-- use this definition -->
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<bar name="[BAR NAME]" register="[BAR REGISTER NAME]" base_field="[BAR BASE BIT FIELD]" enable_field="[BAR ENABLE BIT FIELD]" size="[BAR SIZE]" desc="[BAR DESCRIPTION]"/>
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<!-- or (old definition) -->
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<bar name="[BAR NAME]" bus="[BUS#]" dev="[DEVICE#]" fun="[FUNCTION#]" reg="[BAR REGISTER OFFSET]" width="[BAR REGISTER WIDTH]" mask="[BAR REGISTER MASK]" size="[BAR SIZE]" enable_bit="[BAR ENABLE BIT POSITION]" desc="[BAR DESCRIPTION]"/>
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</mmio>
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<!-- #################################### -->
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<!-- -->
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<!-- I/O spaces (I/O BARs) -->
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<!-- -->
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<!-- #################################### -->
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<io>
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<!-- use this definition -->
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<bar name="[BAR NAME]" register="[BAR REGISTER NAME]" base_field="[BAR BASE BIT FIELD]" enable_field="[BAR ENABLE BIT FIELD]" size="[BAR SIZE]" desc="[BAR DESCRIPTION]"/>
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<!-- or (old definition) -->
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<bar name="[BAR NAME]" bus="[BUS#]" dev="[DEVICE#]" fun="[FUNCTION#]" reg="[BAR REGISTER OFFSET]" mask="[BAR REGISTER MASK]" size="[BAR SIZE]" desc="[BAR DESCRIPTION]"/>
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</io>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory ranges -->
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<!-- -->
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<!-- #################################### -->
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<memory>
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<range name="[RANGE NAME]" access="dram|mmio" address="[PHYS ADDRESS]" size="[RANGE SIZE]"/>
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</memory>
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<!-- #################################### -->
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<!-- -->
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<!-- Configuration registers -->
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<!-- -->
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<!-- #################################### -->
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<registers>
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<register name="[UNIQUE REGISTER NAME]" type="msr|mmio|io|iobar|pcicfg|mmcfg|msgbus|memory" desc="[REGISTER DESCRIPTION]" />
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</registers>
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<!-- #################################### -->
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<!-- -->
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<!-- Controls -->
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<!-- -->
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<!-- #################################### -->
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<controls>
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<control name="[UNIQUE CONTROL NAME]" register="[REGISTER NAME WITH THIS CONTROL]" field="[CONTROL FIELD NAME WITHIN REGISTER]" desc="[CONTROL DESCRIPTION]" />
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</controls>
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</configuration> |