mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Jason Zhou
139 lines
4.1 KiB
C
139 lines
4.1 KiB
C
/*
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CHIPSEC: Platform Security Assessment Framework
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Copyright (c) 2010-2019, Intel Corporation
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; Version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Contact information:
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chipsec@intel.com
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*/
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#ifndef CPU_H
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#define CPU_H
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//#ifndef _WIN64 TODO: remove
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#if 0
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#define _eflags( eflags ) __asm \
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{ \
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__asm push eax \
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__asm pushfd \
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__asm pop eax \
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__asm mov eflags, eax \
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__asm pop eax \
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}
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#endif
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#if defined(_M_AMD64)
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typedef UINT64 CPU_REG_TYPE;
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typedef UINT64 UINTN;
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#elif defined(_M_IX86)
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typedef unsigned long CPU_REG_TYPE;
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typedef UINT32 UINTN;
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#else
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#error "Architecture not supported"
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#endif
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typedef struct _swsmi_msg_t {
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UINTN code_data;
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UINTN rax;
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UINTN rbx;
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UINTN rcx;
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UINTN rdx;
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UINTN rsi;
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UINTN rdi;
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} swsmi_msg_t;
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extern CPU_REG_TYPE ReadCR0();
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extern CPU_REG_TYPE ReadCR2();
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extern CPU_REG_TYPE ReadCR3();
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extern CPU_REG_TYPE ReadCR4();
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#if defined(_M_AMD64)
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extern CPU_REG_TYPE ReadCR8();
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#endif
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extern void WriteCR0( CPU_REG_TYPE cr_val );
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extern void WriteCR2( CPU_REG_TYPE cr_val );
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extern void WriteCR3( CPU_REG_TYPE cr_val );
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extern void WriteCR4( CPU_REG_TYPE cr_val );
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#if defined(_M_AMD64)
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extern void WriteCR8( CPU_REG_TYPE cr_val );
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#endif
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/*
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* External Assembly Functions
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*/
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// -- Access to CPU MSRs
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extern void _rdmsr( UINT32 msr_num, UINT32* msr_lo, UINT32* msr_hi );
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extern void _wrmsr( UINT32 msr_num, UINT32 msr_lo, UINT32 msr_hi );
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// -- Access to PCI CFG space
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extern void WritePCIByte ( UINT32 pci_reg, UINT16 cfg_data_port, UINT8 byte_value );
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extern void WritePCIWord ( UINT32 pci_reg, UINT16 cfg_data_port, UINT16 word_value );
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extern void WritePCIDword( UINT32 pci_reg, UINT16 cfg_data_port, UINT32 dword_value );
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extern UINT8 ReadPCIByte ( UINT32 pci_reg, UINT16 cfg_data_port );
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extern UINT16 ReadPCIWord ( UINT32 pci_reg, UINT16 cfg_data_port );
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extern UINT32 ReadPCIDword ( UINT32 pci_reg, UINT16 cfg_data_port );
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// -- Access to Port I/O
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extern UINT32 ReadPortDword ( UINT16 port_num );
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extern UINT16 ReadPortWord ( UINT16 port_num );
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extern UINT8 ReadPortByte ( UINT16 port_num );
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extern void WritePortDword( UINT32 out_value, UINT16 port_num );
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extern void WritePortWord ( UINT16 out_value, UINT16 port_num );
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extern void WritePortByte ( UINT8 out_value, UINT16 port_num );
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// -- Access to CPU Descriptor tables
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extern void _store_idtr( void* desc_address );
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extern void _load_idtr ( void* desc_address );
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extern void _store_gdtr( void* desc_address );
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extern void _store_ldtr( void* desc_address );
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// -- Interrupts
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extern void _swsmi( swsmi_msg_t* sw_smi );
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// -- Hypercalls
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extern CPU_REG_TYPE hypercall (
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CPU_REG_TYPE rcx_val,
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CPU_REG_TYPE rdx_val,
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CPU_REG_TYPE r8_val,
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CPU_REG_TYPE r9_val,
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CPU_REG_TYPE r10_val,
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CPU_REG_TYPE r11_val,
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CPU_REG_TYPE rax_val,
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CPU_REG_TYPE rbx_val,
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CPU_REG_TYPE rdi_val,
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CPU_REG_TYPE rsi_val,
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CPU_REG_TYPE xmm_buffer,
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CPU_REG_TYPE hypercall_page
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);
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extern CPU_REG_TYPE hypercall_page(void);
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// --
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// -- MSR definitions
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// --
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#define MSR_IA32_BIOS_UPDT_TRIG 0x79
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#define MSR_IA32_BIOS_SIGN_ID 0x8b
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// -- CPU Descriptor tables
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typedef enum {
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CPU_DT_CODE_IDTR = 0x0,
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CPU_DT_CODE_GDTR = 0x1,
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CPU_DT_CODE_LDTR = 0x2,
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} DTR_CODE;
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#pragma pack(1)
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typedef struct _DESCRIPTOR_TABLE_RECORD {
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UINT16 limit;
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//UINT32 base_hi;
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//UINT32 base_lo;
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ULONG_PTR base;
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} DESCRIPTOR_TABLE_RECORD, *PDESCRIPTOR_TABLE_RECORD;
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#pragma pack()
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#endif // CPU_H
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