mirror of
https://github.com/chipsec/chipsec
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coudrant
7247978cfb
* Initial submission of AMD common modules * Corrected Copyright and Email for AMD modules. Major fixes to spectre module. Timeout added to PSP. Added rom_armor. * Corrected Copyright and Email for AMD modules. Major fixes to spectre module. Timeout added to PSP. Added rom_armor. * Corrected Platform Configuration. Corrected cpu_info for Intel. * Corrected register checks in spectre module * Comestic changes to strix.xml. Code quality improvements to psp and smm_addr. smm_base is redundant and removed * Corrected smm_addr use of SMMMASK. Added PATCH_LEVEL. Added psp to chipset. * Cleaned up results.id smm_addr.py * <sku code> now matches <configuration> in strix.xml
235 lines
23 KiB
XML
235 lines
23 KiB
XML
<?xml version="1.0"?>
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<configuration platform="Strix Point">
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<!-- #################################### -->
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<!-- -->
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<!-- Information -->
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<!-- -->
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<!-- #################################### -->
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<info family="core">
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<sku did="0x1507" name="Strix Point" code="Strix Point" longname="Strix Point Root Complex" />
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</info>
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<!-- #################################### -->
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<!-- -->
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<!-- Integrated devices -->
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<!-- -->
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<!-- #################################### -->
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<pci>
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<!--
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00:18.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1679
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00:18.1 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167a
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00:18.2 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167b
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00:18.3 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167c
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00:18.4 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167d
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00:18.5 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167e
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00:18.6 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 167f
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00:18.7 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 1680
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02:00.0 Ethernet controller: Realtek Semiconductor Co., Ltd. RTL8125 2.5GbE Controller (rev 05)
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03:00.0 Network controller: Intel Corporation Wi-Fi 6 AX200 (rev 1a)
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74:00.0 VGA compatible controller: Advanced Micro Devices, Inc. [AMD/ATI] Rembrandt (rev c8)
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74:00.2 Encryption controller: Advanced Micro Devices, Inc. [AMD] VanGogh PSP/CCP
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74:00.5 Multimedia controller: Advanced Micro Devices, Inc. [AMD] Raven/Raven2/FireFlight/Renoir Audio Processor (rev 60)
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-->
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<!-- Table 13: PCI Device ID Assignments. -->
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<!-- Bus A and B are programmable. Here, we assume A = 5 and B = 1. -->
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<!--device name="ROOT" bus="0" dev="0x00" fun="0" vid="0x1022" did="0x14B5" /-->
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<device name="IOMMU" bus="0" dev="0x00" fun="2" vid="0x1022" did="0x14B6" />
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<device name="HOSTDUMMY0" bus="0" dev="0x01" fun="0" vid="0x1022" did="0x14B7" />
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<!-- PCIe GPP Bridge -->
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<device name="GPP0" bus="0" dev="0x01" fun="1" vid="0x1022" did="0x15D3" />
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<device name="LPC" bus="0" dev="0x14" fun="3" vid="0x1022" did="0x790E" />
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<!--
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00:01.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14ba
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<device name="GPP1" bus="0" dev="0x01" fun="2" vid="0x1022" did="0x15D3" />
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00:01.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14ba
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00:02.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 14b7 (rev 01)
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00:02.2 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14ba
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00:03.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 14b7 (rev 01)
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00:03.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14cd
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00:04.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 14b7 (rev 01)
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00:08.0 Host bridge: Advanced Micro Devices, Inc. [AMD] Device 14b7 (rev 01)
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00:08.1 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14b9 (rev 10)
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00:08.3 PCI bridge: Advanced Micro Devices, Inc. [AMD] Device 14b9 (rev 10)
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<device name="HOSTDUMMY1" bus="0" dev="0x08" fun="0" vid="0x1022" did="0x1452" />
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<device name="GPP0TOBUSA" bus="0" dev="0x08" fun="1" vid="0x1022" did="0x15DB" />
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<device name="GPP0TOBUSB" bus="0" dev="0x08" fun="2" vid="0x1022" did="0x15DC" />
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-->
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<!-- Note: Vendor ID 1002h is used for Internal GPU and Display HD Audio Controller. -->
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<!-- Model 18h: did=0x15D8. Models 10h, 11h: did=0x15DD -->
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<!--
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<device name="GPU" bus="5" dev="0x00" fun="0" vid="0x1002" did="0x15D8,0x15DD" />
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<device name="DISPLAYHDAUDIO" bus="5" dev="0x00" fun="1" vid="0x1002" did="0x15DE" />
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<device name="USB0" bus="74" dev00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 161d
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<device name "USB1" bus="74" dev00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 161e
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<device name "USB2" bus="75" dev00.0 USB controller: Advanced Micro Devices, Inc. [AMD] Device 161f
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<device name "USB3" bus="75" dev00.3 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15d6
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<device name "USB4" bus="75" dev00.4 USB controller: Advanced Micro Devices, Inc. [AMD] Device 15d7
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<device name "USB5" bus="75" dev00.5 USB controller: Advanced Micro Devices, Inc. [AMD] Device 162e
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74:00.6 Audio device: Advanced Micro Devices, Inc. [AMD] Family 17h (Models 10h-1fh) HD Audio Controller
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74:00.1 Audio device: Advanced Micro Devices, Inc. [AMD/ATI] Device 1640
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<device name="AUDIO" bus="5" dev="0x00" fun="5" vid="0x1022" did="0x15E2" />
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<device name="HDAUDIO" bus="5" dev="0x00" fun="6" vid="0x1022" did="0x15E3" />
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<device name="DF0" bus="0" dev="0x18" fun="0" vid="0x1022" did="0x15E8" />
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<device name="DF1" bus="0" dev="0x18" fun="1" vid="0x1022" did="0x15E9" />
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<device name="DF2" bus="0" dev="0x18" fun="2" vid="0x1022" did="0x15EA" />
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<device name="DF3" bus="0" dev="0x18" fun="3" vid="0x1022" did="0x15EB" />
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<device name="DF4" bus="0" dev="0x18" fun="4" vid="0x1022" did="0x15EC" />
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<device name="DF5" bus="0" dev="0x18" fun="5" vid="0x1022" did="0x15ED" />
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<device name="DF6" bus="0" dev="0x18" fun="6" vid="0x1022" did="0x15EE" />
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<device name="DF7" bus="0" dev="0x18" fun="7" vid="0x1022" did="0x15EF" />
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<device name="SATAMS" bus="1" dev="0x00" fun="0" vid="0x1022" did="0x7901" />
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<device name="SATAAMD" bus="1" dev="0x00" fun="0" vid="0x1022" did="0x7904" />
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<device name="SD" bus="0" dev="0x14" fun="6" vid="0x1022" did="0x7906" />
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00:14.0 SMBus: Advanced Micro Devices, Inc. [AMD] FCH SMBus Controller (rev 71)
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00:14.3 ISA bridge: Advanced Micro Devices, Inc. [AMD] FCH LPC Bridge (rev 51)
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<device name="SMBUS" bus="0" dev="0x14" fun="0" vid="0x1022" did="0x790B" />
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<device name="SATARAID0" bus="1" dev="0x00" fun="0" vid="0x1022" did="0x7916" />
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<device name="SATARAID1" bus="1" dev="0x00" fun="0" vid="0x1022" did="0x7917" />
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<device name="GBE0" bus="1" dev="0x00" fun="1" vid="0x1022" did="0x1458" />
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<device name="GBE1" bus="1" dev="0x00" fun="2" vid="0x1022" did="0x1458" />
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<device name="FUNCTIONDUMMY" bus="1" dev="0x00" fun="0" vid="0x1022" did="0x145A" />
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-->
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</pci>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory Mapped I/O spaces (MMIO BARs) -->
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<!-- -->
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<!-- #################################### -->
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<mmio>
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</mmio>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory ranges -->
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<!-- -->
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<!-- #################################### -->
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<memory>
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</memory>
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<!-- #################################### -->
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<!-- -->
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<!-- Indirect memory accesses -->
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<!-- -->
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<!-- #################################### -->
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<ima>
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</ima>
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<!-- #################################### -->
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<!-- -->
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<!-- I/O spaces (I/O BARs) -->
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<!-- -->
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<!-- #################################### -->
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<io>
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</io>
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<!-- #################################### -->
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<!-- -->
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<!-- Configuration registers -->
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<!-- -->
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<!-- #################################### -->
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<registers>
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<register name="HWCR" type="msr" msr="0xc0010015" desc="Hardware Configuration">
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<field name="SmmPgCfgLock" bit="33" size="1" desc="1=SMM page config locked."/>
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<field name="SmmBaseLock" bit="31" size="1" desc="Disable SMM_BASE from being saved to and restored from the SMM save state area."/>
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<field name="SmmLock" bit="0" size="1" desc="SMM code in the ASeg and TSeg range and the SMM registers are Read-only and SMI interrupts are not intercepted in SVM."/>
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</register>
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<register name="PATCH_LEVEL" type="msr" msr="0x0000008B" desc="Patch Level. Read,Error-on-write,Volatile. Reset: 0000_0000_0000_0000h.">
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<!-- Bits 63:32 reserved. -->
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<field name="PatchLevel" bit="0" size="32" desc="Read,Error-on-write,Volatile. Reset: 0000_0000h. This returns an identification number for the microcode patch that has been loaded. If no patch has been loaded, this returns 0." />
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</register>
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<register name="SPIBASEADDR" type="pcicfg" device="LPC" offset="0x0A0" size="4" desc="SPI Base_Addr. Read-write. Reset: FEC1_0002h.">
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<field name="Spi_eSpi_BaseAddr" bit="8" size="24" desc="Read-write. Reset: FE_C100h." />
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<!-- Bits 7:5 reserved. -->
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<field name="PspSpiMmioSel" bit="4" size="1" desc="Read-write. Reset: 0. 0=SPI MMIO register for Host. 1=SPI MMIO register for PSP. PSP SPI MMIO select." />
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<field name="RouteTpm2Spi" bit="3" size="1" desc="Read-write. Reset: 0. 1=TPM cycles are routed to SPI bus with TPM_SPI_CS# asserted. Route TPM to SPI." />
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<field name="AbortEnable" bit="2" size="1" desc="Read-write. Reset: 0. LPC Abort enable." />
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<field name="SpiRomEnable" bit="1" size="1" desc="Read-write. Reset: 1. 0=SPI ROM is disabled. 1=SPI ROM is enabled if chip is strapped to SPI ROM." />
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<field name="AltSpiCSEnable" bit="0" size="1" desc="Read-write. Reset: 0. Alternative SPI CS enable." />
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</register>
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<register name="ROMPROTECT0" type="pcicfg" device="LPC" offset="0x050" size="4" lockedby="SpiHostAccessRomEn" desc="ROM Protect 0. Read,Write-once. Reset: 0000_0000h. This register specifies different ROM ranges to be protected. FCH::ITF::SPI::AltSPICS[SpiProtectEn0] enables the protection ranges. The addresses are within the defined ROM range if: {RomBase, 000_0000_0000b} <= address[31:0] <= ({RomBase, 000_0000_0000b} + (Range << (RangeUnit ? 16 : 12))). For the host, this register can only be written once after hardware reset; subsequent writes have no effect. To enable writing to this register again, one can generate an SMI through FCH or apply hardware reset.">
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<field name="RomBase" bit="12" size="20" desc="ROM Base. Read,Write-once. Reset: 0_0000h." />
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<!-- Bit 11 reserved. -->
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<field name="WriteProtect" bit="10" size="1" desc="Write Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is write- protected and writing to the range has no effect." />
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<field name="ReadProtect" bit="9" size="1" desc="Read Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is read- protected and reading any location in the range returns FFFF_FFFFh." />
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<field name="RangeUnit" bit="8" size="1" desc="Read,Write-once. Reset: 0. 0=4 KB. 1=64 KB." />
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<field name="Range" bit="0" size="8" desc="Read,Write-once. Reset: 00h. Description: Specifies the protected range. The unit is defined at bit[8] in the same register. NOTE: The protection is limited to 4GB boundary. Base + Range cannot cross 4GB boundary; otherwise, hardware will not behave correctly. BIOS should make sure the values are within a valid range." />
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</register>
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<register name="ROMPROTECT1" type="pcicfg" device="LPC" offset="0x054" size="4" lockedby="SpiHostAccessRomEn" desc="ROM Protect 1. Read,Write-once. Reset: 0000_0000h. This register specifies different ROM ranges to be protected. FCH::ITF::SPI::AltSPICS[SpiProtectEn0] enables the protection ranges. The addresses are within the defined ROM range if: {RomBase, 000_0000_0000b} <= address[31:0] <= ({RomBase, 000_0000_0000b} + (Range << (RangeUnit ? 16 : 12))). For the host, this register can only be written once after hardware reset; subsequent writes have no effect. To enable writing to this register again, one can generate an SMI through FCH or apply hardware reset.">
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<field name="RomBase" bit="12" size="20" desc="ROM Base. Read,Write-once. Reset: 0_0000h." />
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<!-- Bit 11 reserved. -->
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<field name="WriteProtect" bit="10" size="1" desc="Write Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is write- protected and writing to the range has no effect." />
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<field name="ReadProtect" bit="9" size="1" desc="Read Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is read- protected and reading any location in the range returns FFFF_FFFFh." />
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<field name="RangeUnit" bit="8" size="1" desc="Read,Write-once. Reset: 0. 0=4 KB. 1=64 KB." />
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<field name="Range" bit="0" size="8" desc="Read,Write-once. Reset: 00h. Description: Specifies the protected range. The unit is defined at bit[8] in the same register. NOTE: The protection is limited to 4GB boundary. Base + Range cannot cross 4GB boundary; otherwise, hardware will not behave correctly. BIOS should make sure the values are within a valid range." />
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</register>
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<register name="ROMPROTECT2" type="pcicfg" device="LPC" offset="0x058" size="4" lockedby="SpiHostAccessRomEn" desc="ROM Protect 2. Read,Write-once. Reset: 0000_0000h. This register specifies different ROM ranges to be protected. FCH::ITF::SPI::AltSPICS[SpiProtectEn0] enables the protection ranges. The addresses are within the defined ROM range if: {RomBase, 000_0000_0000b} <= address[31:0] <= ({RomBase, 000_0000_0000b} + (Range << (RangeUnit ? 16 : 12))). For the host, this register can only be written once after hardware reset; subsequent writes have no effect. To enable writing to this register again, one can generate an SMI through FCH or apply hardware reset.">
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<field name="RomBase" bit="12" size="20" desc="ROM Base. Read,Write-once. Reset: 0_0000h." />
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<!-- Bit 11 reserved. -->
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<field name="WriteProtect" bit="10" size="1" desc="Write Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is write- protected and writing to the range has no effect." />
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<field name="ReadProtect" bit="9" size="1" desc="Read Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is read- protected and reading any location in the range returns FFFF_FFFFh." />
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<field name="RangeUnit" bit="8" size="1" desc="Read,Write-once. Reset: 0. 0=4 KB. 1=64 KB." />
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<field name="Range" bit="0" size="8" desc="Read,Write-once. Reset: 00h. Description: Specifies the protected range. The unit is defined at bit[8] in the same register. NOTE: The protection is limited to 4GB boundary. Base + Range cannot cross 4GB boundary; otherwise, hardware will not behave correctly. BIOS should make sure the values are within a valid range." />
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</register>
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<register name="ROMPROTECT3" type="pcicfg" device="LPC" offset="0x05C" size="4" lockedby="SpiHostAccessRomEn" desc="ROM Protect 3. Read,Write-once. Reset: 0000_0000h. This register specifies different ROM ranges to be protected. FCH::ITF::SPI::AltSPICS[SpiProtectEn0] enables the protection ranges. The addresses are within the defined ROM range if: {RomBase, 000_0000_0000b} <= address[31:0] <= ({RomBase, 000_0000_0000b} + (Range << (RangeUnit ? 16 : 12))). For the host, this register can only be written once after hardware reset; subsequent writes have no effect. To enable writing to this register again, one can generate an SMI through FCH or apply hardware reset.">
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<field name="RomBase" bit="12" size="20" desc="ROM Base. Read,Write-once. Reset: 0_0000h." />
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<!-- Bit 11 reserved. -->
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<field name="WriteProtect" bit="10" size="1" desc="Write Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is write- protected and writing to the range has no effect." />
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<field name="ReadProtect" bit="9" size="1" desc="Read Protect. Read,Write-once. Reset: 0. 1=The memory range defined by this register is read- protected and reading any location in the range returns FFFF_FFFFh." />
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<field name="RangeUnit" bit="8" size="1" desc="Read,Write-once. Reset: 0. 0=4 KB. 1=64 KB." />
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<field name="Range" bit="0" size="8" desc="Read,Write-once. Reset: 00h. Description: Specifies the protected range. The unit is defined at bit[8] in the same register. NOTE: The protection is limited to 4GB boundary. Base + Range cannot cross 4GB boundary; otherwise, hardware will not behave correctly. BIOS should make sure the values are within a valid range." />
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</register>
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<register name="SMM_BASE" type="msr" msr="0xC0010111" desc="SMM Base Address. Reset: 0000_0000_0003_0000h. This holds the base of the SMM memory region. The value of this register is stored in the save state on entry into SMM (see 2.1.11.1.5 [SMM Save State]) and it is restored on returning from SMM. The 16-bit CS (code segment) selector is loaded with SmmBase[19:4] on entering SMM. SmmBase[3:0] is required to be 0. The SMM base address can be changed in two ways: • The SMM base address, at offset FF00h in the SMM state save area, may be changed by the SMI handler. The RSM instruction updates SmmBase with the new value. • Normal WRMSR access to this register.">
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<!-- Bits 63:32 reserved. -->
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<field name="SMMBASE" bit="0" size="32" desc="Reset: 0003_0000h. AccessType: Core::X86::Msr::HWCR[SmmLock] ? Read-only : Read-write." />
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</register>
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<register name="SMMADDR" type="msr" msr="0xC0010112" desc="SMM TSeg Base Address. Configurable. Reset: 0000_0000_0000_0000h. See 2.1.11.1 [System Management Mode (SMM)] and 2.1.5.3.1 [Memory Access to the Physical Address Space]. See Core::X86::Msr::SMMMask for more information about the ASeg and TSeg address ranges. Each CPU access, directed at CPUAddr, is determined to be in the TSeg range if the following is true: CPUAddr[47:17] & TSegMask[47:17] == TSegBase[47:17] & TSegMask[47:17]. For example, if TSeg spans 256 KBs and starts at the 1-MB address. The Core::X86::Msr::SMMAddr[TSegBase[47:17]] would be set to 0010_0000h and the Core::X86::Msr::SMMMask[TSegMask[47:17]] to FFFC_0000h (with zeros filling in for bits[16:0]). This results in a TSeg range from 0010_0000 to 0013_FFFFh.">
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<!-- Bits 63:48 reserved. -->
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<field name="TSEGBASE" bit="17" size="31" desc="TSeg address range base. Configurable. Reset: 0000_0000h. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
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<!-- Bits 16:0 reserved. -->
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</register>
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<register name="SMMMASK" type="msr" msr="0xC0010113" desc="SMM TSeg Mask. Configurable. Reset: 0000_0000_0000_0000h. See 2.1.11.1 [System Management Mode (SMM)]. The ASeg address range is located at a fixed address from A0000h–BFFFFh. The TSeg range is located at a variable base (specified by Core::X86::Msr::SMMAddr[TSegBase[47:17]]) with a variable size (specified by Core::X86::Msr::SMMMask[TSegMask[47:17]]). These ranges provide a safe location for SMM code and data that is not readily accessible by non-SMM applications. The SMI handler can be located in one of these two ranges, or it can be located outside these ranges. These ranges must never overlap each other. This register specifies how accesses to the ASeg and TSeg address ranges are controlled as follows: • If [A,T]Valid == 1, then: • If in SMM, then: • If [A, T]Close == 0, then the accesses are directed to DRAM with memory type as specified in [A, T]MTypeDram. • If [A, T]Close == 1, then instruction accesses are directed to DRAM with memory type as specified in [A, T]MTypeDram and data accesses are directed at MMIO space and with attributes based on [A, T]MTypeIoWc. • If not in SMM, then the accesses are directed at MMIO space with attributes based on [A,T]MTypeIoWc. • See 2.1.5.3.1.1 [Determining Memory Type].">
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<!-- Bits 63:48 reserved. -->
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<field name="TSEGMASK" bit="17" size="31" desc="TSeg address range mask. Configurable. Reset: 0000_0000h. See Core::X86::Msr::SMMAddr. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
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<!-- Bits 16:15 reserved. -->
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<field name="TMTYPEDRAM" bit="12" size="3" desc="TSeg address range memory type. Configurable. Reset: 0h. Specifies the memory type for SMM accesses to the TSeg range that are directed to DRAM. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write. " />
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<!-- Bit 11 reserved. -->
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<field name="AMTYPEDRAM" bit="8" size="3" desc="ASeg Range Memory Type. Configurable. Reset: 0h. Specifies the memory type for SMM accesses to the ASeg range that are directed to DRAM. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
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<!-- Bits 7:6 reserved. -->
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<field name="TMTYPEIOWC" bit="5" size="1" desc="non-SMM TSeg address range memory type. Configurable. Reset: 0. 0=UC (uncacheable). 1=WC (write combining). Specifies the attribute of TSeg accesses that are directed to MMIO space. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
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<field name="AMTYPEIOWC" bit="4" size="1" desc="non-SMM ASeg address range memory type. Configurable. Reset: 0. 0=UC (uncacheable). 1=WC (write combining). Specifies the attribute of ASeg accesses that are directed to MMIO space. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
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<field name="TCLOSE" bit="3" size="1" desc="send TSeg address range data accesses to MMIO. Configurable. Reset: 0. 1=When in SMM, direct data accesses in the TSeg address range to MMIO space. See AClose. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
|
||
<field name="ACLOSE" bit="2" size="1" desc="send ASeg address range data accesses to MMIO. Configurable. Reset: 0. 1=When in SMM, direct data accesses in the ASeg address range to MMIO space. [A,T]Close allows the SMI handler to access the MMIO space located in the same address region as the [A,T]Seg. When the SMI handler is finished accessing the MMIO space, it must clear the bit. Failure to do so before resuming from SMM causes the CPU to erroneously read the save state from MMIO space. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
|
||
<field name="TVALID" bit="1" size="1" desc="enable TSeg SMM address range. Configurable. Reset: 0. 1=The TSeg address range SMM enabled. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
|
||
<field name="AVALID" bit="0" size="1" desc="enable ASeg SMM address range. Configurable. Reset: 0. 1=The ASeg address range SMM enabled. AccessType: (Core::X86::Msr::HWCR[SmmLock]) ? Read-only : Read-write." />
|
||
</register>
|
||
<register name="SPEC_CTRL" type="msr" msr="0x48" desc="Speculation Control MSR">
|
||
<field name="IBRS" bit="0" size="1" desc="Enable Indirect Branch Restricted Speculation (IBRS)" />
|
||
<field name="STIBP" bit="1" size="1" desc="Enable Single Thread Indirect Branch Predictors (STIBP)" />
|
||
<field name="SSBD" bit="2" size="1" desc="Delays speculative execution of load until the addr for all older stores are known" />
|
||
<field name="PSFD" bit="7" size="1" desc="Disable predictive store forwarding" />
|
||
</register>
|
||
</registers>
|
||
|
||
|
||
|
||
<!-- #################################### -->
|
||
<!-- -->
|
||
<!-- Controls -->
|
||
<!-- -->
|
||
<!-- #################################### -->
|
||
<controls>
|
||
</controls>
|
||
|
||
<!-- #################################### -->
|
||
<!-- -->
|
||
<!-- Locks -->
|
||
<!-- -->
|
||
<!-- #################################### -->
|
||
<locks>
|
||
</locks>
|
||
|
||
</configuration>
|