mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
97 lines
4.7 KiB
XML
97 lines
4.7 KiB
XML
<?xml version="1.0"?>
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<configuration platform="ADL" req_pch="True">
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<!--
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CHIPSEC: Platform Security Assessment Framework
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Copyright (c) 2023, Intel Corporation
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; Version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Contact information:
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chipsec@intel.com
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-->
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<!--
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XML configuration file for Alder Lake based platforms
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http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
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* 12th Generation Intel(R) Core Processor Family Datasheet
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Review: !!!
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* Intel(R) 600 Series Chipset Family on-package Platform Controller Hub (PCH)
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-->
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<!-- #################################### -->
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<!-- -->
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<!-- Information -->
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<!-- -->
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<!-- #################################### -->
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<info family="core" detection_value="0x90670-0x90672, 0x90674-0x90675, 0x906a0-0x906a4">
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<sku did="0x4601" name="AlderLake" code="ADL" longname="ADL-P/U15 2+8"/>
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<sku did="0x4602" name="AlderLake" code="ADL" longname="ADL-U9 2+8"/>
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<sku did="0x4609" name="AlderLake" code="ADL" longname="ADL-U15 2+4"/>
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<sku did="0x460A" name="AlderLake" code="ADL" longname="ADL-U9 2+4"/>
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<sku did="0x4610" name="AlderLake" code="ADL" longname="ADL-S LGA 2+0"/>
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<sku did="0x4619" name="AlderLake" code="ADL" longname="ADL-U15 1+4"/>
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<sku did="0x461A" name="AlderLake" code="ADL" longname="ADL-U9 1+4"/>
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<sku did="0x4621" name="AlderLake" code="ADL" longname="ADL-P/H 4+8"/>
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<sku did="0x4629" name="AlderLake" code="ADL" longname="ADL-H 4+4"/>
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<sku did="0x4630" name="AlderLake" code="ADL" longname="ADL-S LGA 4+0"/>
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<sku did="0x4641" name="AlderLake" code="ADL" longname="ADL-P/H 6+8"/>
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<sku did="0x4648" name="AlderLake" code="ADL" longname="ADL-S LGA 6+4"/>
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<sku did="0x4649" name="AlderLake" code="ADL" longname="ADL-H 6+4"/>
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<sku did="0x4650" name="AlderLake" code="ADL" longname="ADL-S LGA 6+0"/>
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<sku did="0x4660" name="AlderLake" code="ADL" longname="ADL-S LGA 8+8"/>
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<sku did="0x4668" name="AlderLake" code="ADL" longname="ADL-S LGA 8+4"/>
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</info>
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<!-- #################################### -->
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<!-- -->
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<!-- Integrated devices -->
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<!-- -->
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<!-- #################################### -->
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<pci>
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<!-- Review !!!! !!!! /-->
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<device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" did="0x4621,0x4660" config="HOSTCTL.hostctl1.xml" >
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<subcomponent type="mmiobar" name="MCHBAR" register="MCHBAR" base_field="MCHBAR" size="0x8000" enable_bit="0" desc="Host Memory Mapped Register Range" config="MMIO.mmio0.xml" />
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<subcomponent type="mmiobar" name="MCHBARMC1" register="MCHBAR" base_field="MCHBAR" offset="0x10000" size="0x8000" enable_bit="0" desc="Host Memory Mapped Register Range" config="MMIO.mmio0.xml" />
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<subcomponent type="mmiobar" name="VTBAR" register="MCHBAR.VTBAR" base_field="BASE" size="0x8000" enable_bit="0" desc="VTD Register Range" config="IOMMU.iommu.xml" />
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<subcomponent type="mmiobar" name="GFXVTBAR" register="MCHBAR.GFXVTBAR" base_field="BASE" size="0x8000" enable_bit="0" desc="GFXVTD Register Range" config="IOMMU.iommu.xml" />
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</device>
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<!-- <device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" config=""/> -->
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<device name="IGD" bus="0x00" dev="0x02" fun="0" config="IGD.igd0.xml" />
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<device name="MEI1" bus="0x00" dev="0x16" fun="0" config="ME.mei0.xml" />
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</pci>
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<msr>
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<definition name="MSR" config="MSR.msr2.xml" />
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</msr>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory ranges -->
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<!-- -->
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<!-- #################################### -->
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<memory>
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<range name="TPM" access="mmio" address="0xFED40000" limit="0xFED4FFFF" config="TPM.tpm12.xml" />
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<range name="TXT" access="mmio" address="0xFED30000" limit="0xFED4FFFF" config="TPM.txt.xml" />
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</memory>
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</configuration>
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