mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
66 lines
2.8 KiB
XML
66 lines
2.8 KiB
XML
<?xml version="1.0"?>
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<configuration platform="LNL" req_pch="False">
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<!-- XML configuration file for Lunar Lake -->
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<!--
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CHIPSEC: Platform Security Assessment Framework
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Copyright (c) 2026, Intel Corporation
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; Version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Contact information:
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chipsec@intel.com
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LNL Datasheet Vol1: 829568
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LNL Datasheet Vol2: 831519
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-->
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<!-- #################################### -->
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<!-- -->
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<!-- Information -->
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<!-- -->
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<!-- #################################### -->
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<info family="core" detection_value="0xB06D0-0xB06D1">
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<sku did="0x6400" name="Lunar Lake" code="LNL" longname="Core Ultra 200V Series Processor" />
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</info>
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<!-- #################################### -->
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<!-- -->
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<!-- Integrated devices -->
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<!-- -->
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<!-- #################################### -->
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<pci>
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<!-- Using default configuration files for devices. Need to verify registers once documentation is available. CHIPSEC results may be wrong. -->
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<device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" did="0x6400" config="HOSTCTL.hostctl1.xml"/>
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<device name="IGD" bus="0x00" dev="0x02" fun="0" did="0x64A0" config="IGD.igd0.xml" />
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<device name="DTT" bus="0x00" dev="0x04" fun="0" did="0x641D" />
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<device name="MEI1" bus="0x00" dev="0x16" fun="0" did="0xA870" config="ME.mei0.xml" />
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<device name="P2SBC" bus="0x00" dev="0x1F" fun="1" did="0xA84C,0xA820" config="P2SB.p2sbc0.xml" />
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<device name="SPI" bus="0x00" dev="0x1F" fun="5" did="0xA823" config="SPI.spi0.xml" />
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</pci>
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<msr>
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<definition name="MSR" config="MSR.msr2.xml" />
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</msr>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory ranges -->
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<!-- -->
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<!-- #################################### -->
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<memory>
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<range name="TPM" access="mmio" address="0xFED40000" limit="0xFED4FFFF" config="TPM.tpm12.xml" />
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</memory>
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</configuration>
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