mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
114 lines
5.9 KiB
XML
114 lines
5.9 KiB
XML
<?xml version="1.0"?>
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<configuration platform="RPL" req_pch="True">
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<!--
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CHIPSEC: Platform Security Assessment Framework
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Copyright (c) 2026, Intel Corporation
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; Version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Contact information:
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chipsec@intel.com
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-->
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<!--
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XML configuration file for Raptor Lake based platforms
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http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
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* 13th/14th Generation Intel(R) Core Processor Family Datasheet
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http://www.intel.com/content/www/us/en/processors/core/core-technical-resources.html
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https://cdrdv2.intel.com/v1/dl/getContent/743844
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https://edc.intel.com/content/www/us/en/design/publications/13th-generation-core-processor-datasheet-volume-2-of-2/Chapter-1%20RPL-P%20Datasheet/
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* Intel(R) 600 Series Chipset Family on-package Platform Controller Hub (PCH)
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-->
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<!-- #################################### -->
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<!-- -->
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<!-- Information -->
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<!-- -->
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<!-- #################################### -->
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<info family="core" detection_value="0xB0671,0xB06A2,0xB06A3,0xB06F2,0xB06F5">
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<sku did="0xA700" name="Raptor Lake" code="RPL" longname="RPL-S 8+16"/>
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<sku did="0xA703" name="Raptor Lake" code="RPL" longname="RPL-S 8+8"/>
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<sku did="0xA704" name="Raptor Lake" code="RPL" longname="RPL-S 6+8"/>
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<sku did="0xA705" name="Raptor Lake" code="RPL" longname="RPL-S 6+4"/>
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<sku did="0x4640" name="Raptor Lake" code="RPL" longname="RPL-S 6+8"/>
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<sku did="0x4648" name="Raptor Lake" code="RPL" longname="RPL-S 6+4"/>
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<sku did="0x4630" name="Raptor Lake" code="RPL" longname="RPL-S 4+0"/>
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<sku did="0x4740" name="Raptor Lake" code="RPL" longname="RPL-S 8+12"/>
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<sku did="0x4610" name="Raptor Lake" code="RPL" longname="RPL-S 2+0"/>
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<sku did="0xA702" name="Raptor Lake" code="RPL" longname="RPL-HX 8+16"/>
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<sku did="0xA729" name="Raptor Lake" code="RPL" longname="RPL-HX 8+12"/>
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<sku did="0xA728" name="Raptor Lake" code="RPL" longname="RPL-HX 8+8"/>
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<sku did="0xA72A" name="Raptor Lake" code="RPL" longname="RPL-HX 6+8"/>
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<sku did="0xA719" name="Raptor Lake" code="RPL" longname="RPL-HX 6+4"/>
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<sku did="0x4637" name="Raptor Lake" code="RPL" longname="RPL-HX 8+8"/>
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<sku did="0x463B" name="Raptor Lake" code="RPL" longname="RPL-HX 6+8"/>
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<sku did="0x4647" name="Raptor Lake" code="RPL" longname="RPL-HX 6+4"/>
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<sku did="0xA706" name="Raptor Lake" code="RPL" longname="RPL-H/P/PX 6+8"/>
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<sku did="0xA707" name="Raptor Lake" code="RPL" longname="RPL-H/P 4+8"/>
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<sku did="0xA715" name="Raptor Lake" code="RPL" longname="RPL-H 6+4"/>
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<sku did="0xA716" name="Raptor Lake" code="RPL" longname="RPL-H 4+4"/>
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<sku did="0xA709" name="Raptor Lake" code="RPL" longname="RPL-P 6+8"/>
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<sku did="0xA70A" name="Raptor Lake" code="RPL" longname="RPL-P 4+8"/>
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<sku did="0xA708" name="Raptor Lake" code="RPL" longname="RPL-U 2+8"/>
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<sku did="0xA71B" name="Raptor Lake" code="RPL" longname="RPL-U 2+4"/>
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<sku did="0xA71C" name="Raptor Lake" code="RPL" longname="RPL-U 1+4"/>
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<sku did="0xA711" name="Raptor Lake" code="RPL" longname="RPL-E 8+0"/>
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<sku did="0xA712" name="Raptor Lake" code="RPL" longname="RPL-E 6+0"/>
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<sku did="0xA713" name="Raptor Lake" code="RPL" longname="RPL-E 4+0"/>
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</info>
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<!-- #################################### -->
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<!-- -->
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<!-- Integrated devices -->
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<!-- -->
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<!-- #################################### -->
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<pci>
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<device name="HOSTCTL" bus="0x00" dev="0x00" fun="0" did="0x4610,0x4630-0x464F,0x4740,0xA700-0xA72F" config="HOSTCTL.hostctl13gen.xml" >
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<subcomponent type="mmiobar" name="MCHBAR" register="MCHBAR" base_field="MCHBAR" size="0x20000" enable_bit="0" desc="Host Memory Mapped Register Range" config="MMIO.mmio13gen.xml" />
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<subcomponent type="mmiobar" name="MCHBARMC1" register="MCHBAR" base_field="MCHBAR" offset="0x10000" size="0x20000" enable_bit="0" desc="Host Memory Mapped Register Range" config="MMIO.mmio13gen.xml" />
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<subcomponent type="mmiobar" name="VTBAR" register="MCHBAR.VTBAR" base_field="BASE" size="0x8000" enable_bit="0" desc="VTD Register Range" config="IOMMU.iommu.xml" />
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<subcomponent type="mmiobar" name="GFXVTBAR" register="MCHBAR.GFXVTBAR" base_field="BASE" size="0x8000" enable_bit="0" desc="GFXVTD Register Range" config="IOMMU.iommu.xml" />
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</device>
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<device name="IGD" vid="0x8086" did="0x4680-0x4682,0x4692,0x4693,0xA780-0xA78B,0xA7A0-0xA7AB" config="IGD.igd0.xml" />
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</pci>
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<msr>
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<definition name="MSR" config="MSR.msr2.xml" />
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</msr>
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<!-- #################################### -->
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<!-- -->
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<!-- Memory ranges -->
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<!-- -->
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<!-- #################################### -->
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<memory>
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<range name="TPM" access="mmio" address="0xFED40000" limit="0xFED4FFFF" config="TPM.tpm12.xml" />
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<range name="TXT" access="mmio" address="0xFED30000" limit="0xFED4FFFF" config="TPM.txt.xml" />
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</memory>
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</configuration>
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