mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
BrentHoltsclaw
114 lines
3.5 KiB
C
114 lines
3.5 KiB
C
/*
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CHIPSEC: Platform Security Assessment Framework
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Copyright (c) 2010-2019, Intel Corporation
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; Version 2.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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You should have received a copy of the GNU General Public License
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along with this program; if not, write to the Free Software
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Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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Contact information:
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chipsec@intel.com
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*/
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#ifndef CHIPSEC_H
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#define CHIPSEC_H
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#define MSR_IA32_BIOS_UPDT_TRIG 0x79
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#define MSR_IA32_BIOS_SIGN_ID 0x8b
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#define IOCTL_NUM 'C'
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#define IOCTL_BASE _IO(IOCTL_NUM, 0)
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#define IOCTL_RDIO _IOWR(IOCTL_NUM, 0x1, int*)
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#define IOCTL_WRIO _IOWR(IOCTL_NUM, 0x2, int*)
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#define IOCTL_RDPCI _IOWR(IOCTL_NUM, 0x3, int*)
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#define IOCTL_WRPCI _IOWR(IOCTL_NUM, 0x4, int*)
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#define IOCTL_RDMSR _IOWR(IOCTL_NUM, 0x5, int*)
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#define IOCTL_WRMSR _IOWR(IOCTL_NUM, 0x6, int*)
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#define IOCTL_CPUID _IOWR(IOCTL_NUM, 0x7, int*)
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#define IOCTL_GET_CPU_DESCRIPTOR_TABLE _IOWR(IOCTL_NUM, 0x8, int*)
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#define IOCTL_HYPERCALL _IOWR(IOCTL_NUM, 0x9, int*)
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#define IOCTL_SWSMI _IOWR(IOCTL_NUM, 0xA, int*)
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#define IOCTL_LOAD_UCODE_PATCH _IOWR(IOCTL_NUM, 0xB, int*)
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#define IOCTL_ALLOC_PHYSMEM _IOWR(IOCTL_NUM, 0xC, int*)
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#define IOCTL_GET_EFIVAR _IOWR(IOCTL_NUM, 0xD, int*)
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#define IOCTL_SET_EFIVAR _IOWR(IOCTL_NUM, 0xE, int*)
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#define IOCTL_RDCR _IOWR(IOCTL_NUM, 0x10, int*)
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#define IOCTL_WRCR _IOWR(IOCTL_NUM, 0x11, int*)
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#define IOCTL_RDMMIO _IOWR(IOCTL_NUM, 0x12, int*)
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#define IOCTL_WRMMIO _IOWR(IOCTL_NUM, 0x13, int*)
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#define IOCTL_VA2PA _IOWR(IOCTL_NUM, 0x14, int*)
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#define IOCTL_MSGBUS_SEND_MESSAGE _IOWR(IOCTL_NUM, 0x15, int*)
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#define IOCTL_FREE_PHYSMEM _IOWR(IOCTL_NUM, 0x16, int*)
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//
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// SoC IOSF Message Bus constants
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//
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#define MSGBUS_BUS 0x0
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#define MSGBUS_DEV 0x0
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#define MSGBUS_FUN 0x0
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#define MCR 0xD0
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#define MDR 0xD4
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#define MCRX 0xD8
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#define MSGBUS_MDR_IN_MASK 0x1
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#define MSGBUS_MDR_OUT_MASK 0x2
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/// if defined debug is enabled
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#define DEBUG
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#ifdef DEBUG
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/// Macro for debug print
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#define dbgprint(format, args...) \
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do { \
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printk(KERN_DEBUG "%s %s %d: "format"\n", program_name, __FUNCTION__, __LINE__, ## args);\
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} while ( 0 )
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#else
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#define dbgprint(format, args...) do {} while( 0 );
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#endif
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#endif
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#ifdef __x86_64__
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typedef u64 physaddr_t;
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#else
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typedef __u32 physaddr_t;
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#endif
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typedef enum {
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CPU_DT_CODE_IDTR = 0x0,
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CPU_DT_CODE_GDTR = 0x1,
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CPU_DT_CODE_LDTR = 0x2,
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} DTR_CODE;
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#pragma pack(1)
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typedef union {
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struct {
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uint32_t low;
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int32_t high;
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} u;
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physaddr_t quadpart;
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} PHYSICAL_ADDRESS;
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#pragma pack()
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#pragma pack(1)
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typedef struct _DESCRIPTOR_TABLE_RECORD {
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uint16_t limit;
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physaddr_t base;
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} DESCRIPTOR_TABLE_RECORD, *PDESCRIPTOR_TABLE_RECORD;
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#pragma pack()
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struct allocated_mem_list {
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physaddr_t pa;
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void *va;
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struct list_head list;
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};
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