mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
BrentHoltsclaw
78 lines
2.7 KiB
C
78 lines
2.7 KiB
C
//
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// Copyright 2016 Google Inc. All Rights Reserved.
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// Author: Thiebaud Weksteen (tweksteen@gmail.com)
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//
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// Copyright (c) 2010-2015, Intel Corporation
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//
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// Licensed under the Apache License, Version 2.0 (the "License");
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// you may not use this file except in compliance with the License.
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// You may obtain a copy of the License at
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//
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// http://www.apache.org/licenses/LICENSE-2.0
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//
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// Unless required by applicable law or agreed to in writing, software
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// distributed under the License is distributed on an "AS IS" BASIS,
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// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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// See the License for the specific language governing permissions and
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// limitations under the License.
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#ifndef _CPU_H
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#define _CPU_H
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extern "C" {
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typedef struct _descriptor_table_record{
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uint16_t limit;
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uint64_t base;
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} descriptor_table_record;
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void WritePCIByte(uint32_t pci_reg, uint16_t data_port, uint8_t byte_value);
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void WritePCIWord(uint32_t pci_reg, uint16_t data_port, uint16_t word_value);
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void WritePCIDword(uint32_t pci_reg, uint16_t data_port, uint32_t dword_value);
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uint8_t ReadPCIByte(uint32_t pci_reg, uint16_t data_port);
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uint16_t ReadPCIWord(uint32_t pci_reg, uint16_t data_port);
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uint32_t ReadPCIDword(uint32_t pci_reg, uint16_t data_port);
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unsigned long ReadCR0(void);
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unsigned long ReadCR2(void);
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unsigned long ReadCR3(void);
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unsigned long ReadCR4(void);
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unsigned long ReadCR8(void);
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void WriteCR0(unsigned long);
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void WriteCR2(unsigned long);
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void WriteCR3(unsigned long);
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void WriteCR4(unsigned long);
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void WriteCR8(unsigned long);
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uint8_t ReadPortByte (uint16_t data_port);
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uint16_t ReadPortWord (uint16_t data_port);
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uint32_t ReadPortDword (uint16_t data_port);
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void WritePortByte (uint8_t byte_value, uint16_t data_port);
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void WritePortWord (uint16_t word_value, uint16_t data_port);
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void WritePortDword (uint32_t dword_value, uint16_t data_port);
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void ReadMSR(uint64_t msr_num, uint64_t* msr_lo, uint64_t* msr_hi);
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void WriteMSR(uint64_t msr_num, uint64_t msr_lo, uint64_t msr_hi);
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void chipCPUID(cpuid_msg_t *cpuid_regs);
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void SWSMI(swsmi_msg_t *swsmi_regs);
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uint64_t hypercall(uint64_t rdi, uint64_t rsi, uint64_t rdx, uint64_t rcx, uint64_t r8, uint64_t r9, uint64_t rax, uint64_t rbx, uint64_t r10, uint64_t r11, uint64_t xmm_buff, uint64_t hypercall_page);
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uint64_t hypercall_page();
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void store_idtr ( descriptor_table_record * address);
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void store_gdtr ( descriptor_table_record * address);
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void store_ldtr ( descriptor_table_record * address);
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void load_idtr ( descriptor_table_record * address);
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void load_gdtr ( descriptor_table_record * address);
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void load_ldtr ( descriptor_table_record * address);
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void load_gdt ( descriptor_table_record * address);
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}
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#endif /* _CPU_H */
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