mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
210 lines
8.4 KiB
Python
210 lines
8.4 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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I/O BAR access (dump, read/write)
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usage:
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>>> get_IO_BAR_base_address( bar_name )
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>>> read_IO_BAR_reg( bar_name, offset, size )
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>>> write_IO_BAR_reg( bar_name, offset, size, value )
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>>> dump_IO_BAR( bar_name )
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"""
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from typing import Tuple, List
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from chipsec.hal import hal_base
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from chipsec.library.exceptions import IOBARNotFoundError
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from chipsec.library.exceptions import CSReadError
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from chipsec.library.registers.io import IO
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DEFAULT_IO_BAR_SIZE = 0x100
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class IOBAR(hal_base.HALBase):
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def __init__(self, cs):
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super(IOBAR, self).__init__(cs)
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#
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# Check if I/O BAR with bar_name has been defined in XML config
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# Use this function to fall-back to hardcoded config in case XML config is not available
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#
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def is_IO_BAR_defined(self, bar_name: str) -> bool:
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is_bar_defined = False
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try:
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_bar = self.cs.register.io.get_def(bar_name)
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if _bar is not None:
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if _bar.register:
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is_bar_defined = self.cs.register.is_defined(_bar.register)
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if not is_bar_defined and _bar.fixed_address:
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is_bar_defined = True
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except KeyError:
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pass
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if not is_bar_defined:
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if self.logger.HAL:
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self.logger.log_warning(f"'{bar_name}' I/O BAR register definition not found in XML config")
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return is_bar_defined
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#
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# Get base address of I/O range by IO BAR name
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#
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def get_IO_BAR_base_address(self, bar_name: str, instance:'PCIObj') -> Tuple[int, int]:
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try:
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bar_def = self.cs.register.io.get_def(bar_name)
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except IndexError:
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raise IOBARNotFoundError(f'IOBARNotFound: {bar_name} is not defined. Check scoping and configuration')
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if not bar_def:
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raise IOBARNotFoundError(f'IOBARNotFound: {bar_name} is not defined. Check scoping and configuration')
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base, size = bar_def.get_base(instance)
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if base:
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return base, size
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empty_base = 0
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if bar_def.register:
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if instance is not None:
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bar_reg = self.cs.register.get_instance_by_name(bar_def.register, instance)
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else:
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bar_reg = self.cs.register.get_list_by_name(bar_def.register)[0]
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if bar_def.base_field:
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base_field = bar_def.base_field
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try:
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base = bar_reg.get_field(base_field, True)
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except Exception:
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pass
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try:
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empty_base = bar_reg.get_field_mask(base_field, True)
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except Exception:
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pass
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else:
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try:
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base = bar_reg.read()
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except Exception:
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pass
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try:
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empty_base = bar_reg.get_mask()
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except Exception:
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pass
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if bar_def.fixed_address and (not base or base == empty_base):
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base = bar_def.fixed_address
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self.logger.log_hal(f'[iobar] Using fixed address for {bar_name}: 0x{base:016X}')
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if bar_def.mask:
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base = base & bar_def.mask
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if bar_def.offset:
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base = base + bar_def.offset
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size = bar_def.size if bar_def.size else DEFAULT_IO_BAR_SIZE
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if not base:
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raise CSReadError(f'IOBAR ({bar_name}) base address is 0 or not defined')
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self.logger.log_hal(f'[iobar] {bar_name}: 0x{base:04X} (size = 0x{size:X})')
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return base, size
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#
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# Read I/O register from I/O range defined by I/O BAR name
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#
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def read_IO_BAR_reg(self, bar_name: str, offset: int, size: int) -> int:
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self.logger.log_hal(f'[iobar] read {bar_name} + 0x{offset:X} ({size:d})')
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(bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
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io_port = bar_base + offset
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if offset > bar_size and self.logger.HAL:
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self.logger.log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
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value = self.cs.hals.io.read(io_port, size)
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return value
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#
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# Write I/O register from I/O range defined by I/O BAR name
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#
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def write_IO_BAR_reg(self, bar_name: str, offset: int, size: int, value: int) -> int:
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(bar_base, bar_size) = self.get_IO_BAR_base_address(bar_name)
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self.logger.log_hal(f'[iobar] write {bar_name} + 0x{offset:X} ({size:d}): 0x{value:X}')
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io_port = bar_base + offset
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if offset > bar_size and self.logger.HAL:
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self.logger.log_warning(f'offset 0x{offset:X} is outside {bar_name} size (0x{size:X})')
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return self.cs.hals.io.write(io_port, value, size)
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#
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# Check if I/O range is enabled by BAR name
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#
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def is_IO_BAR_enabled(self, bar_name: str) -> bool:
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if not self.is_IO_BAR_defined(bar_name):
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return False
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bar = self.cs.register.io.get_def(bar_name)
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is_enabled = True
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if bar.register:
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bar_reg = bar.register
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if bar.enable_field:
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bar_en_field = bar.enable_field
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is_enabled = bar_reg.is_all_field_value(1, bar_en_field)
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return is_enabled
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def list_IO_BARs(self) -> None:
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self.logger.log('')
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self.logger.log('--------------------------------------------------------------------------------')
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self.logger.log(f' {"I/O Range":35} | {"B:D.F":7} | {"Base":16} | {"Size":8} | {"En?":3} | Description')
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self.logger.log('--------------------------------------------------------------------------------')
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for vid in self.cs.Cfg.IO_BARS.keys():
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for dev in self.cs.Cfg.IO_BARS[vid].keys():
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for _bar_name in self.cs.Cfg.IO_BARS[vid][dev].keys():
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bar_name = f'{vid}.{dev}.{_bar_name}'
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if not self.is_IO_BAR_defined(bar_name):
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continue
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_bar = self.cs.Cfg.IO_BARS[vid][dev][_bar_name]
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for instance in _bar.instances:
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(_base, _size) = _bar.get_base(instance)
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if _base is None:
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try:
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(_base, _size) = self.get_IO_BAR_base_address(bar_name, instance)
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except CSReadError as err:
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self.logger.log_hal(f'[iobar] {err}')
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continue
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_en = self.is_IO_BAR_enabled(bar_name)
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if instance.bus is not None:
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bdf = f'{instance.bus:02X}:{instance.dev:02X}.{instance.fun:1X}'
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else:
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bdf = 'fixed'
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self.logger.log(f' {_bar_name:35} | {bdf:7} | {_base:016X} | {_size:08X} | {_en:d} | {_bar.desc}')
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#
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# Read I/O range by I/O BAR name
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#
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def read_IO_BAR(self, bar_name: str, size: int = 1) -> List[int]:
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(range_base, range_size) = self.get_IO_BAR_base_address(bar_name)
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n = range_size // size
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io_ports = []
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for i in range(n):
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io_ports.append(self.cs.hals.io.read(range_base + i * size, size))
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return io_ports
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#
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# Dump I/O range by I/O BAR name
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#
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def dump_IO_BAR(self, bar_name: str, size: int = 1) -> None:
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(range_base, range_size) = self.get_IO_BAR_base_address(bar_name)
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n = range_size // size
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fmt = f'0{size * 2:d}X'
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self.logger.log(f"[iobar] I/O BAR {bar_name}:")
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for i in range(n):
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reg = self.cs.hals.io.read(range_base + i * size, size)
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self.logger.log(f'{size * i:+04X}: {reg:{fmt}}')
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haldata = {"arch":[hal_base.HALBase.MfgIds.Any], 'name': {'iobar': "IOBAR"}}
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