mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
180 lines
7.5 KiB
Python
180 lines
7.5 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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Access to CPU resources (for each CPU thread): Model Specific Registers (MSR), IDT/GDT
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usage:
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>>> read( 0x8B )
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>>> write( 0x79, 0x12345678 )
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>>> get_cpu_thread_count()
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>>> get_IDTR( 0 )
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>>> get_GDTR( 0 )
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>>> dump_Descriptor_Table( 0, DESCRIPTOR_TABLE_CODE_IDTR )
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>>> IDT( 0 )
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>>> GDT( 0 )
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>>> IDT_all()
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>>> GDT_all()
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"""
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from typing import Dict, Tuple, Optional
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from chipsec.library.logger import logger, print_buffer_bytes
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from chipsec.hal.hal_base import HALBase
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DESCRIPTOR_TABLE_CODE_IDTR = 0
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DESCRIPTOR_TABLE_CODE_GDTR = 1
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DESCRIPTOR_TABLE_CODE_LDTR = 2
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MTRR_MEMTYPE_UC = 0x0
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MTRR_MEMTYPE_WC = 0x1
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MTRR_MEMTYPE_WT = 0x4
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MTRR_MEMTYPE_WP = 0x5
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MTRR_MEMTYPE_WB = 0x6
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MemType: Dict[int, str] = {
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MTRR_MEMTYPE_UC: 'Uncacheable (UC)',
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MTRR_MEMTYPE_WC: 'Write Combining (WC)',
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MTRR_MEMTYPE_WT: 'Write-through (WT)',
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MTRR_MEMTYPE_WP: 'Write-protected (WP)',
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MTRR_MEMTYPE_WB: 'Writeback (WB)'
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}
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class Msr(HALBase):
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def __init__(self, cs):
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super(Msr, self).__init__(cs)
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self.topo = None
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# TODO: Move this somewhere else.
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def get_cpu_thread_count(self) -> int:
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if not self.topo:
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self.topo = self.cs.hals.cpu.get_cpu_topology()
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self.logger.log_hal(f'[Msr] # of logical CPUs: {self.topo["threads"]:d}')
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return self.topo['threads']
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def get_cpu_core_count(self) -> int:
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if not self.topo:
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self.topo = self.cs.hals.cpu.get_cpu_topology()
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core_count = len(self.topo['cores'])
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self.logger.log_hal(f'[Msr] # of cores in Package: {core_count:d}')
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return core_count
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##########################################################################################################
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#
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# Read/Write CPU MSRs
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#
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##########################################################################################################
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def read(self, cpu_thread_id: int, msr_addr: int) -> Tuple[int, int]:
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(eax, edx) = self.cs.helper.read_msr(cpu_thread_id, msr_addr)
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] RDMSR( 0x{msr_addr:x} ): EAX = 0x{eax:08X}, EDX = 0x{edx:08X}')
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return (eax, edx)
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def read_msr(self, cpu_thread_id: int, msr_addr: int) -> Tuple[int, int]:
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return self.read(cpu_thread_id, msr_addr)
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def write(self, cpu_thread_id: int, msr_addr: int, eax: int, edx: int) -> None:
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self.cs.helper.write_msr(cpu_thread_id, msr_addr, eax, edx)
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] WRMSR( 0x{msr_addr:x} ): EAX = 0x{eax:08X}, EDX = 0x{edx:08X}')
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return None
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def write_msr(self, cpu_thread_id: int, msr_addr: int, eax: int, edx: int) -> None:
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return self.write(cpu_thread_id, msr_addr, eax, edx)
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##########################################################################################################
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#
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# Get CPU Descriptor Table Registers (IDTR, GDTR, LDTR..)
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#
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##########################################################################################################
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def get_Desc_Table_Register(self, cpu_thread_id: int, code: int) -> Tuple[int, int, int]:
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desc_table = self.cs.helper.get_descriptor_table(cpu_thread_id, code)
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if desc_table is None:
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self.logger.log_hal(f'[msr] Unable to locate CPU Descriptor Table: Descriptor table code = {code:d}')
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return (0, 0, 0)
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return desc_table
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def get_IDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
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(limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_IDTR)
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] IDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
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return (limit, base, pa)
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def get_GDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
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(limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_GDTR)
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] GDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
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return (limit, base, pa)
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def get_LDTR(self, cpu_thread_id: int) -> Tuple[int, int, int]:
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(limit, base, pa) = self.get_Desc_Table_Register(cpu_thread_id, DESCRIPTOR_TABLE_CODE_LDTR)
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] LDTR Limit = 0x{limit:04X}, Base = 0x{base:016X}, Physical Address = 0x{pa:016X}')
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return (limit, base, pa)
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##########################################################################################################
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#
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# Dump CPU Descriptor Tables (IDT, GDT, LDT..)
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#
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##########################################################################################################
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def dump_Descriptor_Table(self, cpu_thread_id: int, code: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
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(limit, _, pa) = self.cs.helper.get_descriptor_table(cpu_thread_id, code)
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dt = self.cs.helper.read_phys_mem(pa, limit + 1)
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total_num = len(dt) // 16
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if (num_entries is None) or (total_num < num_entries):
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num_entries = total_num
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self.logger.log(f'[cpu{cpu_thread_id:d}] Physical Address: 0x{pa:016X}')
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self.logger.log(f'[cpu{cpu_thread_id:d}] # of entries : {total_num:d}')
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self.logger.log(f'[cpu{cpu_thread_id:d}] Contents ({num_entries:d} entries):')
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print_buffer_bytes(dt)
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self.logger.log('--------------------------------------')
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self.logger.log('# segment:offset attributes')
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self.logger.log('--------------------------------------')
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for i in range(0, num_entries):
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offset = (dt[i * 16 + 11] << 56) | (dt[i * 16 + 10] << 48) | (dt[i * 16 + 9] << 40) | (dt[i * 16 + 8] << 32) | (dt[i * 16 + 7] << 24) | (dt[i * 16 + 6] << 16) | (dt[i * 16 + 1] << 8) | dt[i * 16 + 0]
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segsel = (dt[i * 16 + 3] << 8) | dt[i * 16 + 2]
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attr = (dt[i * 16 + 5] << 8) | dt[i * 16 + 4]
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self.logger.log(f'{i:03d} {segsel:04X}:{offset:016X} 0x{attr:04X}')
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return (pa, dt)
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def IDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] IDT:')
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return self.dump_Descriptor_Table(cpu_thread_id, DESCRIPTOR_TABLE_CODE_IDTR, num_entries)
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def GDT(self, cpu_thread_id: int, num_entries: Optional[int] = None) -> Tuple[int, int]:
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self.logger.log_hal(f'[cpu{cpu_thread_id:d}] GDT:')
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return self.dump_Descriptor_Table(cpu_thread_id, DESCRIPTOR_TABLE_CODE_GDTR, num_entries)
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def IDT_all(self, num_entries: Optional[int] = None) -> None:
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for tid in range(self.get_cpu_thread_count()):
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self.IDT(tid, num_entries)
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def GDT_all(self, num_entries: Optional[int] = None) -> None:
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for tid in range(self.get_cpu_thread_count()):
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self.GDT(tid, num_entries)
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haldata = {"arch":[HALBase.MfgIds.Intel], 'name': {'msr': "Msr"}} |