mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
412 lines
17 KiB
Python
412 lines
17 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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Access to Memory (DRAM) Serial Presence Detect (SPD) EEPROM
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References:
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http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf
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http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf
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http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf
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http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf
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https://www.simmtester.com/News/PublicationArticle/184
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https://www.simmtester.com/News/PublicationArticle/153
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https://www.simmtester.com/News/PublicationArticle/101
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http://en.wikipedia.org/wiki/Serial_presence_detect
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"""
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import struct
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from typing import Any, List
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from collections import namedtuple
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from chipsec.hal.hal_base import HALBase
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from chipsec.library.logger import logger, print_buffer_bytes
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SPD_SMBUS_ADDRESS = 0xA0 # A2, A4, A6, A8, AA, AC, AE
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SPD_SMBUS_ADDRESS_DIMM0 = SPD_SMBUS_ADDRESS
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SPD_SMBUS_ADDRESS_DIMM1 = SPD_SMBUS_ADDRESS + 0x2
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SPD_SMBUS_ADDRESS_DIMM2 = SPD_SMBUS_ADDRESS + 0x4
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SPD_SMBUS_ADDRESS_DIMM3 = SPD_SMBUS_ADDRESS + 0x6
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SPD_SMBUS_ADDRESS_DIMM4 = SPD_SMBUS_ADDRESS + 0x8
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SPD_SMBUS_ADDRESS_DIMM5 = SPD_SMBUS_ADDRESS + 0xA
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SPD_SMBUS_ADDRESS_DIMM6 = SPD_SMBUS_ADDRESS + 0xC
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SPD_SMBUS_ADDRESS_DIMM7 = SPD_SMBUS_ADDRESS + 0xE
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MAX_DIMM_SPD_COUNT = 8
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SPD_DIMMS = {}
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for i in range(MAX_DIMM_SPD_COUNT):
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SPD_DIMMS[SPD_SMBUS_ADDRESS + i * 2] = f'DIMM{i:d}'
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SPD_DIMM_ADDRESSES = {}
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for i in range(MAX_DIMM_SPD_COUNT):
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SPD_DIMM_ADDRESSES[f'DIMM{i:d}'] = SPD_SMBUS_ADDRESS + i * 2
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###############################################################################
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#
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# SPD Decode
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#
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# References:
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# http://www.jedec.org/sites/default/files/docs/4_01_02R19.pdf
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# http://www.jedec.org/sites/default/files/docs/4_01_02_10R17.pdf
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# http://www.jedec.org/sites/default/files/docs/4_01_02_11R24.pdf
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# http://www.jedec.org/sites/default/files/docs/4_01_02_12R23A.pdf
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# http://www.simmtester.com/page/news/showpubnews.asp?num=184
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# http://www.simmtester.com/page/news/showpubnews.asp?num=153
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# http://www.simmtester.com/page/news/showpubnews.asp?num=101
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# http://en.wikipedia.org/wiki/Serial_presence_detect
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#
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# @TODO: add decode of other fields
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#
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###############################################################################
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#
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# DDR/DDR2/DDR3/DDR4 SPD
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#
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SPD_OFFSET_DRAM_DEVICE_TYPE = 2 # Fundamental Memory (DRAM) Type
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#
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# DDR SPD
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#
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SPD_OFFSET_DDR_SPD_BYTES = 0
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SPD_OFFSET_DDR_SPD_SIZE = 1
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SPD_OFFSET_DDR_ROW_ADDRESS_COUNT = 3
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SPD_OFFSET_DDR_COL_ADDRESS_COUNT = 4
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SPD_OFFSET_DDR_BANKDS_COUNT = 5
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SPD_OFFSET_DDR_MODULE_WIDTH_LOW = 6
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SPD_OFFSET_DDR_MODULE_WIDTH_HIGH = 7
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SPD_OFFSET_DDR_VOLTAGE_IFACE_LEVEL = 8
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SPD_OFFSET_DDR_CLOCK_FREQUENCY = 9
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SPD_OFFSET_DDR_tAC = 10
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SPD_OFFSET_DDR_DIMM_CONFIGURATION_TYPE = 11
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SPD_OFFSET_DDR_REFRESH_RATE_TYPE = 12
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SPD_OFFSET_DDR_PRIMARY_SDRAM_WIDTH = 13
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SPD_OFFSET_DDR_ECC_SDRAM_WIDTH = 14
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SPD_OFFSET_DDR_tCCD_MIN = 15
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#
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# DDR3 SPD
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#
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SPD_OFFSET_DDR3_SPD_BYTES = 0 # SPD Bytes Written, Device Size, CRC coverage/range
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SPD_OFFSET_DDR3_SPD_REVISION = 1 # SPD Revision
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SPD_OFFSET_DDR3_MODULE_TYPE = 3 # Module Type
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SPD_OFFSET_DDR3_SDRAM_DENSITY_BANKS = 4 # SDRAM Density and Banks
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SPD_OFFSET_DDR3_SDRAM_ADDRESSING = 5 # SDRAM Addressing
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SPD_OFFSET_DDR3_VDD = 6 # Module Nominal Voltage, VDD
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SPD_OFFSET_DDR3_MODULE_ORGANIZATION = 7 # Module Organization
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SPD_OFFSET_DDR3_MEMORY_BUS_WIDTH_ECC = 8 # Module Memory Bus Width
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SPD_OFFSET_DDR3_FTB = 9 # Fine Time Base (FTB) Divident / Divisor
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SPD_OFFSET_DDR3_MTB_DIVIDENT = 10 # Medium Time Base (MTB) Divident
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SPD_OFFSET_DDR3_MTB_DIVISOR = 11 # Medium Time Base (MTB) Divisor
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SPD_OFFSET_DDR3_tCK_MIN = 12 # SDRAM Minimum Cycle Time (tCKmin)
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SPD_OFFSET_DDR3_RESERVED13 = 13 # Reserved
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SPD_OFFSET_DDR3_CAS_LATENCY_LOW = 14 # CAS Latencies Supported, LSB
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SPD_OFFSET_DDR3_CAS_LATENCY_HIGH = 15 # CAS Latencies Supported, MSB
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#
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# DDR4 SPD
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#
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# Base Configuration and DRAM Parameters
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SPD_OFFSET_DDR4_SPD_BYTES = 0 # SPD Bytes Written, Device Size, CRC coverage/range
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SPD_OFFSET_DDR4_SPD_REVISION = 1 # SPD Revision
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SPD_OFFSET_DDR4_MODULE_TYPE = 3 # Module Type
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SPD_OFFSET_DDR4_SDRAM_DENSITY_BANKS = 4 # SDRAM Density and Banks
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SPD_OFFSET_DDR4_SDRAM_ADDRESSING = 5 # SDRAM Addressing
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SPD_OFFSET_DDR4_SDRAM_PACKAGE_TYPE = 6 # SDRAM Package Type
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SPD_OFFSET_DDR4_OPTIONAL_FEATURES = 7 # SDRAM Optional Features
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SPD_OFFSET_DDR4_THERMAL_AND_REFRESH = 8 # SDRAM Thermal and Refresh Options
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SPD_OFFSET_DDR4_OPTIONAL_FEATURES_1 = 9 # Other Optional Features
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SPD_OFFSET_DDR4_RESERVED10 = 10 # Reserved (must be 0x00)
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SPD_OFFSET_DDR4_VDD = 11 # Module Nominal Voltage, VDD
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SPD_OFFSET_DDR4_MODULE_ORGANIZATION = 12 # Module Organization
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SPD_OFFSET_DDR4_MEMORY_BUS_WIDTH_ECC = 13 # Module Memory Bus Width
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SPD_OFFSET_DDR4_MODULE_THERMAL_SENSOR = 14 # Module Thermal Sensor
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SPD_OFFSET_DDR4_MODULE_TYPE_EXTENDED = 15 # Extended Module Type
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#
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# Fundamental Memory Type
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# Ref: http://www.jedec.org/sites/default/files/docs/4_01_02_01R12.pdf
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#
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DRAM_DEVICE_TYPE_FPM_DRAM = 0x1
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DRAM_DEVICE_TYPE_EDO = 0x2
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DRAM_DEVICE_TYPE_PIPELINED_NIBBLE = 0x3
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DRAM_DEVICE_TYPE_SDR = 0x4
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DRAM_DEVICE_TYPE_MULTIPLEXED_ROM = 0x5
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DRAM_DEVICE_TYPE_DDR = 0x7
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DRAM_DEVICE_TYPE_DDR2 = 0x8
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DRAM_DEVICE_TYPE_DDR3 = 0x0B
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DRAM_DEVICE_TYPE_DDR4 = 0x0C
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DRAM_DEVICE_TYPE = {
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DRAM_DEVICE_TYPE_FPM_DRAM: 'Standard Fast Page Mode DRAM',
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DRAM_DEVICE_TYPE_EDO: 'EDO DRAM',
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DRAM_DEVICE_TYPE_PIPELINED_NIBBLE: 'Pipelined Nibble',
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DRAM_DEVICE_TYPE_SDR: 'Sync DRAM (SDRAM)',
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DRAM_DEVICE_TYPE_MULTIPLEXED_ROM: 'Multiplexed ROM',
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DRAM_DEVICE_TYPE_DDR: 'DDR SDRAM',
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DRAM_DEVICE_TYPE_DDR2: 'DDR2 SDRAM',
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DRAM_DEVICE_TYPE_DDR3: 'DDR3 SDRAM',
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DRAM_DEVICE_TYPE_DDR4: 'DDR4 SDRAM'
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}
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MODULE_TYPE_UNDEFINED = 0x0
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MODULE_TYPE_RDIMM = 0x1
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MODULE_TYPE_UDIMM = 0x2
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MODULE_TYPE_SODIMM = 0x3
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MODULE_TYPE_LRDIMM = 0x4
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MODULE_TYPE = {
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MODULE_TYPE_UNDEFINED: 'Undefined',
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MODULE_TYPE_RDIMM: 'Registered Long DIMM',
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MODULE_TYPE_UDIMM: 'Unbuffered Long DIMM',
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MODULE_TYPE_SODIMM: 'Small Outline DIMM',
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MODULE_TYPE_LRDIMM: 'LR-DIMM'
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}
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SPD_REVISION_0_0 = 0x00
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SPD_REVISION_0_7 = 0x07
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SPD_REVISION_0_8 = 0x08
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SPD_REVISION_0_9 = 0x09
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SPD_REVISION_1_0 = 0x10
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SPD_REVISION_1_1 = 0x11
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SPD_REVISION_1_2 = 0x12
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SPD_REVISION_1_3 = 0x13
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def SPD_REVISION(revision: int) -> str:
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return (f'{revision >> 4:d}.{revision & 0xF:d}')
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def dram_device_type_name(dram_type: int) -> str:
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dt_name = DRAM_DEVICE_TYPE[dram_type] if dram_type in DRAM_DEVICE_TYPE else 'unknown'
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return dt_name
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def module_type_name(module_type: int) -> str:
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mt_name = MODULE_TYPE[module_type] if module_type in MODULE_TYPE else 'unknown'
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return mt_name
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SPD_DDR_FORMAT = '=4B'
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class SPD_DDR(namedtuple('SPD_DDR', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
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__slots__ = ()
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def __str__(self) -> str:
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return f"""------------------------------------------------------------------
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SPD DDR
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------------------------------------------------------------------
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[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
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[1] Total number of bytes : 0x{self.TotalBytes:02X}
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[2] DRAM Memory Type : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
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[3] Number of Row Addresses : 0x{self.RowAddressCount:02X}
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------------------------------------------------------------------
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"""
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SPD_DDR2_FORMAT = '=4B'
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class SPD_DDR2(namedtuple('SPD_DDR2', 'SPDBytes TotalBytes DeviceType RowAddressCount')):
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__slots__ = ()
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def __str__(self) -> str:
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return f"""------------------------------------------------------------------
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SPD DDR2
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------------------------------------------------------------------
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[0] Number of SPD bytes written: 0x{self.SPDBytes:02X}
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[1] Total number of bytes : 0x{self.TotalBytes:02X}
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[2] DRAM Memory Type : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
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[3] Number of Row Addresses : 0x{self.RowAddressCount:02X}
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------------------------------------------------------------------
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"""
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SPD_DDR3_FORMAT = '=16B'
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class SPD_DDR3(namedtuple('SPD_DDR3', 'SPDBytes Revision DeviceType ModuleType ChipSize Addressing Voltages ModuleOrg BusWidthECC FTB MTBDivident MTBDivisor tCKMin RsvdD CASLo CASHi')):
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__slots__ = ()
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def __str__(self) -> str:
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return f"""------------------------------------------------------------------
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SPD DDR3
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------------------------------------------------------------------
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[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
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[0x01] SPD Revision : 0x{self.Revision:02X} ({SPD_REVISION(self.Revision)})
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[0x02] DRAM Memory Type : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
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[0x03] Module Type : 0x{self.ModuleType:02X} ({module_type_name(self.ModuleType)})
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[0x04] SDRAM Density and Banks : 0x{self.ChipSize:02X}
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[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
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[0x06] Module Nominal Voltage, VDD : 0x{self.Voltages:02X}
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[0x07] Module Organization : 0x{self.ModuleOrg:02X}
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[0x08] Module Memory Bus Width, ECC : 0x{self.BusWidthECC:02X}
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[0x09] FTB Divident/Divisor : 0x{self.FTB:02X}
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[0x0A] MTB Divident : 0x{self.MTBDivident:02X}
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[0x0B] MTB Divisor : 0x{self.MTBDivisor:02X}
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[0x0C] SDRAM Minimum Cycle Time (tCKmin) : 0x{self.tCKMin:02X}
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[0x0D] Reserved : 0x{self.RsvdD:02X}
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[0x0E] CAS Latencies Supported (LSB) : 0x{self.CASLo:02X}
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[0x0F] CAS Latencies Supported (MSB) : 0x{self.CASHi:02X}
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------------------------------------------------------------------
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"""
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SPD_DDR4_FORMAT = '=16B'
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class SPD_DDR4(namedtuple('SPD_DDR4', 'SPDBytes Revision DeviceType ModuleType Density Addressing PackageType OptFeatures ThermalRefresh OptFeatures1 ReservedA VDD ModuleOrg BusWidthECC ThermSensor ModuleTypeExt')):
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__slots__ = ()
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def __str__(self) -> str:
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return f"""------------------------------------------------------------------
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SPD DDR4
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------------------------------------------------------------------
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Base Configuration and DRAM Parameters
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[0x00] SPD Bytes Written, Device Size, CRC: 0x{self.SPDBytes:02X}
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[0x01] SPD Revision : 0x{self.Revision:02X} ({SPD_REVISION(self.Revision)})
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[0x02] DRAM Memory Type : 0x{self.DeviceType:02X} ({dram_device_type_name(self.DeviceType)})
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[0x03] Module Type : 0x{self.ModuleType:02X} ({module_type_name(self.ModuleType)})
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[0x04] SDRAM Density and Banks : 0x{self.Density:02X}
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[0x05] SDRAM Addressing (Row/Column Bits) : 0x{self.Addressing:02X}
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[0x06] SDRAM Package Type : 0x{self.PackageType:02X}
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[0x07] SDRAM Optional Features : 0x{self.OptFeatures:02X}
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[0x08] SDRAM Thermal and Refresh Options : 0x{self.ThermalRefresh:02X}
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[0x09] Other Optional Features : 0x{self.OptFeatures1:02X}
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[0x0A] Reserved (== 0x00) : 0x{self.ReservedA:02X}
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[0x0B] Module Nominal Voltage, VDD : 0x{self.VDD:02X}
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[0x0C] Module Organization : 0x{self.ModuleOrg:02X}
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[0x0D] Module Memory Bus Width : 0x{self.BusWidthECC:02X}
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[0x0E] Module Thermal Sensor : 0x{self.ThermSensor:02X}
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[0x0F] Extended Module Type : 0x{self.ModuleTypeExt:02X}
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------------------------------------------------------------------
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"""
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###############################################################################
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#
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# Main SPD HAL component class
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#
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###############################################################################
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class SPD: #TODO: Refactor to derive from HALBase.
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def __init__(self, cs):
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self.smbus = cs.hals.smbus
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def read_byte(self, offset: int, device: int = SPD_SMBUS_ADDRESS) -> int:
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return self.smbus.read_byte(device, offset)
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def write_byte(self, offset: int, value: int, device: int = SPD_SMBUS_ADDRESS) -> bool:
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return self.smbus.write_byte(device, offset, value)
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def read_range(self, start_offset: int, size: int, device: int = SPD_SMBUS_ADDRESS) -> bytes:
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return bytes(self.read_byte(start_offset + i, device) for i in range(size))
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def write_range(self, start_offset: int, buffer: bytes, device: int = SPD_SMBUS_ADDRESS) -> bool:
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for i, b in enumerate(buffer):
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self.write_byte(start_offset + i, b, device)
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return True
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def dump_spd_rom(self, device: int = SPD_SMBUS_ADDRESS) -> bytes:
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return self.read_range(0x0, 0x100, device)
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#
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# Decoding certain bytes of DIMM SPD: may be dependent on the DRAM type
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#
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def getDRAMDeviceType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
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dram_type = self.read_byte(SPD_OFFSET_DRAM_DEVICE_TYPE, device)
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logger().log_hal(f'[spd][0x{device:02X}] DRAM Device Type (byte 2): 0x{dram_type:01X}')
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return dram_type
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def getModuleType(self, device: int = SPD_SMBUS_ADDRESS) -> int:
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module_type = self.read_byte(SPD_OFFSET_DDR3_MODULE_TYPE, device)
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logger().log_hal(f'[spd][0x{device:02X}] Module Type (byte 3): 0x{module_type:01X}')
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return module_type
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def isECC(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
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device_type = self.getDRAMDeviceType(device)
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ecc_supported = False
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ecc_off = 0
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ecc = None
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if DRAM_DEVICE_TYPE_DDR3 == device_type:
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ecc_off = SPD_OFFSET_DDR3_MEMORY_BUS_WIDTH_ECC
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ecc = self.read_byte(ecc_off, device)
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ecc_supported = (0xB == ecc)
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elif DRAM_DEVICE_TYPE_DDR4 == device_type:
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ecc_off = SPD_OFFSET_DDR4_MEMORY_BUS_WIDTH_ECC
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ecc = self.read_byte(ecc_off, device)
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ecc_supported = (0xB == ecc)
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elif DRAM_DEVICE_TYPE_DDR == device_type or DRAM_DEVICE_TYPE_DDR2 == device_type:
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ecc_off = SPD_OFFSET_DDR_DIMM_CONFIGURATION_TYPE
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ecc = self.read_byte(ecc_off, device)
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ecc_supported = (0x2 == ecc)
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ecc_width = self.read_byte(SPD_OFFSET_DDR_ECC_SDRAM_WIDTH, device)
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logger().log_hal(f'[spd][0x{device:02X}] DDR/DDR2 ECC width (byte {SPD_OFFSET_DDR_ECC_SDRAM_WIDTH:d}): 0x{ecc_width:02X}')
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if logger().HAL:
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if ecc is None:
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logger().log(f'[spd][0x{device:02X}] Unable to determine ECC support')
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else:
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not_str = '' if ecc_supported else 'not '
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logger().log(f'[spd][0x{device:02X}] ECC is {not_str}supported by the DIMM (byte {ecc_off:d} = 0x{ecc:02X})')
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return ecc_supported
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def detect(self) -> List[int]:
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_dimms = []
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for d in SPD_DIMMS:
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if self.isSPDPresent(d):
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_dimms.append(d)
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if logger().HAL:
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logger().log('Detected the following SPD devices:')
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for _dimm in _dimms:
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logger().log(f"{SPD_DIMMS[_dimm]}: 0x{_dimm:02X}")
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return _dimms
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def isSPDPresent(self, device: int = SPD_SMBUS_ADDRESS) -> bool:
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device_type = self.getDRAMDeviceType(device)
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is_spd_present = (device_type != 0xFF)
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not_str = '' if is_spd_present else 'not '
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logger().log_hal(f'[spd][0x{device:02X}] Detecting SPD.. {not_str}found (DRAM memory type = 0x{device_type:X})')
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return is_spd_present
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def decode(self, device: int = SPD_SMBUS_ADDRESS) -> None:
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spd: Any = None
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device_type = self.getDRAMDeviceType(device)
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spd_buffer = self.dump_spd_rom(device)
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logger().log(f'[spd][0x{device:02X}] Serial Presence Detect (SPD) EEPROM contents:')
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print_buffer_bytes(spd_buffer)
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if DRAM_DEVICE_TYPE_DDR == device_type:
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spd = SPD_DDR(*struct.unpack_from(SPD_DDR_FORMAT, spd_buffer))
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elif DRAM_DEVICE_TYPE_DDR2 == device_type:
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spd = SPD_DDR2(*struct.unpack_from(SPD_DDR2_FORMAT, spd_buffer))
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elif DRAM_DEVICE_TYPE_DDR3 == device_type:
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spd = SPD_DDR3(*struct.unpack_from(SPD_DDR3_FORMAT, spd_buffer))
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elif DRAM_DEVICE_TYPE_DDR4 == device_type:
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spd = SPD_DDR4(*struct.unpack_from(SPD_DDR4_FORMAT, spd_buffer))
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else:
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logger().log_warning('[spd] Unsupported SPD format')
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if spd is not None:
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logger().log(str(spd))
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haldata = {"arch":[HALBase.MfgIds.Any], 'name': {'spd': "SPD"}}
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