mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Frinzell, Aaron
117 lines
4.4 KiB
Python
117 lines
4.4 KiB
Python
# -*- coding: utf-8 -*-
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# Copyright (c) 2020 Intel Corporation
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# SPDX-License-Identifier: GPL-2.0-only
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#
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# This file incorporates work covered by the following copyright and
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# permission notice:
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#
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# Copyright (c) 2014 Anders Høst
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# Copyright (c) 2018 Anders Høst
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#
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# Permission is hereby granted, free of charge, to any person obtaining a copy of
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# this software and associated documentation files (the "Software"), to deal in
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# the Software without restriction, including without limitation the rights to
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# use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of
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# the Software, and to permit persons to whom the Software is furnished to do so,
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# subject to the following conditions:
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#
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# The above copyright notice and this permission notice shall be included in all
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# copies or substantial portions of the Software.
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#
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# THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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# IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS
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# FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR
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# COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER
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# IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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# CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
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import mmap
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import platform
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from collections.abc import Callable, Generator
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from ctypes import CFUNCTYPE, POINTER, Structure, addressof, c_uint32, c_void_p, sizeof
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from typing import Tuple
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from chipsec.library.logger import logger
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# Posix x86_64:
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# Three first call registers : RDI, RSI, RDX
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# Volatile registers : RAX, RCX, RDX, RSI, RDI, R8-11
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# cdecl 32 bit:
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# Three first call registers : Stack (%esp)
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# Volatile registers : EAX, ECX, EDX
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_POSIX_64_OPC = bytes((
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0x53, # push %rbx
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0x89, 0xf0, # mov %esi,%eax
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0x89, 0xd1, # mov %edx,%ecx
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0x0f, 0xa2, # cpuid
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0x89, 0x07, # mov %eax,(%rdi)
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0x89, 0x5f, 0x04, # mov %ebx,0x4(%rdi)
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0x89, 0x4f, 0x08, # mov %ecx,0x8(%rdi)
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0x89, 0x57, 0x0c, # mov %edx,0xc(%rdi)
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0x5b, # pop %rbx
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0xc3 # retq
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))
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_CDECL_32_OPC = bytes((
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0x53, # push %ebx
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0x57, # push %edi
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0x8b, 0x7c, 0x24, 0x0c, # mov 0xc(%esp),%edi
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0x8b, 0x44, 0x24, 0x10, # mov 0x10(%esp),%eax
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0x8b, 0x4c, 0x24, 0x14, # mov 0x14(%esp),%ecx
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0x0f, 0xa2, # cpuid
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0x89, 0x07, # mov %eax,(%edi)
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0x89, 0x5f, 0x04, # mov %ebx,0x4(%edi)
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0x89, 0x4f, 0x08, # mov %ecx,0x8(%edi)
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0x89, 0x57, 0x0c, # mov %edx,0xc(%edi)
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0x5f, # pop %edi
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0x5b, # pop %ebx
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0xc3 # ret
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))
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is_64bit = sizeof(c_void_p) == 8
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class CPUID_struct(Structure):
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_fields_ = [(r, c_uint32) for r in ("eax", "ebx", "ecx", "edx")]
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class CPUID:
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def __init__(self) -> None:
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if platform.machine() not in ("AMD64", "x86_64", "x86", "i686"):
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raise SystemError("Only available for x86")
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code: bytes = _POSIX_64_OPC if is_64bit else _CDECL_32_OPC
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self.addr = mmap.mmap(-1, mmap.PAGESIZE, flags=mmap.MAP_PRIVATE, prot=mmap.PROT_READ | mmap.PROT_WRITE | mmap.PROT_EXEC)
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self.addr.write(code)
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func_type = CFUNCTYPE(None, POINTER(CPUID_struct), c_uint32, c_uint32)
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self.fp = c_void_p.from_buffer(self.addr)
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self.func_ptr: Callable[[CPUID_struct, int, int], None] = func_type(addressof(self.fp))
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def __call__(self, eax: int, ecx: int = 0) -> Tuple[int, int, int, int]:
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struct = CPUID_struct()
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self.func_ptr(struct, eax, ecx)
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return struct.eax, struct.ebx, struct.ecx, struct.edx
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def __del__(self) -> None:
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del self.fp
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self.addr.close()
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if __name__ == "__main__":
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def valid_inputs() -> Generator[Tuple[int, Tuple[int, int, int, int]], None, None]:
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cpuid = CPUID()
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for eax in (0x0, 0x80000000):
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highest, _, _, _ = cpuid(eax)
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while eax <= highest:
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regs = cpuid(eax)
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yield (eax, regs)
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eax += 1
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logger().log(" ".join(x.ljust(8) for x in ("CPUID", "A", "B", "C", "D")).strip())
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for eax, regs in valid_inputs():
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reg_string = " ".join(f"{reg:08X}" for reg in regs)
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logger().log(f'{eax:08X} {reg_string}')
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