mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
78 lines
3.3 KiB
Python
78 lines
3.3 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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The msr command allows direct access to read and write MSRs.
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>>> chipsec_util msr <msr> [eax] [edx] [thread_id]
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Examples:
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>>> chipsec_util msr 0x3A
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>>> chipsec_util msr 0x3A 0x0
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>>> chipsec_util msr 0x8B 0x0 0x0 0x0
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"""
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from chipsec.command import BaseCommand, toLoad
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from argparse import ArgumentParser
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# CPU Model Specific Registers
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class MSRCommand(BaseCommand):
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def requirements(self) -> toLoad:
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return toLoad.Driver
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def parse_arguments(self) -> None:
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parser = ArgumentParser(prog='chipsec_util msr', usage=__doc__)
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parser.add_argument('msr_addr', type=lambda x: int(x, 0), metavar='<msr>', help='MSR address')
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parser.add_argument('msr_input1', type=lambda x: int(x, 0), metavar='MSR Value', nargs='?', default=None, help='EAX (Low)')
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parser.add_argument('msr_input2', type=lambda x: int(x, 0), metavar='MSR Value', nargs='?', default=None, help='EDX (High)')
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parser.add_argument('thread_id', type=lambda x: int(x, 0), metavar='Thread ID', nargs='?', default=None, help='Thread ID')
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parser.parse_args(self.argv, namespace=self)
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def run(self):
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if self.msr_input1 is None:
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for tid in range(self.cs.hals.msr.get_cpu_thread_count()):
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(eax, edx) = self.cs.hals.msr.read_msr(tid, self.msr_addr)
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val64 = ((edx << 32) | eax)
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self.logger.log("[CHIPSEC] CPU{:d}: RDMSR( 0x{:x} ) = {:016X} (EAX={:08X}, EDX={:08X})".format(tid, self.msr_addr, val64, eax, edx))
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elif self.msr_input2 is None:
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cpu_thread_id = self.msr_input1
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(eax, edx) = self.cs.hals.msr.read_msr(cpu_thread_id, self.msr_addr)
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val64 = ((edx << 32) | eax)
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self.logger.log("[CHIPSEC] CPU{:d}: RDMSR( 0x{:x} ) = {:016X} (EAX={:08X}, EDX={:08X})".format(cpu_thread_id, self.msr_addr, val64, eax, edx))
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else:
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eax = self.msr_input1
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edx = self.msr_input2
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val64 = ((edx << 32) | eax)
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if self.thread_id is None:
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self.logger.log("[CHIPSEC] All CPUs: WRMSR( 0x{:x} ) = {:016X}".format(self.msr_addr, val64))
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for tid in range(self.cs.hals.msr.get_cpu_thread_count()):
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self.cs.hals.msr.write_msr(tid, self.msr_addr, eax, edx)
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else:
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cpu_thread_id = self.thread_id
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self.logger.log("[CHIPSEC] CPU{:d}: WRMSR( 0x{:x} ) = {:016X}".format(cpu_thread_id, self.msr_addr, val64))
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self.cs.hals.msr.write_msr(cpu_thread_id, self.msr_addr, eax, edx)
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commands = {'msr': MSRCommand}
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