mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
1259e568de
Signed-off-by: Nathaniel Mitchell <nathaniel.p.mitchell@intel.com>
196 lines
10 KiB
Python
196 lines
10 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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The pci command can enumerate PCI/PCIe devices, enumerate expansion ROMs and allow direct access to PCI configuration registers via bus/device/function.
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>>> chipsec_util pci enumerate
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>>> chipsec_util pci read <bus> <device> <function> <offset> [width]
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>>> chipsec_util pci write <bus> <device> <function> <offset> <width> <value>
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>>> chipsec_util pci dump [<bus>] [<device>] [<function>]
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>>> chipsec_util pci xrom [<bus>] [<device>] [<function>] [xrom_address]
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>>> chipsec_util pci cmd [mask] [class] [subclass]
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Examples:
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>>> chipsec_util pci enumerate
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>>> chipsec_util pci read 0 0 0 0x00
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>>> chipsec_util pci read 0 0 0 0x88 byte
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>>> chipsec_util pci write 0 0x1F 0 0xDC 1 0x1
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>>> chipsec_util pci write 0 0 0 0x98 dword 0x004E0040
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>>> chipsec_util pci dump
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>>> chipsec_util pci dump 0 0 0
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>>> chipsec_util pci xrom
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>>> chipsec_util pci xrom 3 0 0 0xFEDF0000
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>>> chipsec_util pci cmd
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>>> chipsec_util pci cmd 1
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"""
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from chipsec.command import BaseCommand, toLoad
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from chipsec.library.logger import pretty_print_hex_buffer
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from argparse import ArgumentParser
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from chipsec_util import get_option_width, is_option_valid_width, CMD_OPTS_WIDTH
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from chipsec.library.pci import PCI as pcilib
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# PCIe Devices and Configuration Registers
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class PCICommand(BaseCommand):
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def requirements(self) -> toLoad:
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return toLoad.Driver
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def parse_arguments(self) -> None:
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parser = ArgumentParser(prog='chipsec_util pci', usage=__doc__)
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subparsers = parser.add_subparsers()
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parser_enumerate = subparsers.add_parser('enumerate')
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parser_enumerate.set_defaults(func=self.pci_enumerate)
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parser_read = subparsers.add_parser('read')
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parser_read.add_argument('bus', type=lambda x: int(x, 16), help='Bus (hex)')
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parser_read.add_argument('device', type=lambda x: int(x, 16), help='Device (hex)')
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parser_read.add_argument('function', type=lambda x: int(x, 16), help='Function (hex)')
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parser_read.add_argument('offset', type=lambda x: int(x, 16), help='Offset (hex)')
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parser_read.add_argument('size', type=str, default=None, nargs='?', help='Width')
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parser_read.set_defaults(func=self.pci_read)
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parser_write = subparsers.add_parser('write')
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parser_write.add_argument('bus', type=lambda x: int(x, 16), help='Bus (hex)')
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parser_write.add_argument('device', type=lambda x: int(x, 16), help='Device (hex)')
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parser_write.add_argument('function', type=lambda x: int(x, 16), help='Function (hex)')
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parser_write.add_argument('offset', type=lambda x: int(x, 16), help='Offset (hex)')
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parser_write.add_argument('size', type=str, help='Width')
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parser_write.add_argument('value', type=lambda x: int(x, 16), help='Value (hex)')
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parser_write.set_defaults(func=self.pci_write)
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parser_dump = subparsers.add_parser('dump')
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parser_dump.add_argument('bus', type=lambda x: int(x, 16), nargs='?', default=None, help='Bus (hex)')
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parser_dump.add_argument('device', type=lambda x: int(x, 16), nargs='?', default=None, help='Device (hex)')
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parser_dump.add_argument('function', type=lambda x: int(x, 16), nargs='?', default=None, help='Function (hex)')
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parser_dump.set_defaults(func=self.pci_dump)
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parser_xrom = subparsers.add_parser('xrom')
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parser_xrom.add_argument('bus', type=lambda x: int(x, 16), nargs='?', default=None, help='Bus (hex)')
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parser_xrom.add_argument('device', type=lambda x: int(x, 16), nargs='?', default=None, help='Device (hex)')
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parser_xrom.add_argument('function', type=lambda x: int(x, 16), nargs='?', default=None, help='Function (hex)')
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parser_xrom.add_argument('xrom_addr', type=lambda x: int(x, 16), nargs='?', default=None, help='XROM Address (hex)')
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parser_xrom.set_defaults(func=self.pci_xrom)
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parser_cmd = subparsers.add_parser('cmd')
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parser_cmd.add_argument('cmd_mask', type=lambda x: int(x, 16), default=0xFFFF, nargs='?', help='Mask (hex)')
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parser_cmd.add_argument('pci_class', type=lambda x: int(x, 16), default=None, nargs='?', help='Class (hex)')
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parser_cmd.add_argument('pci_sub_class', type=lambda x: int(x, 16), default=None, nargs='?', help='Subclass (hex)')
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parser_cmd.set_defaults(func=self.pci_cmd)
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parser.parse_args(self.argv, namespace=self)
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def pci_enumerate(self):
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self.logger.log("[CHIPSEC] Enumerating available PCIe devices...")
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pcilib.print_pci_devices(self.cs.hals.pci.enumerate_devices())
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def pci_dump(self):
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if self.bus is not None:
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if self.device is not None and self.function is not None:
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devices = [(self.bus, self.device, self.function, 0x0000, 0x0000, 0x0000)]
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else:
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devices = self.cs.hals.pci.enumerate_devices(self.bus, self.device, self.function)
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for (_bus, _device, _function, _vid, _did, _rid) in devices:
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self.logger.log("[CHIPSEC] PCI device {:02X}:{:02X}.{:02X} configuration:".format(_bus, _device, _function))
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cfg_buf = self.cs.hals.pci.dump_pci_config(_bus, _device, _function)
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pretty_print_hex_buffer(cfg_buf)
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else:
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self.logger.log("[CHIPSEC] Dumping configuration of available PCI devices...")
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self.cs.hals.pci.print_pci_config_all()
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def pci_xrom(self):
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if self.bus is not None:
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if self.device is not None and self.function is not None:
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devices = [(self.bus, self.device, self.function, 0x0000, 0x0000, 0x000)]
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else:
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devices = self.cs.hals.pci.enumerate_devices(self.bus, self.device, self.function)
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for (_bus, _device, _function, _vid, _did, _rid) in devices:
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self.logger.log("[CHIPSEC] Locating PCI expansion ROM (XROM) of {:02X}:{:02X}.{:02X}...".format(_bus, _device, _function))
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exists, xrom = self.cs.hals.pci.find_XROM(_bus, _device, _function, True, True, self.xrom_addr)
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if exists:
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self.logger.log("[CHIPSEC] Found XROM of {:02X}:{:02X}.{:02X}".format(_bus, _device, _function))
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if xrom is not None:
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self.logger.log("[CHIPSEC] XROM enabled = {:d}, base = 0x{:08X}, size = 0x{:08X}".format(xrom.en, xrom.base, xrom.size))
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if xrom.header is not None:
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self.logger.log("[CHIPSEC] XROM header: {}".format(xrom.header))
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else:
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self.logger.log("[CHIPSEC] Couldn't find XROM of {:02X}:{:02X}.{:02X}".format(_bus, _device, _function))
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else:
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self.logger.log("[CHIPSEC] Enumerating PCI expansion ROMs...")
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_xroms = self.cs.hals.pci.enumerate_xroms(True, True, self.xrom_addr)
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self.logger.log("[CHIPSEC] found {:d} PCI expansion ROMs".format(len(_xroms)))
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if len(_xroms) > 0:
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pcilib.print_pci_XROMs(_xroms)
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def pci_read(self):
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width = 4
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if self.size is not None:
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width = get_option_width(self.size) if is_option_valid_width(self.size) else int(self.size, 16)
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if 1 == width:
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pci_value = self.cs.hals.pci.read_byte(self.bus, self.device, self.function, self.offset)
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elif 2 == width:
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pci_value = self.cs.hals.pci.read_word(self.bus, self.device, self.function, self.offset)
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elif 4 == width:
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pci_value = self.cs.hals.pci.read_dword(self.bus, self.device, self.function, self.offset)
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else:
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self.logger.log_error("Width should be one of {}".format(CMD_OPTS_WIDTH))
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return
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self.logger.log("[CHIPSEC] PCI {:02X}:{:02X}.{:02X} + 0x{:02X}: 0x{:X}".format(self.bus, self.device, self.function, self.offset, pci_value))
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def pci_write(self):
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width = get_option_width(self.size) if is_option_valid_width(self.size) else int(self.size, 16)
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if 1 == width:
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self.cs.hals.pci.write_byte(self.bus, self.device, self.function, self.offset, self.value)
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elif 2 == width:
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self.cs.hals.pci.write_word(self.bus, self.device, self.function, self.offset, self.value)
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elif 4 == width:
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self.cs.hals.pci.write_dword(self.bus, self.device, self.function, self.offset, self.value)
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else:
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self.logger.log_error("Width should be one of {}".format(CMD_OPTS_WIDTH))
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return
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self.logger.log("[CHIPSEC] Write 0x{:X} to PCI {:02X}:{:02X}.{:02X} + 0x{:02X}".format(self.value, self.bus, self.device, self.function, self.offset))
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def pci_cmd(self):
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self.logger.log('BDF | VID:DID | CMD | CLS | Sub CLS')
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self.logger.log('------------------------------------------')
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for (b, d, f, vid, did, rid) in self.cs.hals.pci.enumerate_devices():
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dev_cls = self.cs.hals.pci.read_byte(b, d, f, pcilib.PCI_HDR_CLS_OFF)
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if self.pci_class is not None and (dev_cls != self.pci_class):
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continue
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dev_sub_cls = self.cs.hals.pci.read_byte(b, d, f, pcilib.PCI_HDR_SUB_CLS_OFF)
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if self.pci_sub_class is not None and (dev_sub_cls != self.pci_sub_class):
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continue
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cmd_reg = self.cs.hals.pci.read_word(b, d, f, pcilib.PCI_HDR_CMD_OFF)
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if (cmd_reg & self.cmd_mask) == 0:
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continue
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self.logger.log('{:02X}:{:02X}.{:X} | {:04X}:{:04X} | {:04X} | {:02X} | {:02X}'.format(b, d, f, vid, did, cmd_reg, dev_cls, dev_sub_cls))
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commands = {'pci': PCICommand}
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