mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Nathaniel Mitchell
180 lines
6.2 KiB
Python
180 lines
6.2 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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Access to message bus (IOSF sideband) interface registers on Intel SoCs
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References:
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- Intel(R) Atom(TM) Processor D2000 and N2000 Series Datasheet, Volume 2, July 2012, Revision 003
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http://www.intel.com/content/dam/doc/datasheet/atom-d2000-n2000-vol-2-datasheet.pdf (section 1.10.2)
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usage:
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>>> msgbus_reg_read( port, register )
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>>> msgbus_reg_write( port, register, data )
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>>> msgbus_read_message( port, register, opcode )
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>>> msgbus_write_message( port, register, opcode, data )
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>>> msgbus_send_message( port, register, opcode, data )
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"""
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from typing import Optional
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from chipsec.hal import hal_base
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#
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# IOSF Message bus message opcodes
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# Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
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#
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class MessageBusOpcode:
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MB_OPCODE_MMIO_READ = 0x00
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MB_OPCODE_MMIO_WRITE = 0x01
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MB_OPCODE_IO_READ = 0x02
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MB_OPCODE_IO_WRITE = 0x03
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MB_OPCODE_CFG_READ = 0x04
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MB_OPCODE_CFG_WRITE = 0x05
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MB_OPCODE_CR_READ = 0x06
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MB_OPCODE_CR_WRITE = 0x07
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MB_OPCODE_REG_READ = 0x10
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MB_OPCODE_REG_WRITE = 0x11
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MB_OPCODE_ESRAM_READ = 0x12
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MB_OPCODE_ESRAM_WRITE = 0x13
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#
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# IOSF Message bus unit ports
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# Reference: http://lxr.free-electrons.com/source/arch/x86/include/asm/iosf_mbi.h
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# @TODO: move these to per-platform XML config?
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#
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class MessageBusPort_Atom:
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UNIT_AUNIT = 0x00
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UNIT_SMC = 0x01
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UNIT_CPU = 0x02
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UNIT_BUNIT = 0x03
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UNIT_PMC = 0x04
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UNIT_GFX = 0x06
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UNIT_SMI = 0x0C
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UNIT_USB = 0x43
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UNIT_SATA = 0xA3
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UNIT_PCIE = 0xA6
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class MessageBusPort_Quark:
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UNIT_HBA = 0x00
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UNIT_HB = 0x03
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UNIT_RMU = 0x04
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UNIT_MM = 0x05
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UNIT_SOC = 0x31
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class MsgBus(hal_base.HALBase):
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def __init__(self, cs):
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super(MsgBus, self).__init__(cs)
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self.instance = 0
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self.p2sbHide = None
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self.get_registers()
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def get_registers(self):
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self.msg_ctl_reg = self.cs.register.get_instance_by_name('8086.P2SBC.MSG_CTRL_REG', self.instance)
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self.msg_ctl_reg_ext = self.cs.register.get_instance_by_name('8086.P2SBC.MSG_CTRL_REG_EXT', self.instance)
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self.msg_data_reg = self.cs.register.get_instance_by_name('8086.P2SBC.MSG_DATA_REG', self.instance)
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def __MB_MESSAGE_MCR(self, port: int, reg: int, opcode: int) -> int:
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self.msg_ctl_reg.set_value(0x0)
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self.msg_ctl_reg.set_field('MESSAGE_WR_BYTE_ENABLES', 0xF)
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self.msg_ctl_reg.set_field('MESSAGE_ADDRESS_OFFSET', reg)
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self.msg_ctl_reg.set_field('MESSAGE_PORT', port)
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self.msg_ctl_reg.set_field('MESSAGE_OPCODE', opcode)
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return self.msg_ctl_reg.value
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def __MB_MESSAGE_MCRX(self, reg: int) -> int:
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self.msg_ctl_reg_ext.set_value(0x0)
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mcrx = self.msg_ctl_reg_ext.set_field('MESSAGE_ADDRESS_OFFSET_EXT', reg >> 8)
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return mcrx
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def __MB_MESSAGE_MDR(self, data: int) -> int:
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self.msg_data_reg.set_value(0x0)
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mdr = self.msg_data_reg.set_field('MESSAGE_DATA', data)
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return mdr
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#
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# Issues read message on the message bus
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#
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def msgbus_read_message(self, port: int, register: int, opcode: int) -> Optional[int]:
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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self.logger.log_hal(f'[msgbus] Read: port 0x{port:02X} + 0x{register:08X} (op = 0x{opcode:02X})')
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self.logger.log_hal(f'[msgbus] MCR = 0x{mcr:08X}, MCRX = 0x{mcrx:08X}')
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mdr_out = self.cs.helper.msgbus_send_read_message(mcr, mcrx)
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self.logger.log_hal(f'[msgbus] < 0x{mdr_out:08X}')
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return mdr_out
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#
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# Issues write message on the message bus
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#
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def msgbus_write_message(self, port: int, register: int, opcode: int, data: int) -> None:
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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mdr = self.__MB_MESSAGE_MDR(data)
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self.logger.log_hal(f'[msgbus] Write: port 0x{port:02X} + 0x{register:08X} (op = 0x{opcode:02X}) < data = 0x{data:08X}')
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self.logger.log_hal(f'[msgbus] MCR = 0x{mcr:08X}, MCRX = 0x{mcrx:08X}, MDR = 0x{mdr:08X}')
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return self.cs.helper.msgbus_send_write_message(mcr, mcrx, mdr)
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#
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# Issues generic message on the message bus
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#
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def msgbus_send_message(self, port: int, register: int, opcode: int, data: Optional[int] = None) -> Optional[int]:
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mcr = self.__MB_MESSAGE_MCR(port, register, opcode)
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mcrx = self.__MB_MESSAGE_MCRX(register)
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mdr = None if data is None else self.__MB_MESSAGE_MDR(data)
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self.logger.log_hal(f'[msgbus] message: port 0x{port:02X} + 0x{register:08X} (op = 0x{opcode:02X})')
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if data is not None:
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self.logger.log_hal(f'[msgbus] data = 0x{data:08X}')
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self.logger.log_hal(f'[msgbus] MCR = 0x{mcr:08X}, MCRX = 0x{mcrx:08X}, MDR = 0x{mdr:08X}')
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mdr_out = self.cs.helper.msgbus_send_message(mcr, mcrx, mdr)
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self.logger.log_hal(f'[msgbus] < 0x{mdr_out:08X}')
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return mdr_out
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#
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# Message bus register read/write
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#
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def msgbus_reg_read(self, port: int, register: int) -> Optional[int]:
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return self.msgbus_read_message(port, register, MessageBusOpcode.MB_OPCODE_REG_READ)
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def msgbus_reg_write(self, port: int, register: int, data: int) -> None:
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return self.msgbus_write_message(port, register, MessageBusOpcode.MB_OPCODE_REG_WRITE, data)
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haldata = {"arch": [hal_base.HALBase.MfgIds.Intel], 'name': {'msgbus': "MsgBus"}}
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