mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
William Leara
79f81bbb7e
This commit fixes whitespace errors from checkers W291,W292,W293,W391. They were found by running "flake8 ." from the root directory. These are errors defined by "pycodestyle", and have no functional impact to the source. This is simply fixing whitespace as defined by CHIPSEC's .flake8 configuration. background: https://www.flake8rules.com/rules/W291.html https://www.flake8rules.com/rules/W292.html https://www.flake8rules.com/rules/W293.html https://www.flake8rules.com/rules/W391.html tool versions: flake8 v7.3.0, python v3.13.11 Signed-off-by: William Leara <william.leara@dell.com>
107 lines
3.7 KiB
Python
107 lines
3.7 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2018, Eclypsium, Inc.
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# Copyright (c) 2019-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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"""
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This module checks if memory configuration is locked to protect SMM
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Reference:
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- https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c
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- https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h
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This module checks the following:
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- LT_LOCK_MEMORY MSR (0x2E7) - Bit [0]
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The module returns the following results:
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- **FAILED** : LT_LOCK_MEMORY[0] is not set
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- **PASSED** : LT_LOCK_MEMORY[0] is set
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- **ERROR** : Problem reading LT_LOCK_MEMORY values
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Usage:
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``chipsec_main -m common.memlock``
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Example:
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>>> chipsec_main.py -m common.memlock
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Registers used:
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- LT_LOCK_MEMORY
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.. note::
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- This module will not run on Atom based platforms.
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"""
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from chipsec.module_common import BaseModule, HWCONFIG
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from chipsec.library.returncode import ModuleResult
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from chipsec.library.exceptions import HWAccessViolationError
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from typing import List
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TAGS = [HWCONFIG]
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METADATA_TAGS = ['OPENSOURCE', 'IA', 'COMMON', 'MEMLOCK']
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_MODULE_NAME = 'memlock'
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class memlock(BaseModule):
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def __init__(self):
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BaseModule.__init__(self)
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self.is_read_error = False
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self.cs.set_scope({
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"LT_LOCK_MEMORY": "8086.MSR",
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})
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def is_supported(self) -> bool:
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# Workaround for Atom based processors. Accessing this MSR on these systems
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# causes a GP fault and can't be caught in UEFI Shell.
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if not self.cs.is_atom():
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if self.cs.register.has_field('LT_LOCK_MEMORY', 'LT_LOCK'):
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return True
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else:
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self.logger.log_important("'LT_LOCK_MEMORY.LT_LOCK' not defined for platform. Skipping module.")
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else:
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self.logger.log_important('Found an Atom based platform. Skipping module.')
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return False
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def check_LT_LOCK_MEMORY(self) -> bool:
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self.logger.log('[*] Checking LT_LOCK_MEMORY status')
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ltlockreg = self.cs.register.get_list_by_name('LT_LOCK_MEMORY')
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try:
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ltlockreg.read_and_verbose_print()
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except HWAccessViolationError:
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self.logger.log_important('Could not read LT_LOCK_MEMORY')
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self.is_read_error = True
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return False
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return ltlockreg.is_all_field_value(0, 'LT_LOCK')
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def run(self, module_argv: List[str]) -> int:
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self.logger.start_test('Check LT_LOCK_MEMORY')
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check_LT_LOCK_MEMORY_test_fail = self.check_LT_LOCK_MEMORY()
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if self.is_read_error:
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self.logger.log_error('There was a problem reading LT_LOCK_MEMORY.')
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self.logger.log_important('Possible the environment or a platform feature is preventing these reads.')
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self.res = ModuleResult.ERROR
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self.result.setStatusBit(self.result.status.ACCESS_RW)
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elif check_LT_LOCK_MEMORY_test_fail is True:
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self.logger.log_failed('LT_LOCK_MEMORY.LT_LOCK bit is not configured correctly')
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self.res = ModuleResult.FAILED
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self.result.setStatusBit(self.result.status.LOCKS)
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else:
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self.logger.log_passed('LT_LOCK_MEMORY.LT_LOCK bit is set')
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self.res = ModuleResult.PASSED
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return self.result.getReturnCode(self.res)
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