mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
William Leara
79f81bbb7e
This commit fixes whitespace errors from checkers W291,W292,W293,W391. They were found by running "flake8 ." from the root directory. These are errors defined by "pycodestyle", and have no functional impact to the source. This is simply fixing whitespace as defined by CHIPSEC's .flake8 configuration. background: https://www.flake8rules.com/rules/W291.html https://www.flake8rules.com/rules/W292.html https://www.flake8rules.com/rules/W293.html https://www.flake8rules.com/rules/W391.html tool versions: flake8 v7.3.0, python v3.13.11 Signed-off-by: William Leara <william.leara@dell.com>
167 lines
7.6 KiB
Python
167 lines
7.6 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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>>> chipsec_util cpu info
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>>> chipsec_util cpu cr <thread> <cr_number> [value]
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>>> chipsec_util cpu cpuid <eax> [ecx]
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>>> chipsec_util cpu pt [paging_base_cr3]
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>>> chipsec_util cpu topology
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Examples:
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>>> chipsec_util cpu info
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>>> chipsec_util cpu cr 0 0
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>>> chipsec_util cpu cr 0 4 0x0
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>>> chipsec_util cpu cpuid 0x40000000
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>>> chipsec_util cpu pt
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>>> chipsec_util cpu topology
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"""
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from argparse import ArgumentParser
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from chipsec.command import BaseCommand, toLoad
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from typing import Dict, List, Optional, Union
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# ###################################################################
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#
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# CPU utility
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#
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# ###################################################################
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class CPUCommand(BaseCommand):
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def requirements(self) -> toLoad:
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return toLoad.All
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def parse_arguments(self) -> None:
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parser = ArgumentParser(usage=__doc__)
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subparsers = parser.add_subparsers()
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parser_info = subparsers.add_parser('info')
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parser_cr = subparsers.add_parser('cr')
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parser_cpuid = subparsers.add_parser('cpuid')
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parser_pt = subparsers.add_parser('pt')
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parser_topology = subparsers.add_parser('topology')
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parser_info.set_defaults(func=self.cpu_info)
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parser_cr.set_defaults(func=self.cpu_cr)
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parser_cpuid.set_defaults(func=self.cpu_cpuid)
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parser_pt.set_defaults(func=self.cpu_pt)
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parser_topology.set_defaults(func=self.cpu_topology)
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parser_cr.add_argument('thread', type=int, nargs='?', default=None)
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parser_cr.add_argument('cr_number', type=int, nargs='?', default=None)
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parser_cr.add_argument('value', type=lambda x: int(x, 0), nargs='?', default=None)
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parser_cpuid.add_argument('eax', type=lambda x: int(x, 0))
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parser_cpuid.add_argument('ecx', type=lambda x: int(x, 0), nargs='?', default=0)
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parser_pt.add_argument('cr3', type=lambda x: int(x, 0), nargs='?', default=None)
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parser.parse_args(self.argv, namespace=CPUCommand)
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def cpu_info(self) -> None:
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self.logger.log("[CHIPSEC] CPU information:")
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ht = self.cs.hals.cpu.is_HT_active()
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threads_per_core = self.cs.hals.cpu.get_number_logical_processor_per_core()
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threads_per_pkg = self.cs.hals.cpu.get_number_logical_processor_per_package()
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cores_per_pkg = self.cs.hals.cpu.get_number_physical_processor_per_package()
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self.logger.log(f' Hyper-Threading : {"Enabled" if ht else "Disabled"}')
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self.logger.log(f' CPU cores per package : {cores_per_pkg:d}')
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self.logger.log(f' CPU threads per core : {threads_per_core:d}')
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self.logger.log(f' CPU threads per package : {threads_per_pkg:d}')
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try:
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threads_count = self.cs.hals.cpu.get_number_threads_from_APIC_table()
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sockets_count = self.cs.hals.cpu.get_number_sockets_from_APIC_table()
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self.logger.log(f' Number of sockets : {sockets_count:d}')
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self.logger.log(f' Number of CPU threads : {threads_count:d}')
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except Exception:
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pass
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def cpu_topology(self) -> Dict[str, Dict[int, List[int]]]:
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self.logger.log("[CHIPSEC] CPU information:")
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ht = self.cs.hals.cpu.is_HT_active()
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threads_per_core = self.cs.hals.cpu.get_number_logical_processor_per_core()
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threads_per_pkg = self.cs.hals.cpu.get_number_logical_processor_per_package()
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cores_per_pkg = self.cs.hals.cpu.get_number_physical_processor_per_package()
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num_threads = self.cs.helper.get_threads_count()
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self.logger.log(f' Hyper-Threading : {"Enabled" if ht else "Disabled"}')
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self.logger.log(f' CPU cores per package : {cores_per_pkg:d}')
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self.logger.log(f' CPU threads per core : {threads_per_core:d}')
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self.logger.log(f' CPU threads per package : {threads_per_pkg:d}')
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self.logger.log(f' Total threads : {num_threads:d}')
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topology = self.cs.hals.cpu.get_cpu_topology()
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self.logger.log(" Packages:")
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for p in topology['packages']:
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self.logger.log(f' {p:d}: {topology["packages"][p]}')
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self.logger.log(" Cores:")
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for c in topology['cores']:
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self.logger.log(f' {c:d}: {topology["cores"][c]}')
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return topology
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def cpu_cr(self) -> Optional[Union[bool, int]]:
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if self.value is not None:
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self.logger.log(f'[CHIPSEC] CPU{self.thread:d}: write CR{self.cr_number:d} <- 0x{self.value:08X}')
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self.cs.hals.cpu.write_cr(self.thread, self.cr_number, self.value)
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return True
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elif self.cr_number is not None:
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value = self.cs.hals.cpu.read_cr(self.thread, self.cr_number)
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self.logger.log(f'[CHIPSEC] CPU{self.thread:d}: read CR{self.cr_number:d} -> 0x{value:08X}')
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return value
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else:
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for tid in range(self.cs.hals.msr.get_cpu_thread_count()):
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cr0 = self.cs.hals.cpu.read_cr(tid, 0)
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cr2 = self.cs.hals.cpu.read_cr(tid, 2)
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cr3 = self.cs.hals.cpu.read_cr(tid, 3)
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cr4 = self.cs.hals.cpu.read_cr(tid, 4)
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cr8 = self.cs.hals.cpu.read_cr(tid, 8)
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self.logger.log(f'[CHIPSEC][cpu{tid:d}] x86 Control Registers:')
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self.logger.log(f' CR0: 0x{cr0:016X}')
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self.logger.log(f' CR2: 0x{cr2:016X}')
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self.logger.log(f' CR3: 0x{cr3:016X}')
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self.logger.log(f' CR4: 0x{cr4:016X}')
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self.logger.log(f' CR8: 0x{cr8:016X}')
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def cpu_cpuid(self) -> None:
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self.logger.log(f'[CHIPSEC] CPUID < EAX: 0x{self.eax:08X}')
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self.logger.log(f'[CHIPSEC] ECX: 0x{self.ecx:08X}')
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(_eax, _ebx, _ecx, _edx) = self.cs.hals.cpu.cpuid(self.eax, self.ecx)
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self.logger.log("[CHIPSEC] CPUID > EAX: 0x%08X" % _eax)
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self.logger.log("[CHIPSEC] EBX: 0x%08X" % _ebx)
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self.logger.log("[CHIPSEC] ECX: 0x%08X" % _ecx)
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self.logger.log("[CHIPSEC] EDX: 0x%08X" % _edx)
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def cpu_pt(self) -> None:
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if self.cr3 is not None:
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pt_fname = f'pt_{self.cr3:08X}'
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self.logger.log(f'[CHIPSEC] paging physical base (CR3): 0x{self.cr3:016X}')
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self.logger.log(f'[CHIPSEC] dumping paging hierarchy to \'{pt_fname}\'...')
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self.cs.hals.cpu.dump_page_tables(self.cr3, pt_fname)
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else:
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for tid in range(self.cs.hals.msr.get_cpu_thread_count()):
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cr3 = self.cs.hals.cpu.read_cr(tid, 3)
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pt_fname = f'cpu{tid:d}_pt_{cr3:08X}'
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self.logger.log(f'[CHIPSEC][cpu{tid:d}] paging physical base (CR3): 0x{cr3:016X}')
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self.logger.log(f'[CHIPSEC][cpu{tid:d}] dumping paging hierarchy to \'{pt_fname}\'...')
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self.cs.hals.cpu.dump_page_tables(cr3, pt_fname)
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commands = {'cpu': CPUCommand}
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