mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
c7zero
16af0c7dfd
* More operation in chipsec_util reg command Added write, read_field, write_field, get_control, set_control operations * reg read util command updated Returned back "chipsec_util reg read" syntax and added tests. * Commented out test_reg_get_control Need to implement get_MMIO_BAR_base_address or read_pci_reg for SPIBAR in mock_helper.py
46 lines
1.5 KiB
Python
46 lines
1.5 KiB
Python
#!/usr/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2017, Google
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#
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import unittest
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from tests.software import mock_helper, util
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class TestRegChipsecUtil(util.TestChipsecUtil):
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"""Test the reg commands exposed by chipsec_utils."""
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def test_reg_read(self):
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self._chipsec_util("reg read PCI0.0.0_VID")
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self._assertLogValue("PCI0.0.0_VID", "0x8086")
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def test_reg_read_field(self):
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self._chipsec_util("reg read PCI0.0.0_TOUUD LOCK")
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self._assertLogValue("PCI0.0.0_TOUUD.LOCK", "0x0")
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def test_reg_read_field1(self):
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self._chipsec_util("reg read_field PCI0.0.0_TOUUD LOCK")
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self._assertLogValue("PCI0.0.0_TOUUD.LOCK", "0x0")
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#def test_reg_get_control(self):
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# self._chipsec_util("reg get_control FlashLockDown")
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# self._assertLogValue("FlashLockDown", "0x0")
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if __name__ == '__main__':
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unittest.main()
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