Files
chipsec-chipsec/chipsec/utilcmd/txt_cmd.py
T
Nicolas Iooss 88d185e33f Add a command to dump Intel TXT public registers
Provide a way to dump the content of all TXT registers.
Here is an example of output:

    $ ./chipsec_util.py txt state

    ################################################################
    ##                                                            ##
    ##  CHIPSEC: Platform Hardware Security Assessment Framework  ##
    ##                                                            ##
    ################################################################
    [CHIPSEC] Version : 1.8.1
    [CHIPSEC] OS      : Linux 5.16.5-arch1-1 #1 SMP PREEMPT Tue, 01 Feb 2022 21:42:50 +0000 x86_64
    [CHIPSEC] Python  : 3.10.2 (64-bit)

    ****** Chipsec Linux Kernel module is licensed under GPL 2.0
    [CHIPSEC] API mode: using CHIPSEC kernel module API
    [CHIPSEC] Helper  : LinuxHelper (/mnt/data/to-be-backed-up/projects/chipsec/drivers/linux/chipsec.ko)
    [CHIPSEC] Platform: Desktop 6th Generation Core Processor Quad Core (Skylake CPU / Sunrise Point PCH)
    [CHIPSEC]      VID: 8086
    [CHIPSEC]      DID: 191F
    [CHIPSEC]      RID: 07
    [CHIPSEC] PCH     : Intel H170 (100 series) PCH
    [CHIPSEC]      VID: 8086
    [CHIPSEC]      DID: A144
    [CHIPSEC]      RID: 31
    [CHIPSEC] Executing command 'txt' with args ['state']

    [CHIPSEC] CPUID.01H.ECX[Bit 6] = 1 << Safer Mode Extensions (SMX)
    [CHIPSEC] CPUID.01H.ECX[Bit 5] = 1 << Virtual Machine Extensions (VMX)
    [CHIPSEC] CR4.SMXE[Bit 14] = 0 << Safer Mode Extensions Enable
    [CHIPSEC] CR4.VMXE[Bit 13] = 0 << Virtual Machine Extensions Enable
    [CHIPSEC] IA32_FEATURE_CONTROL = 0x00000005 (Processor Feature Control)
    [CHIPSEC]     [00] LOCK                    = 1 << Lock
    [CHIPSEC]     [01] EN_VMX_INSIDE_SMX       = 0 << Enable VMX inside SMX operation
    [CHIPSEC]     [02] EN_VMX_OUTSIDE_SMX      = 1 << Enable VMX outside SMX operation
    [CHIPSEC]     [03] Reserved0               = 0 << Reserved
    [CHIPSEC]     [08] SENTER_LOCAL_EN         = 0 << SENTER Local Functions Enable
    [CHIPSEC]     [15] SENTER_GLOBAL_EN        = 0 << SENTER Global Enable
    [CHIPSEC]     [16] Reserved1               = 0 << Reserved
    [CHIPSEC]     [17] SGX_LAUNCH_CTRL_EN      = 0 << SGX Launch Control Enable
    [CHIPSEC]     [18] SGX_GLOBAL_EN           = 0 << SGX Global Enable
    [CHIPSEC]     [19] Reserved2               = 0 << Reserved
    [CHIPSEC]     [20] LMCE_ON                 = 0 << Turn Local Machine Check On
    [CHIPSEC]
    [CHIPSEC] TXT_DIDVID = 0x00000001B0068086 (TXT Device ID, at FED30110)
    [CHIPSEC]     [00] VID                     = 8086 << Vendor ID
    [CHIPSEC]     [16] DID                     = B006 << Device ID
    [CHIPSEC]     [32] RID                     = 1 << Revision ID
    [CHIPSEC]     [48] EXTID                   = 0 << Extended ID
    [CHIPSEC]
    [CHIPSEC] TXT Public Key Hash: 2d67ddd75ef9339266a56f27189555ae77a2b0de774222e5de248dbeb8e33dd7
    [CHIPSEC] Public Key Hash in MSR[0x20...0x23]: c14a4b4be9b8aa001b65377fe689d252e6c68dcd66d37bce1da9769867d10cfd
    [CHIPSEC]
    [CHIPSEC] TXT_STS = 0x0000000000000002 (TXT Status, at FED30000)
    [CHIPSEC]     [00] SENTER_DONE_STS         = 0 << SENTER Done
    [CHIPSEC]     [01] SEXIT_DONE_STS          = 1 << SEXIT Done
    [CHIPSEC]     [04] MEM_UNLOCK_STS          = 0 << Memory Unlocked
    [CHIPSEC]     [06] MEM_CONFIG_LOCK_STS     = 0 << Memory Configuration Locked
    [CHIPSEC]     [07] PRIVATE_OPEN_STS        = 0 << Open-Private Command Performed
    [CHIPSEC]     [10] NTP_ENABLE_STS          = 0 << NTP Enabled
    [CHIPSEC]     [11] MEM_CONFIG_OK_STS       = 0 << Mem CFG OK
    [CHIPSEC]     [12] PMRC_LOCK_STS           = 0 << PMRC Locked
    [CHIPSEC]     [13] SMM_OPEN_STS            = 0 << SMM Opened
    [CHIPSEC]     [14] TXT_LOCALITY3_OPEN_STS  = 0 << Locality 3 Opened
    [CHIPSEC]     [15] TXT_LOCALITY1_OPEN_STS  = 0 << Locality 1 Opened
    [CHIPSEC]     [16] TXT_LOCALITY2_OPEN_STS  = 0 << Locality 2 Opened
    [CHIPSEC] TXT_ESTS = 0x0000000000000000 (TXT Error Status, at FED30008)
    [CHIPSEC]     [00] TXT_RESET_STS           = 0 << TXT Reset
    [CHIPSEC]     [01] ROGUE_STS               = 0 << Rogue Status
    [CHIPSEC]     [06] WAKE_ERROR_STS          = 0 << Wake Error
    [CHIPSEC] TXT_E2STS = 0x0000000000000004 (TXT Extended Error Status, at FED308F0)
    [CHIPSEC]     [01] SECRETS_STS             = 0 << Secrets in Memory
    [CHIPSEC] TXT_ERRORCODE = 0x0000000000000000 (TXT Error Code (0xC0000001 when successful SINIT), at FED30030)
    [CHIPSEC]     [00] TYPE2_MODULE_TYPE       = 0 << Module Type (0 for BIOS ACM, 1 for SINIT)
    [CHIPSEC]     [04] TYPE2_CLASS_CODE        = 0 << Class Code
    [CHIPSEC]     [10] TYPE2_MAJOR_ERROR_CODE  = 0 << Major Error Code
    [CHIPSEC]     [15] SOFTWARE_SOURCE         = 0 << Software Source (0 for ACM, 1 of MLE)
    [CHIPSEC]     [16] TYPE1_MINOR_ERROR_CODE  = 0 << Minor Error Code
    [CHIPSEC]     [28] TYPE1_RESERVED          = 0 << Failure Condition Details
    [CHIPSEC]     [30] SOFTWARE                = 0 << Error reported by Software (0 for Processor)
    [CHIPSEC]     [31] VALID                   = 0 << Valid Register Content
    [CHIPSEC]
    [CHIPSEC] TXT_SPAD = 0x0000000000000000 (Boot Status, at FED300A0)
    [CHIPSEC]     [00] ACM_INTERNAL            = 0 << ACM Internal Use
    [CHIPSEC]     [30] TXT_STARTUP_SUCCESS     = 0 << TXT Startup Success
    [CHIPSEC]     [31] BOOT_STATUS             = 0 << General Startup ACM to BIOS status communication
    [CHIPSEC]     [47] MEM_POWER_DOWN_EXECUTED = 0 << Memory content was cleared via power down
    [CHIPSEC]     [48] BOOT_STATUS_DETAILS_48  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [53] TXT_POLICY_ENABLE       = 0 << Startup ACM indication of run-time enabled status of TXT
    [CHIPSEC]     [54] BOOT_STATUS_DETAILS_54  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [59] BIOS_TRUSTED            = 0 << BIOS is trusted
    [CHIPSEC]     [60] TXT_POLICY_DISABLE      = 0 << TXT has been disabled by runtime FIT type 0xA record policy setting
    [CHIPSEC]     [61] BOOT_STATUS_DETAILS_61  = 0 << Startup ACM to BIOS communication in MP platforms
    [CHIPSEC]     [62] CPU_ERROR               = 0 << ACM authentication error
    [CHIPSEC]     [63] S_ACM_SUCCESS           = 0 << S-ACM successfully enforced its logic for all provisioned technologies
    [CHIPSEC] TXT_ACM_STATUS = 0x00000000 (TXT ACM Status, at FED30328)
    [CHIPSEC]     [00] MODULE_TYPE             = 0 << Module Type
    [CHIPSEC]     [04] CLASS_CODE              = 0 << Class Code
    [CHIPSEC]     [10] MAJOR_ERROR_CODE        = 0 << Major Error Code
    [CHIPSEC]     [15] ACM_STARTED             = 0 << ACM Started
    [CHIPSEC]     [16] MINOR_ERROR_CODE        = 0 << Minor Error Code
    [CHIPSEC]     [31] VALID                   = 0 << Valid
    [CHIPSEC] TXT_FIT = 0x00000000 (FIT (Firmware Interface Table), at FED30340)
    [CHIPSEC]     [00] FIT_FAILED              = 0 << FIT Failed
    [CHIPSEC]     [01] S_ACM_FAILED            = 0 << S-ACM Failed
    [CHIPSEC]     [02] FIT_MEASURED            = 0 << FIT Measured
    [CHIPSEC]     [03] FIT_FALLBACK            = 0 << FIT Fallback
    [CHIPSEC] TXT_SCRATCHPAD = 0x0000000000000000 (ACM Policy Status, at FED30378)
    [CHIPSEC]     [13] TPM_TYPE                = 0 << TPM type detected by Startup ACM (0 for no TPM, 1 for dTPM1.2, 2 for dTPM2.0, 3 for PTT)
    [CHIPSEC]     [15] TPM_SUCCESS             = 0 << TPM Success
    [CHIPSEC]     [17] BOOT_POLICIES_2         = 0 << Boot Policies
    [CHIPSEC]     [18] BACKUP_ACTION           = 0 << Backup Action
    [CHIPSEC]     [20] TXT_PROFILE             = 0 << TXT Profile
    [CHIPSEC]     [25] MEMORY_SCRUB_POLICY     = 0 << Memory Scrub Policy
    [CHIPSEC]     [29] IBB_DMA_PROTECTION      = 0 << IBB (Initial Boot Block) DMA Protection
    [CHIPSEC]     [32] S_CRTM_STATUS           = 0 << Startup ACM S-CRTM establishment
    [CHIPSEC]     [35] CPU_COSIGNING_ENABLE    = 0 << CPU co-signing enabled
    [CHIPSEC]     [36] TPM_STARTUP_LOCALITY    = 0 << Locality at which TPM2_Startup command was executed (0 for locality 3, 1 for locality 0)
    [CHIPSEC]
    [CHIPSEC] TXT_SINIT_BASE = 0x00000000 (SINIT Base Address, at FED30270)
    [CHIPSEC] TXT_SINIT_SIZE = 0x00000000 (SINIT Size, at FED30278)
    [CHIPSEC] TXT_MLE_JOIN = 0x00000000 (MLE Join Base Address, at FED30290)
    [CHIPSEC] TXT_HEAP_BASE = 0x00000000 (TXT Heap Base Address, at FED30300)
    [CHIPSEC] TXT_HEAP_SIZE = 0x00000000 (TXT Heap Size, at FED30308)
    [CHIPSEC] TXT_MSEG_BASE = 0x00000000 (TXT MSEG Base Address, at FED30310)
    [CHIPSEC] TXT_MSEG_SIZE = 0x00000000 (TXT MSEG Size, at FED30318)
    [CHIPSEC]
    [CHIPSEC] TXT_DPR = 0x00000000 (TXT DMA Protected Range (deprecated, replaced by PCI0.0.0_DPR), at FED30330)
    [CHIPSEC]     [00] LOCK                    = 0 << Lock Bits 19:0
    [CHIPSEC]     [04] SIZE                    = 0 << Protected Memory Size (in MB)
    [CHIPSEC]     [20] TOP                     = 0 << Top Address+1 of DPR (base of TSEG)
    [CHIPSEC] TXT_VER_FSBIF = 0xFFFFFFFF (TXT Front Side Bus Interface, at FED30100)
    [CHIPSEC]     [31] DEBUG_FUSE              = 1 << Chipset is Production Fused (0 for Debug)
    [CHIPSEC] TXT_VER_QPIIF = 0x9D003000 (TXT Intel QuickPath Interconnect Interface, at FED30200)
    [CHIPSEC]     [19] PMRC_CAPABLE            = 0 << PMRC Capable
    [CHIPSEC]     [26] DPR_CAPABLE             = 1 << DPR Capable
    [CHIPSEC]     [31] DEBUG_FUSE              = 1 << Chipset is Production Fused (0 for Debug)
    [CHIPSEC] TXT_PCH_DIDVID = 0x00000001A1448086 (TXT Platform Controller Hub Device ID, at FED30810)
    [CHIPSEC]     [00] VID                     = 8086 << Vendor ID
    [CHIPSEC]     [16] DID                     = A144 << Device ID
    [CHIPSEC]     [32] RID                     = 1 << Revision ID
    [CHIPSEC] INSMM = 0x00000000 (InSMM.STS, at FED30880)
    [CHIPSEC]     [00] STS                     = 0 << BIOS Write Enable when enabled by SPI.BC.EISS=1

Signed-off-by: Nicolas Iooss <nicolas.iooss_git@polytechnique.org>
2022-02-28 15:49:48 -08:00

171 lines
7.1 KiB
Python

# CHIPSEC: Platform Security Assessment Framework
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License
# as published by the Free Software Foundation; Version 2.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
#You should have received a copy of the GNU General Public License
#along with this program; if not, write to the Free Software
#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
#
#Contact information:
#chipsec@intel.com
#
"""
Command-line utility providing access to Intel TXT (Trusted Execution Technology) registers
Usage:
>>> chipsec_util txt dump
>>> chipsec_util txt state
"""
from argparse import ArgumentParser
import binascii
from chipsec.command import BaseCommand
from chipsec.exceptions import HWAccessViolationError
import struct
class TXTCommand(BaseCommand):
def requires_driver(self):
parser = ArgumentParser(usage=__doc__)
subparsers = parser.add_subparsers()
parser_state = subparsers.add_parser('dump')
parser_state.set_defaults(func=self.txt_dump)
parser_state = subparsers.add_parser('state')
parser_state.set_defaults(func=self.txt_state)
parser.parse_args(self.argv[2:], namespace=self)
return True
def txt_dump(self):
# Read TXT Public area as hexdump, with absolute address and skipping zeros
txt_public = self.cs.mem.read_physical_mem(0xfed30000, 0x1000)
has_skipped_line = False
for offset in range(0, len(txt_public), 16):
line_bytes = txt_public[offset:offset + 16]
if all(b == 0 for b in line_bytes):
has_skipped_line = True
continue
if has_skipped_line:
self.logger.log("[CHIPSEC] *")
has_skipped_line = False
line_hex = " ".join("{:02X}".format(b) for b in line_bytes)
self.logger.log("[CHIPSEC] {:08X}: {}".format(0xfed30000 + offset, line_hex))
def _log_register(self, reg_name):
"""Log the content of a register with lines starting with [CHIPSEC]"""
reg_def = self.cs.get_register_def(reg_name)
value = self.cs.read_register(reg_name)
desc = reg_def["desc"]
if reg_def["type"] == "memory":
addr = int(reg_def["address"], 16) + int(reg_def["offset"], 16)
desc += ", at {:08X}".format(addr)
self.logger.log("[CHIPSEC] {} = 0x{:0{width}X} ({})".format(
reg_name, value, desc, width=int(reg_def['size'], 16) * 2))
if 'FIELDS' in reg_def:
sorted_fields = sorted(reg_def['FIELDS'].items(), key=lambda field: int(field[1]['bit']))
for field_name, field_attrs in sorted_fields:
field_bit = int(field_attrs['bit'])
field_size = int(field_attrs['size'])
field_mask = (1 << field_size) - 1
field_value = (value >> field_bit) & field_mask
self.logger.log("[CHIPSEC] [{:02d}] {:23} = {:X} << {}".format(
field_bit, field_name, field_value, field_attrs['desc']))
def txt_state(self):
"""Dump Intel TXT state
This is similar to command "txt-stat" from Trusted Boot project
https://sourceforge.net/p/tboot/code/ci/v2.0.0/tree/utils/txt-stat.c
which was documented on
https://www.intel.com/content/dam/www/public/us/en/documents/guides/dell-one-stop-txt-activation-guide.pdf
and it is also similar to command "sl-stat" from TrenchBoot project
https://github.com/TrenchBoot/sltools/blob/842cfd041b7454727b363b72b6d4dcca9c00daca/sl-stat/sl-stat.c
"""
# Read bits in CPUID
(eax, ebx, ecx, edx) = self.cs.cpu.cpuid(0x01, 0x00)
self.logger.log("[CHIPSEC] CPUID.01H.ECX[Bit 6] = {} << Safer Mode Extensions (SMX)".format((ecx >> 6) & 1))
self.logger.log("[CHIPSEC] CPUID.01H.ECX[Bit 5] = {} << Virtual Machine Extensions (VMX)".format((ecx >> 5) & 1))
# Read bits in CR4
cr4 = self.cs.cpu.read_cr(0, 4)
self.logger.log("[CHIPSEC] CR4.SMXE[Bit 14] = {} << Safer Mode Extensions Enable".format((cr4 >> 14) & 1))
self.logger.log("[CHIPSEC] CR4.VMXE[Bit 13] = {} << Virtual Machine Extensions Enable".format((cr4 >> 13) & 1))
# Read bits in MSR IA32_FEATURE_CONTROL
self._log_register("IA32_FEATURE_CONTROL")
self.logger.log("[CHIPSEC]")
# Read TXT Device ID
self._log_register("TXT_DIDVID")
self.logger.log("[CHIPSEC]")
# Read hashes of public keys
txt_pubkey = struct.pack("<QQQQ",
self.cs.read_register("TXT_PUBLIC_KEY_0"),
self.cs.read_register("TXT_PUBLIC_KEY_1"),
self.cs.read_register("TXT_PUBLIC_KEY_2"),
self.cs.read_register("TXT_PUBLIC_KEY_3"),
)
self.logger.log("[CHIPSEC] TXT Public Key Hash: {}".format(
binascii.hexlify(txt_pubkey).decode("ascii")))
try:
eax, edx = self.cs.msr.read_msr(0, 0x20)
pubkey_in_msr = struct.pack("<II", eax, edx)
eax, edx = self.cs.msr.read_msr(0, 0x21)
pubkey_in_msr += struct.pack("<II", eax, edx)
eax, edx = self.cs.msr.read_msr(0, 0x22)
pubkey_in_msr += struct.pack("<II", eax, edx)
eax, edx = self.cs.msr.read_msr(0, 0x23)
pubkey_in_msr += struct.pack("<II", eax, edx)
self.logger.log("[CHIPSEC] Public Key Hash in MSR[0x20...0x23]: {}".format(
binascii.hexlify(pubkey_in_msr).decode("ascii")))
except HWAccessViolationError as exc:
# Report the exception and continue
self.logger.log("[CHIPSEC] Unable to read Public Key Hash in MSR[0x20...0x23]: {}".format(exc))
self.logger.log("[CHIPSEC]")
# Read TXT status
self._log_register("TXT_STS")
self._log_register("TXT_ESTS")
self._log_register("TXT_E2STS")
self._log_register("TXT_ERRORCODE")
self.logger.log("[CHIPSEC]")
self._log_register("TXT_SPAD")
self._log_register("TXT_ACM_STATUS")
self._log_register("TXT_FIT")
self._log_register("TXT_SCRATCHPAD")
self.logger.log("[CHIPSEC]")
# Read memory area for TXT components
self._log_register("TXT_SINIT_BASE")
self._log_register("TXT_SINIT_SIZE")
self._log_register("TXT_MLE_JOIN")
self._log_register("TXT_HEAP_BASE")
self._log_register("TXT_HEAP_SIZE")
self._log_register("TXT_MSEG_BASE")
self._log_register("TXT_MSEG_SIZE")
self.logger.log("[CHIPSEC]")
# Read other registers in the TXT memory area
self._log_register("TXT_DPR")
self._log_register("TXT_VER_FSBIF")
self._log_register("TXT_VER_QPIIF")
self._log_register("TXT_PCH_DIDVID")
self._log_register("INSMM")
def run(self):
self.func()
commands = {'txt': TXTCommand}