mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
abazhaniuk
c377a72e28
* merge * Add Debian packaging * cleanup * Removed incorrect info into Copyright. * One more: removed incorrect info in Copyright.
88 lines
3.3 KiB
Python
88 lines
3.3 KiB
Python
#!/usr/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2015, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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# -------------------------------------------------------------------------------
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#
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# CHIPSEC: Platform Hardware Security Assessment Framework
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# (c) 2010-2012 Intel Corporation
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#
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# -------------------------------------------------------------------------------
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"""
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Functionality encapsulating interrupt generation
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CPU Interrupts specific functions (SMI, NMI)
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usage:
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>>> send_SMI_APMC( 0xDE )
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>>> send_NMI()
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"""
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#TODO IPIs through Local APIC??
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__version__ = '1.0'
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import struct
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import sys
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from chipsec.hal import hal_base
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from chipsec.logger import *
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from chipsec.cfg.common import *
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SMI_APMC_PORT = 0xB2
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NMI_TCO1_CTL = 0x8 # NMI_NOW is bit [8] in TCO1_CTL (or bit [1] in TCO1_CTL + 1)
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NMI_NOW = 0x1
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class Interrupts(hal_base.HALBase):
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def send_SW_SMI( self, thread_id, SMI_code_port_value, SMI_data_port_value, _rax, _rbx, _rcx, _rdx, _rsi, _rdi ):
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SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
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if logger().HAL:
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logger().log( "[intr] sending SW SMI: code port 0x%02X <- 0x%02X, data port 0x%02X <- 0x%02X (0x%04X)" % (SMI_APMC_PORT, SMI_code_port_value, SMI_APMC_PORT+1, SMI_data_port_value, SMI_code_data) )
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logger().log( " RAX = 0x%016X (AX will be overwridden with values of SW SMI ports B2/B3)" % _rax )
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logger().log( " RBX = 0x%016X" % _rbx )
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logger().log( " RCX = 0x%016X" % _rcx )
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logger().log( " RDX = 0x%016X (DX will be overwridden with 0x00B2)" % _rdx )
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logger().log( " RSI = 0x%016X" % _rsi )
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logger().log( " RDI = 0x%016X" % _rdi )
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return self.cs.helper.send_sw_smi( thread_id, SMI_code_data, _rax, _rbx, _rcx, _rdx, _rsi, _rdi )
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def send_SMI_APMC( self, SMI_code_port_value, SMI_data_port_value ):
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SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
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if logger().HAL: logger().log( "[intr] sending SMI via APMC ports: code 0xB2 <- 0x%02X, data 0xB3 <- 0x%02X (0x%04X)" % (SMI_code_port_value, SMI_data_port_value, SMI_code_data) )
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return self.cs.io.write_port_word( SMI_APMC_PORT, SMI_code_data )
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def get_PMBASE(self):
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return (self.cs.pci.read_dword( 0, 31, 0, Cfg.CFG_REG_PCH_LPC_PMBASE ) & ~0x1)
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def get_TCOBASE(self):
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return (self.get_PMBASE() + Cfg.TCOBASE_ABASE_OFFSET)
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def send_NMI( self ):
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if logger().HAL: logger().log( "[intr] sending NMI# through TCO1_CTL[NMI_NOW]" )
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tcobase = self.get_TCOBASE()
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return self.cs.io.write_port_byte( tcobase + NMI_TCO1_CTL + 1, NMI_NOW )
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