mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
abazhaniuk
c377a72e28
* merge * Add Debian packaging * cleanup * Removed incorrect info into Copyright. * One more: removed incorrect info in Copyright.
82 lines
2.9 KiB
Python
82 lines
2.9 KiB
Python
#!/usr/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2015, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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"""
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The msr command allows direct access to read and write MSRs.
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"""
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__version__ = '1.0'
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from chipsec.command import BaseCommand
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from chipsec.hal.msr import Msr
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# CPU Model Specific Registers
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class MSRCommand(BaseCommand):
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"""
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>>> chipsec_util msr <msr> [eax] [edx] [cpu_id]
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Examples:
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>>> chipsec_util msr 0x3A
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>>> chipsec_util msr 0x8B 0x0 0x0 0
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"""
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def requires_driver(self):
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# No driver required when printing the util documentation
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if len(self.argv) < 3:
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return False
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return True
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def run(self):
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if len(self.argv) < 3:
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print MSRCommand.__doc__
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return
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#msr = Msr( os_helper )
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msr_addr = int(self.argv[2],16)
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if (3 == len(self.argv)):
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for tid in range(self.cs.msr.get_cpu_thread_count()):
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(eax, edx) = self.cs.msr.read_msr( tid, msr_addr )
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val64 = ((edx << 32) | eax)
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self.logger.log( "[CHIPSEC] CPU%d: RDMSR( 0x%x ) = %016X (EAX=%08X, EDX=%08X)" % (tid, msr_addr, val64, eax, edx) )
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elif (4 == len(self.argv)):
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cpu_thread_id = int(self.argv[3], 16)
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(eax, edx) = self.cs.msr.read_msr( cpu_thread_id, msr_addr )
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val64 = ((edx << 32) | eax)
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self.logger.log( "[CHIPSEC] CPU%d: RDMSR( 0x%x ) = %016X (EAX=%08X, EDX=%08X)" % (cpu_thread_id, msr_addr, val64, eax, edx) )
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else:
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eax = int(self.argv[3], 16)
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edx = int(self.argv[4], 16)
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val64 = ((edx << 32) | eax)
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if (5 == len(self.argv)):
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self.logger.log( "[CHIPSEC] All CPUs: WRMSR( 0x%x ) = %016X" % (msr_addr, val64) )
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for tid in range(self.cs.msr.get_cpu_thread_count()):
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self.cs.msr.write_msr( tid, msr_addr, eax, edx )
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elif (6 == len(self.argv)):
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cpu_thread_id = int(self.argv[5], 16)
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self.logger.log( "[CHIPSEC] CPU%d: WRMSR( 0x%x ) = %016X" % (cpu_thread_id, msr_addr, val64) )
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self.cs.msr.write_msr( cpu_thread_id, msr_addr, eax, edx )
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commands = { 'msr': MSRCommand }
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