mirror of
https://github.com/chipsec/chipsec
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Sae86
132 lines
5.4 KiB
Python
132 lines
5.4 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2010-2022, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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# You should have received a copy of the GNU General Public License
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# along with this program; if not, write to the Free Software
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# Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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# Contact information:
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# chipsec@intel.com
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#
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"""
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Checks for RTC memory locks.
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Since we do not know what RTC memory will be used for on a specific platform, we return WARNING (rather than FAILED) if the memory is not locked.
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Usage:
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``chipsec_main -m common.rtclock [-a modify]``
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- ``-a modify``: Attempt to modify CMOS values
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Examples:
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>>> chipsec_main.py -m common.rtclock
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>>> chipsec_main.py -m common.rtclock -a modify
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Registers used:
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- RC.LL
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- RC.UL
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.. NOTE::
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- This module will only run on Core platforms
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"""
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from chipsec.module_common import BaseModule, ModuleResult, MTAG_BIOS, MTAG_HWCONFIG
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from chipsec.hal.cmos import CMOS
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from chipsec.config import CHIPSET_CODE_AVN
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TAGS = [MTAG_BIOS, MTAG_HWCONFIG]
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class rtclock(BaseModule):
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def __init__(self):
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BaseModule.__init__(self)
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self.cmos = CMOS(self.cs)
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self.rc_res = ModuleResult(0xb305218, 'https://chipsec.github.io/modules/chipsec.modules.common.rtclock.html')
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self.user_request = False
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self.test_offset = 0x38
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self.test_value = 0xAA
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def is_supported(self):
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if self.cs.is_core() or (self.cs.Cfg.get_chipset_code() == CHIPSET_CODE_AVN):
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if self.cs.is_register_defined('RC'):
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return True
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self.logger.log_important('RC register not defined for platform. Skipping module.')
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else:
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self.logger.log_important('Not a Core platform. Skipping check.')
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self.rc_res.setStatusBit(self.rc_res.status.NOT_APPLICABLE)
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self.res = self.rc_res.getReturnCode(ModuleResult.NOTAPPLICABLE)
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return False
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def check_rtclock(self):
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ll = ul = 0
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check_config_regs = self.cs.read_register('RC') != 0xFFFFFFFF
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if check_config_regs:
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rc_reg = self.cs.read_register('RC')
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self.cs.print_register('RC', rc_reg)
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ll = self.cs.get_register_field('RC', rc_reg, 'LL')
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ul = self.cs.get_register_field('RC', rc_reg, 'UL')
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elif self.user_request:
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self.logger.log_important('Writing to CMOS to determine write protection (original values will be restored)')
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# Try to modify the low RTC memory regions.
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original_val = self.cmos.read_cmos_low(self.test_offset)
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self.cmos.write_cmos_low(self.test_offset, original_val ^ self.test_value)
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if original_val == self.cmos.read_cmos_low(self.test_offset):
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ll = 1
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else:
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self.logger.log_important('Restoring original value')
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self.cmos.write_cmos_low(self.test_offset, original_val)
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# Try to modify the upper RTC memory regions.
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original_val = self.cmos.read_cmos_high(self.test_offset)
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self.cmos.write_cmos_high(self.test_offset, original_val ^ self.test_value)
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if original_val == self.cmos.read_cmos_high(self.test_offset):
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ul = 1
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else:
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self.logger.log_important('Restoring original value')
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self.cmos.write_cmos_high(self.test_offset, original_val)
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else:
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self.logger.log_important("Unable to test lock bits without attempting to modify CMOS.")
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self.logger.log("[*] Run chipsec_main manually with the following commandline flags.")
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self.logger.log("[*] python chipsec_main -m common.rtclock -a modify")
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self.rc_res.setStatusBit(self.rc_res.status.VERIFY)
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return self.rc_res.getReturnCode(ModuleResult.WARNING)
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if ll == 1:
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self.logger.log_good("Protected bytes (0x38-0x3F) in low 128-byte bank of RTC memory are locked")
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else:
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self.logger.log_bad("Protected bytes (0x38-0x3F) in low 128-byte bank of RTC memory are not locked")
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if ul == 1:
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self.logger.log_good("Protected bytes (0x38-0x3F) in high 128-byte bank of RTC memory are locked")
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else:
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self.logger.log_bad("Protected bytes (0x38-0x3F) in high 128-byte bank of RTC memory are not locked")
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if (ll == 1) and (ul == 1):
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res = ModuleResult.PASSED
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self.logger.log_passed("Protected locations in RTC memory are locked")
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else:
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res = ModuleResult.WARNING
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self.rc_res.setStatusBit(self.rc_res.status.POTENTIALLY_VULNERABLE)
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self.logger.log_warning("Protected locations in RTC memory are accessible (BIOS may not be using them)")
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return self.rc_res.getReturnCode(res)
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def run(self, module_argv):
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self.logger.start_test("Protected RTC memory locations")
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if len(module_argv) >= 1:
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if module_argv[0].lower() == 'modify':
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self.user_request = True
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self.res = self.check_rtclock()
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return self.res
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