mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
Frinzell, Aaron
108 lines
4.0 KiB
Python
108 lines
4.0 KiB
Python
# CHIPSEC: Platform Security Assessment Framework
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# Copyright (c) 2018, Eclypsium, Inc.
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# Copyright (c) 2019-2021, Intel Corporation
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#
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# This program is free software; you can redistribute it and/or
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# modify it under the terms of the GNU General Public License
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# as published by the Free Software Foundation; Version 2.
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#
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# This program is distributed in the hope that it will be useful,
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# but WITHOUT ANY WARRANTY; without even the implied warranty of
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# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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# GNU General Public License for more details.
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#
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"""
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This module checks if memory configuration is locked to protect SMM
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Reference:
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- https://github.com/coreboot/coreboot/blob/master/src/cpu/intel/model_206ax/finalize.c
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- https://github.com/coreboot/coreboot/blob/master/src/soc/intel/broadwell/include/soc/msr.h
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This module checks the following:
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- MSR_LT_LOCK_MEMORY MSR (0x2E7) - Bit [0]
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The module returns the following results:
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- **FAILED** : MSR_LT_LOCK_MEMORY[0] is not set
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- **PASSED** : MSR_LT_LOCK_MEMORY[0] is set
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- **ERROR** : Problem reading MSR_LT_LOCK_MEMORY values
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Usage:
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``chipsec_main -m common.memlock``
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Example:
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>>> chipsec_main.py -m common.memlock
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Registers used:
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- MSR_LT_LOCK_MEMORY
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.. note::
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- This module will not run on Atom based platforms.
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"""
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from chipsec.module_common import BaseModule
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from chipsec.library.returncode import ModuleResult
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from chipsec.library.exceptions import HWAccessViolationError
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from typing import List
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_MODULE_NAME = 'memlock'
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class memlock(BaseModule):
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def __init__(self):
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BaseModule.__init__(self)
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self.is_read_error = False
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def is_supported(self) -> bool:
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# Workaround for Atom based processors. Accessing this MSR on these systems
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# causes a GP fault and can't be caught in UEFI Shell.
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if not self.cs.is_atom():
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if self.cs.register.has_field('MSR_LT_LOCK_MEMORY', 'LT_LOCK'):
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return True
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else:
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self.logger.log_important("'MSR_LT_LOCK_MEMORY.LT_LOCK' not defined for platform. Skipping module.")
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else:
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self.logger.log_important('Found an Atom based platform. Skipping module.')
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return False
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def check_MSR_LT_LOCK_MEMORY(self) -> bool:
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self.logger.log('[*] Checking MSR_LT_LOCK_MEMORY status')
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status = False
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for tid in range(self.cs.msr.get_cpu_thread_count()):
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lt_lock_msr = 0
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try:
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lt_lock_msr = self.cs.register.read('MSR_LT_LOCK_MEMORY', tid)
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except HWAccessViolationError:
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self.logger.log_important('Could not read MSR_LT_LOCK_MEMORY')
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self.is_read_error = True
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break
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if self.logger.VERBOSE:
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self.cs.register.print('MSR_LT_LOCK_MEMORY', lt_lock_msr)
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lt_lock = self.cs.register.get_field('MSR_LT_LOCK_MEMORY', lt_lock_msr, 'LT_LOCK')
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self.logger.log(f'[*] cpu{tid:d}: MSR_LT_LOCK_MEMORY[LT_LOCK] = {lt_lock:x}')
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if 0 == lt_lock:
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status = True
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return status
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def run(self, module_argv: List[str]) -> int:
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self.logger.start_test('Check MSR_LT_LOCK_MEMORY')
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check_MSR_LT_LOCK_MEMORY_test_fail = self.check_MSR_LT_LOCK_MEMORY()
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if self.is_read_error:
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self.logger.log_error('There was a problem reading MSR_LT_LOCK_MEMORY.')
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self.logger.log_important('Possible the environment or a platform feature is preventing these reads.')
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self.res = ModuleResult.ERROR
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self.result.setStatusBit(self.result.status.ACCESS_RW)
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elif check_MSR_LT_LOCK_MEMORY_test_fail is True:
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self.logger.log_failed('MSR_LT_LOCK_MEMORY.LT_LOCK bit is not configured correctly')
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self.res = ModuleResult.FAILED
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self.result.setStatusBit(self.result.status.LOCKS)
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else:
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self.logger.log_passed('MSR_LT_LOCK_MEMORY.LT_LOCK bit is set')
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self.res = ModuleResult.PASSED
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return self.result.getReturnCode(self.res)
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