mirror of
https://github.com/chipsec/chipsec
synced 2026-06-08 13:31:00 +00:00
CHIPSEC
ac2ca7264f
UEFI shell. 2. Decompression of images in SPI flash parsing is only supported in Windows. 3. UEFI - Support for IA32 and i586 (Quark) 4. Added capability to use modules from an arbitrary path with the -I / --import command line option 5. Module functionality encapsulated in class inheriting BaseModule 6. Fixed loading platform specific configuration 7. Fixed issue with modules which run on multiple logical CPUs hanging on Bay Trail (Windows/Linux). The issue still exist when running from UEFI shell 8. Added template for a module - module_template.py 9. Added options to flush log files 10. Added ability to define custom platforms Driver changes: 1. Windows - Added IOCTL_ALLOC_PHYSMEM to allocate physical memory buffer 2. Linux - Fix wrpci defect
76 lines
2.5 KiB
C
76 lines
2.5 KiB
C
#ifndef CPU_H
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#define CPU_H
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//#ifndef _WIN64 TODO: remove
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#if 0
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#define _eflags( eflags ) __asm \
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{ \
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__asm push eax \
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__asm pushfd \
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__asm pop eax \
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__asm mov eflags, eax \
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__asm pop eax \
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}
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#endif
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#if defined(_M_AMD64)
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typedef UINT64 CPU_REG_TYPE;
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#elif defined(_M_IX86)
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typedef UINT32 CPU_REG_TYPE;
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#else
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#error "Architecture not supported"
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#endif
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/*
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* External Assembly Functions
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*/
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// -- Access to CPU MSRs
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extern void _rdmsr( UINT32 msr_num, UINT32* msr_lo, UINT32* msr_hi );
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extern void _wrmsr( UINT32 msr_num, UINT32 msr_lo, UINT32 msr_hi );
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// -- Access to PCI CFG space
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extern void WritePCIByte ( UINT32 pci_reg, UINT16 cfg_data_port, UINT8 byte_value );
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extern void WritePCIWord ( UINT32 pci_reg, UINT16 cfg_data_port, UINT16 word_value );
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extern void WritePCIDword( UINT32 pci_reg, UINT16 cfg_data_port, UINT32 dword_value );
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extern UINT8 ReadPCIByte ( UINT32 pci_reg, UINT16 cfg_data_port );
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extern UINT16 ReadPCIWord ( UINT32 pci_reg, UINT16 cfg_data_port );
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extern UINT32 ReadPCIDword ( UINT32 pci_reg, UINT16 cfg_data_port );
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// -- Access to Port I/O
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extern UINT32 ReadPortDword ( UINT16 port_num );
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extern UINT16 ReadPortWord ( UINT16 port_num );
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extern UINT8 ReadPortByte ( UINT16 port_num );
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extern void WritePortDword( UINT32 out_value, UINT16 port_num );
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extern void WritePortWord ( UINT16 out_value, UINT16 port_num );
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extern void WritePortByte ( UINT8 out_value, UINT16 port_num );
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// -- Access to CPU Descriptor tables
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extern void _store_idtr( void* desc_address );
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extern void _load_idtr ( void* desc_address );
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extern void _store_gdtr( void* desc_address );
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extern void _store_ldtr( void* desc_address );
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// -- Interrupts
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extern void _swsmi( UINT32 smi_code_data, CPU_REG_TYPE rax_value, CPU_REG_TYPE rbx_value, CPU_REG_TYPE rcx_value, CPU_REG_TYPE rdx_value, CPU_REG_TYPE rsi_value, CPU_REG_TYPE rdi_value );
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// --
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// -- MSR definitions
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// --
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#define MSR_IA32_BIOS_UPDT_TRIG 0x79
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#define MSR_IA32_BIOS_SIGN_ID 0x8b
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// -- CPU Descriptor tables
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typedef enum {
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CPU_DT_CODE_IDTR = 0x0,
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CPU_DT_CODE_GDTR = 0x1,
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CPU_DT_CODE_LDTR = 0x2,
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} DTR_CODE;
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#pragma pack(1)
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typedef struct _DESCRIPTOR_TABLE_RECORD {
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UINT16 limit;
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//UINT32 base_hi;
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//UINT32 base_lo;
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ULONG_PTR base;
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} DESCRIPTOR_TABLE_RECORD, *PDESCRIPTOR_TABLE_RECORD;
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#pragma pack()
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#endif // CPU_H
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