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https://github.com/chipsec/chipsec
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CHIPSEC
ac2ca7264f
UEFI shell. 2. Decompression of images in SPI flash parsing is only supported in Windows. 3. UEFI - Support for IA32 and i586 (Quark) 4. Added capability to use modules from an arbitrary path with the -I / --import command line option 5. Module functionality encapsulated in class inheriting BaseModule 6. Fixed loading platform specific configuration 7. Fixed issue with modules which run on multiple logical CPUs hanging on Bay Trail (Windows/Linux). The issue still exist when running from UEFI shell 8. Added template for a module - module_template.py 9. Added options to flush log files 10. Added ability to define custom platforms Driver changes: 1. Windows - Added IOCTL_ALLOC_PHYSMEM to allocate physical memory buffer 2. Linux - Fix wrpci defect
94 lines
3.5 KiB
Python
94 lines
3.5 KiB
Python
#!/usr/local/bin/python
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#CHIPSEC: Platform Security Assessment Framework
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#Copyright (c) 2010-2014, Intel Corporation
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#
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#This program is free software; you can redistribute it and/or
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#modify it under the terms of the GNU General Public License
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#as published by the Free Software Foundation; Version 2.
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#
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#This program is distributed in the hope that it will be useful,
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#but WITHOUT ANY WARRANTY; without even the implied warranty of
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#MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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#GNU General Public License for more details.
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#
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#You should have received a copy of the GNU General Public License
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#along with this program; if not, write to the Free Software
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#Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301, USA.
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#
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#Contact information:
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#chipsec@intel.com
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#
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# -------------------------------------------------------------------------------
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#
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# CHIPSEC: Platform Hardware Security Assessment Framework
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# (c) 2010-2012 Intel Corporation
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#
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# -------------------------------------------------------------------------------
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## \addtogroup hal
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#
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# chipsec/hal/interrupts.py
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# ===============================================
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# Functionality encapsulating interrupt generation
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# CPU Interrupts specific functions (SMI, NMI)
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# ~~~
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# #usage:
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# send_SMI_APMC( 0xDE )
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# send_NMI()
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# ~~~
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# \TODO IPIs through Local APIC??
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#
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__version__ = '1.0'
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import struct
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import sys
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from chipsec.logger import *
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from chipsec.cfg.common import *
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SMI_APMC_PORT = 0xB2
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NMI_TCO1_CTL = 0x8 # NMI_NOW is bit [8] in TCO1_CTL (or bit [1] in TCO1_CTL + 1)
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NMI_NOW = 0x1
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class Interrupts:
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def __init__( self, cs ):
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self.cs = cs
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def send_SW_SMI( self, SMI_code_port_value, SMI_data_port_value, _rax, _rbx, _rcx, _rdx, _rsi, _rdi ):
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SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
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if logger().VERBOSE:
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logger().log( "[intr] sending SW SMI: code port 0x%02X <- 0x%02X, data port 0x%02X <- 0x%02X (0x%04X)" % (SMI_APMC_PORT, SMI_code_port_value, SMI_APMC_PORT+1, SMI_data_port_value, SMI_code_data) )
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logger().log( " RAX = 0x%016X (AX will be overwridden with values of SW SMI ports B2/B3)" % _rax )
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logger().log( " RBX = 0x%016X" % _rbx )
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logger().log( " RCX = 0x%016X" % _rcx )
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logger().log( " RDX = 0x%016X (DX will be overwridden with 0x00B2)" % _rdx )
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logger().log( " RSI = 0x%016X" % _rsi )
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logger().log( " RDI = 0x%016X" % _rdi )
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return self.cs.helper.send_sw_smi( SMI_code_data, _rax, _rbx, _rcx, _rdx, _rsi, _rdi )
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def send_SMI_APMC( self, SMI_code_port_value, SMI_data_port_value ):
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SMI_code_data = (SMI_data_port_value << 8 | SMI_code_port_value)
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if logger().VERBOSE:
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logger().log( "[intr] sending SMI via APMC ports: code 0xB2 <- 0x%02X, data 0xB3 <- 0x%02X (0x%04X)" % (SMI_code_port_value, SMI_data_port_value, SMI_code_data) )
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return self.cs.io.write_port_word( SMI_APMC_PORT, SMI_code_data )
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def get_PMBASE(self):
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return (self.cs.pci.read_dword( 0, 31, 0, Cfg.CFG_REG_PCH_LPC_PMBASE ) & ~0x1)
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def get_TCOBASE(self):
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return (self.get_PMBASE() + Cfg.TCOBASE_ABASE_OFFSET)
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def send_NMI( self ):
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if logger().VERBOSE:
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logger().log( "[intr] sending NMI# through TCO1_CTL[NMI_NOW]" )
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tcobase = self.get_TCOBASE()
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return self.cs.io.write_port_byte( tcobase + NMI_TCO1_CTL + 1, NMI_NOW )
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